WO2005041457A1 - Ofdm送受信装置 - Google Patents
Ofdm送受信装置 Download PDFInfo
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- WO2005041457A1 WO2005041457A1 PCT/JP2004/014721 JP2004014721W WO2005041457A1 WO 2005041457 A1 WO2005041457 A1 WO 2005041457A1 JP 2004014721 W JP2004014721 W JP 2004014721W WO 2005041457 A1 WO2005041457 A1 WO 2005041457A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2626—Arrangements specific to the transmitter only
Definitions
- the present invention relates to an OF DM transmission / reception apparatus applied to an orthogonal frequency division multiplexing (hereinafter referred to as OFDM) transmission method used in a wireless communication system.
- OFDM orthogonal frequency division multiplexing
- OFDM is a type of multi-carrier modulation scheme, and is characterized in that it is more resistant to multipath fading that occurs when propagation paths are complicated by an obstacle than conventional single-carrier modulation schemes.
- the first countermeasure is reception based on multipath fading based on propagation path characteristics of each subcarrier between the transmitting side (shown left) and the receiving side (shown right).
- This is a subcarrier transmission power control system that adjusts the transmission power of each subcarrier in a manner to compensate for the power attenuation.
- the attenuation of received power is large due to multipath fading, the subcarrier is low, the modulation scheme with multiple levels is small, the subcarrier is high, This is an adaptive modulation scheme that transmits with a multi-level modulation scheme.
- multilevel transmission power is used to perform adaptive modulation and adjust the transmission power of subcarriers transmitting data so as to obtain a desired SNR. It is a control method (Multilevel Transmit Power Control: hereinafter referred to as "MTPC method").
- MTPC method Multilevel Transmit Power Control
- FIG. 23 is a diagram showing a configuration example of a frame format in the case of transmission according to the OFDMZ MTPC system.
- the transmission frame 201 is composed of ten slots 202-1 to 202-10, and each slot 202-1 to 202-10 is roughly divided into synchronous Z control data part 203 and And the user data unit 204.
- a channel estimation data string 205 (Channel Estimation word known to the receiving side used for channel estimation, which defines the modulation scheme of each subcarrier, which is a feature of the OFDMZ MTPC scheme, and the transmission power of each subcarrier. (Hereinafter referred to as CE)) and “modulation method information 206 (Modulation Level Information: hereinafter referred to as MLI)” for notifying the receiving side of the modulation method of each subcarrier for transmitting user data.
- Sync Z control data unit 203 is included.
- MLI is usually updated every frame.
- modulation schemes of subcarriers in the synchronous Z control data unit and transmission powers of the subcarriers are as follows.
- the transmission powers of the respective subcarriers are all made equal.
- the transmit power of each subcarrier is adjusted according to the channel quality so that the receiver can obtain the desired reception CNR for each subcarrier.
- the modulation scheme of subcarriers in the user data section and the transmission power of each subcarrier are transmitted as follows.
- the modulation scheme for each subcarrier is the modulation scheme specified by MLI in the synchronous Z control data section.
- each subcarrier is adjusted according to the quality of the propagation path so that the desired reception CNR can be obtained on the reception side for each subcarrier.
- a subcarrier hole may be used without transmitting power to subcarriers with extremely poor propagation path quality.
- FIG. 24 shows the configuration of a communication device of the OFDMZ MTPC communication system.
- the RF signal is input to the OFDMZMTPC demodulation circuit 209 through the reception antenna 211 and the RF down converter 212 which down converts the RF signal.
- the OFDMZMTPC demodulation circuit 209 converts the RF downconverter output 212 into an analog signal strength digital signal, an analog Z digital conversion circuit 213, and an output of the analog Z digital conversion circuit 213 in the slot configuration shown in FIG.
- the demultiplexer 214 separately outputs each of the CE data unit 205, the MLI symbol unit 206, and the user data symbol unit 204, and the FFT circuit 215-1-215-3 for Fourier transforming the output of the demultiplexer 214 , Fourier transform circuit 215-1: A propagation path estimation circuit 216 that compares received CE data reproduced by the reference CE data with reference CE data and estimates the quality of the propagation path of each subcarrier; and Fourier transform circuit 215-2.
- a propagation path compensation circuit 217 performs propagation path compensation on the regenerated received MLI symbol based on the estimation result of the propagation path estimation circuit 216.
- a symbol demodulation circuit 218 that demodulates MLI data from the received MLI symbols that are channel-compensated by the path compensation circuit 217, and a demodulation scheme designation circuit that designates the demodulation scheme of each subcarrier of user data based on the demodulated MLI 2 19 and a channel compensation circuit 220 for performing channel compensation based on the estimation result of the channel estimation circuit 216 with respect to the received user data symbol reproduced by the Fourier transform circuit 215-3, and the channel compensation circuit
- the symbol demodulation circuit 221 demodulates the reception user data symbol subjected to propagation path compensation in 220 by the demodulation method of the user data symbol portion of each subcarrier designated by the demodulation method designation circuit 219, and the symbol portion demodulation circuit 221.
- a decoding circuit 222 for performing error correction and expansion processing on the demodulated code /
- the CE, MLI, and portions for demodulating user data can be summarized as follows.
- a user data demodulator 224 comprising two.
- the OFDMZ MTPC modulation circuit 210 includes the following configuration.
- An encoding circuit 2 26 that performs processing such as compression encoding of user data and addition of an error correction code.
- Modulation scheme A symbol modulation circuit 2 27 that modulates user data encoded by the coding circuit 226 based on the modulation scheme of each subcarrier determined by the transmission power designation circuit 225.
- a transmission power control circuit 228 which adjusts the modulation signal output of the symbol modulation circuit 227 to a value determined by the modulation scheme transmission power designation circuit 225 for each subcarrier.
- Modulation scheme MLI generation circuit 230 that generates an MLI based on the modulation scheme of each subcarrier at the time of user data transmission determined by the transmission power designation circuit 225.
- a symbol modulation circuit 231 that modulates the MLI generated by the MLI generation circuit 230.
- a transmission power control circuit 232 which adjusts the modulation signal output of the symbol modulation circuit 231 to a value determined by the modulation scheme transmission power designation circuit 225 for each subcarrier.
- a multiplexer 236 which multiplexes the outputs of the three IFFT circuits (229, 233, 235) so as to have the slot configuration of FIG.
- a digital Z analog conversion circuit 237 which converts the output of the multiplexer 236 from a digital signal to an analog signal.
- a CE modulation unit 238 configured of a CE generation circuit 234 and an IFFT circuit 235.
- MLI modulation unit 239 including MLI generation circuit 230, symbol modulation circuit 231, transmission power control circuit 232, and IFFT circuit 233.
- a user data modulation unit 240 comprising 9.
- the output of the OFDMZ MTPC modulation circuit 210 is transmitted through the up converter 241 and the transmission antenna 242.
- MLI is basic information and must be transmitted using all subcarriers. It is necessary to give a large amount of transmit power to the sub-carriers present at the drop point of the transmission path characteristic etc. so as to obtain the required reception SNR.
- the transmission power control circuit controls the power by changing the amplitude by multiplying the coefficient according to the transmission power designation signal
- the transmission power control circuit is a digital circuit, and therefore the multiplication coefficient and the multiplication result
- the data such as has a certain bit width. Therefore, there is a certain limit to the range in which power can be controlled.
- the present invention aims to provide an OFDM transceiver capable of improving the probability of successful MLI demodulation in a wireless communication system using the OFDMZ MTPC scheme.
- Non-Patent Document 1 2003 IEICE General Conference "Study on interference countermeasures in 1 cell repetition OFDM adaptive modulation with multilevel transmission power control ZTDM A system” Means to solve the problem
- the vector addition MLI means of the above-mentioned method 1 is characterized in that the vector addition MLI is generated using the propagation path compensated MLI symbol (method 2).
- the vector addition MLI means of method 2 is characterized by using MLI transmitted by assigning data to different subcarriers in each slot (method 3).
- the demodulator circuit is characterized in that it comprises a majority decision circuit for comparing the MLI data bit strings of a plurality of slots in the same frame to make a majority decision as a means for improving the demodulation success rate (scheme 4).
- the majority decision judging means of the system 4 is characterized by using the MLI transmitted by assigning data to different subcarriers in each slot (system 5).
- the majority decision judging means of the system 4 is characterized by using the MLI transmitted by rearranging the data bit sequence for each slot (system 6).
- the data allocation subcarrier selection means of the above-mentioned method 3 and method 5 is a subcarrier selection method characterized in that reordering is performed according to a known reordering method at the transmitter / receiver.
- the data allocation subcarrier selection means of the above-mentioned method 3 and method 5 is characterized by using the propagation path characteristic estimated from the slot sent from the receiver side (method 8).
- the data allocation subcarrier selection means of the above-mentioned method 8 is to select from among several kinds of arrays set in advance in order to reduce the amount of information for notifying the reception side of the arrangement of subcarriers to which data are allocated. It is characterized in that the optimal sequence is selected and the sequence number is notified (scheme 9).
- the data allocation subcarrier selection means of the above-mentioned method 8 can reduce the amount of information for notifying the reception side of the arrangement of subcarriers to which data are allocated, by using the arrangement of each slot in the frame.
- Several combinations are set, and among It is characterized in that the appropriate combination is selected and the combination number is notified in the first slot (scheme 10).
- the probability of successful demodulation of MLI can be improved, and there is an advantage that a decrease in data transmission efficiency as a whole system can be avoided.
- FIG. 1 is a block diagram showing a configuration of an MLI demodulation unit according to a first embodiment of the present invention.
- FIG. 2 is a flowchart showing a flow of vector addition processing operation according to the first embodiment of the present invention.
- FIG. 3 is a block diagram showing a configuration example of an MLI demodulation unit according to a second embodiment of the present invention.
- FIG. 4 is a block diagram showing a configuration example of an MLI demodulation unit according to a third embodiment of the present invention.
- FIG. 5 is a flowchart showing a flow of majority decision processing operation according to the third embodiment of the present invention.
- FIG. 6 is a diagram showing an example of majority decision processing according to the third embodiment of the present invention.
- FIG. 7 is a block diagram showing a configuration example of an MLI modulator according to a fourth embodiment of the present invention.
- FIG. 8 is a block diagram showing a configuration example of an MLI demodulation unit according to a fourth embodiment of the present invention.
- FIG. 9 is a block diagram showing a configuration example of an MLI modulator according to a fifth embodiment of the present invention.
- FIG. 10 is a block diagram showing a configuration example of an MLI demodulation unit according to a fifth embodiment of the present invention.
- FIG. 11 is a diagram showing a data allocation method according to the sixth embodiment of the present invention.
- FIG. 12 is a block diagram showing a configuration example of an OFDM Z MTPC modulation circuit according to a seventh embodiment of the present invention.
- FIG. 13 A block showing an example of configuration of a data sorting unit according to the seventh embodiment of the present invention.
- FIG. 14 is a diagram showing an example of a slot format according to the seventh embodiment of the present invention.
- FIG. 15 is a flowchart showing a flow of data rearrangement processing operation according to the seventh embodiment of the present invention.
- FIG. 16 is a correspondence table of MLI symbols to subcarriers in the conventional rearrangement scheme.
- FIG. 17 is a MLI symbol-to-subcarrier correspondence table according to the eighth embodiment of the present invention.
- FIG. 18 is a correspondence table of slot pair reordering scheme combinations according to the ninth embodiment of the present invention.
- FIG. 20 This is a spectrum in an orthogonal frequency division multiplexing system using subcarrier transmission power control.
- FIG. 21 A spectrum in an orthogonal frequency division multiplexing system using an adaptive modulation scheme.
- FIG. 22 A spectrum in an orthogonal frequency division multiplexing system using a multilevel transmission power control system.
- FIG. 23 is a diagram showing a frame format in an orthogonal frequency division multiplexing system using a multilevel transmission power control system.
- FIG. 24 A communication device of an orthogonal frequency division multiplexing system using a conventional multilevel transmission power control system.
- FIG. 1 is a diagram showing a configuration example of the MLI demodulation unit according to the present embodiment.
- the MLI demodulation unit 100 generates an error based on an error detection code or the like from the MLI vector addition unit 101 that performs vector addition of the MLI symbol unit output from the demultiplexer 214 and the output signal of the symbol demodulation circuit 218.
- the MLI vector addition unit 101 stores the output of the vector addition circuit 102 for performing vector addition of the output of the demultiplexer 214 and the output of the memory circuit 103, and the output of the vector addition circuit 102. And a switching circuit 104 for switching the output of the demultiplexer 214 and the output of the vector addition circuit 102.
- FIG. 2 is a flowchart showing the flow of the vector calculation process. The operation of the beta addition processing when the Nth slot after MLI modulation is received will be described according to the flowchart of FIG. 2 with reference to FIG.
- the switching circuit 104 is set to output the output signal of the demultiplexer 128 !.
- step S1 the Nth slot is received in step S1 and the received MLI in the Nth slot is demodulated (step S2).
- the error detection circuit 102 determines whether or not the MLI has successfully demodulated the power (step S3). As a result of the determination in step S3, when it is determined that the MLI demodulation has failed, the switching circuit 104 is switched to the vector addition circuit 102 side (step S4).
- Vector calculation circuit 102 includes an MLI symbol portion of the Nth slot output from demultiplexer 214 and an MLI symbol portion from the 1st slot stored in storage circuit 103 to the (N-1) th slot.
- the vector calculation result of the vector calculation is performed (step S5).
- the storage circuit 103 stores the result of vector addition of the MLI symbol part from the first slot to the Nth slot, which is output from the vector addition circuit 102 (step S6).
- the vector addition results are demodulated (step S7).
- the switching circuit 104 is switched to the multiplexer 214 (step S8).
- the error detection circuit 105 determines whether the vector addition result has been correctly demodulated (step S9).
- step S 9 If it is determined in step S 9 that the demodulation of the vector addition result has failed, the process returns to step S 1 to receive the next (N + 1) -th slot. After that, it operates according to the above rules. As a result of the determination in step S3 and step S9, when it is determined that the demodulation is successful, the data stored in the memory circuit 103 is discarded (step S10). If the MLI demodulation succeeds, the user data in the slot in the same frame is demodulated using that MLI. When the next frame is received, the MLI is demodulated again in the above manner.
- the MLI of each slot in the same frame is the same, while the noise components included in those slots have no correlation. Therefore, by performing vector addition, only the desired signal power can be strengthened, and the SNR can be improved.
- FIG. 3 is a book It is a figure which shows the structural example of the MLI demodulation part 106 by embodiment.
- MLI vector addition section 107 performs vector addition of the MLI symbol section output from propagation path compensation circuit 217. Since the propagation path changes with time, the amount of phase rotation that each slot receives in the propagation path is different.
- the demodulation unit according to the present embodiment compensates for the rotation of the phase with the propagation path compensation circuit and adds the force vectors, so that the desired signal can be efficiently added compared to the first embodiment. The amount of improvement is significant.
- FIG. 4 is a diagram showing a configuration example of the MLI demodulation unit 108 according to the present embodiment.
- the MLI demodulation unit 108 includes a majority decision unit 119 that determines the symbol-demodulated MLI by majority.
- Majority determination section 109 determines majority determination circuit 110 which determines the output of symbol demodulation circuit 218 and the output of storage circuit 111 by majority determination, storage circuit 111 storing the output of symbol demodulation circuit 218, and And a switching circuit 112 that switches between the output of the symbol demodulation circuit 218 and the output of the majority decision circuit 110.
- FIG. 5 is a flowchart showing the flow of the majority decision processing operation. The flow of the majority decision process when the Nth slot is received will be described along the flow chart shown in FIG. At the start of the demodulation operation, the switching circuit 112 is set to output the symbol demodulation circuit output signal 218.
- step S11 the Nth slot is received.
- step S12 the received MLI of the Nth slot is demodulated.
- the error detection circuit 105 determines whether the MLI has been correctly demodulated (step S13). If it is determined in step S13 that the MLI demodulation has failed, it is determined whether the slot number N is even or odd (step S14). By performing the determination in step S14, the slot that has been correctly demodulated when N is even and the incorrect slot become the same number, and it becomes impossible to make the determination by majority decision, so it is meaningful to avoid the situation. If it is determined in step S14 that N is an even number, the process returns to step S11, and the next (N + 1) th slot is received.
- the switching circuit 112 is switched to the majority decision circuit 110 (step S15).
- the majority decision circuit 110 stores the N-th slot MLI output from the symbol modulation circuit 218 and the storage circuit 111.
- Each bit with the MLI from the existing first slot to the (N ⁇ 1) slot is subjected to majority decision (step S16).
- the method of majority decision for the first to seventh seven slots will be described with reference to FIG.
- the storage circuit 111 additionally stores the MLI output from the symbol demodulation circuit 218 (step S17), and demodulates the majority decision result (step S18).
- the switching circuit 112 is switched to the symbol demodulation circuit 218 (step S19), and the error detection circuit 105 determines whether the majority decision result is correctly demodulated (step S20).
- the process returns to step S11, and the (N + 1) th slot is received. Thereafter, the operation is performed in accordance with the above rules.
- step S21 the data stored in the memory circuit 111 is discarded (step S21). If the MLI is successfully demodulated, user data in slots in the same frame is demodulated using that MLI. When the next frame is received, MLI demodulation is performed again by the above method.
- FIG. 7 is a diagram showing a configuration example of the MLI modulation unit 113 according to the present embodiment.
- the MLI modulation unit 113 includes an MLI generation circuit 230, a data rearrangement circuit 114 that rearranges bit strings output from the MLI generation circuit 230, a symbol modulation circuit 231, a transmission power control circuit 232, and an IFFT circuit 233. And. A signal is output from the IFFT circuit 233 to the multiplexer.
- FIG. 8 is a diagram showing a configuration example of the MLI demodulation unit 115 according to the present embodiment.
- the MLI demodulation unit 115 rearranges the MLI, which has been symbol-demodulated and has become a bit string, in the reverse order of the transmission procedure, and puts it in the original order.
- a data rearrangement circuit 116 is provided.
- MLI is basic information
- the bit sequence of M LI is rearranged for each slot and transmission is performed. Since the SNR is low and the bits transmitted on subcarriers are different in each slot, when demodulation and rearrangement are performed in the original order, the position at which error bits appear is different in each S slot. Therefore, the error correction ability of the majority decision is extremely excellent against such an error, so that there is an advantage that the MLI demodulation success probability can be improved.
- FIG. 9 is a diagram showing a configuration example of the MLI modulation unit 117 according to the present embodiment.
- the MLI modulator 117 according to the present embodiment is characterized in that it comprises a data reordering circuit 118 for reordering the output from the symbol modulation circuit 231.
- FIG. 10 is a diagram showing a configuration example of the MLI demodulation unit 119 according to the present embodiment.
- the MLI demodulation unit 119 rearranges the propagation path compensated MLI symbols in the reverse procedure to that for transmission, and restores the data to the original order.
- a replacement circuit 120 is provided.
- the SNR of the MLI symbol transmitted in the subcarrier over several slots is bad. Therefore, even if vector power calculation is performed, the amount of improvement in the SNR of the M LI symbol is small, which becomes a bottleneck of the MLI demodulation success probability.
- FIG. 11 is a diagram showing an assignment method when the number of subcarriers in the present embodiment is 32.
- the symbols dl to d32 shown in FIG. 11 are MLI symbols. Also, let SC1-SC32 be the subcarrier number.
- the reordering method when transmitting the second slot is as follows.
- the subcarrier is divided into two blocks of SC1-SC16 and SC17-SC32, which are respectively referred to as a first block and a second block.
- the MLI symbol transmitted in the first block when transmitting the first slot is assigned to the second block.
- the rearrangement scheme when transmitting the third slot is as follows.
- the subcarrier is divided into four blocks of SC1-SC8, SC9-SC16, SC17-SC24, and SC25-SC32, which are respectively referred to as a first block, a second block, a third block, and a fourth block.
- the third slot is divided into eight blocks, and the fourth slot is divided into 16 blocks, and MLI symbols are similarly allocated. If the number of blocks can not be divided equally, the remaining subcarriers are assigned to any block. In this embodiment, the number of subcarriers is equally divided and divided into blocks, and those blocks are allocated as a pair of two. MLI symbol replacement force is obtained. A similar effect can be obtained.
- the alternative method is not limited to the above-described method.
- This embodiment is one of the MLI symbol reordering methods performed by the data reordering circuit according to the fifth embodiment, and is characterized in that reordering is performed based on the propagation path estimation result.
- FIG. 12 is a diagram showing a configuration example of the OFDM Z MTPC modulation circuit 121 according to the present embodiment.
- the OFDMZMTPC modulation circuit 121 is a data specifying a data reordering method of the data reordering circuit based on the propagation path estimation result for each subcarrier of the propagation path estimation circuit 216 (FIG. 24) of the OFDMZMTPC demodulation circuit 209 (FIG. 24).
- the signal generation circuit 123 for generating a signal and the signal generated in the signal generation circuit 123 are modulated.
- FIG. 13 is a diagram showing a configuration example of the data rearrangement designation unit 122. As shown in FIG. As shown in FIG. 13, the data reordering specification unit 122 measures the power per subcarrier of the propagation path estimation result output from the propagation path estimation circuit 216 (FIG. 24) of the OFDMZMTPC demodulation circuit 209 (FIG. 24).
- Power calculation circuit 128 to be calculated data sorting circuit 129 that rearranges the output signals of power calculation circuit 128 in subcarrier order as well as data, the output signal of data sorting circuit 129 and the output signal of storage circuit 131
- the addition circuit 130 that adds the data
- the storage circuit 131 that stores the output signal of the addition circuit 130
- the data arrangement that specifies the MLI symbol rearrangement method from the output signal of the addition circuit 130 and the output signal of the power calculation circuit 128
- a replacement designation circuit 132 a replacement designation circuit 132.
- a frame format in the present embodiment is shown in FIG.
- Signal subframe 133 is inserted to indicate the sort order of the MLI symbols.
- the data reordering specification circuit 132 internally has a table in which subcarrier numbers and MLI symbol numbers correspond to each other.
- Sub carrier number column at present The subcarrier power of the propagation path estimation result of the channel number is sequentially written in the subcarrier power, and the MLI symbol number column indicates the MLI symbol number in order from the MLI symbol estimated that the transmit / receive power of the slot transmitted so far is small.
- Write The data rearrangement specification circuit 132 specifies the rearrangement scheme to assign the MLI symbol to the corresponding subcarrier on the table.
- the table is sequentially updated each time a slot is transmitted.
- FIG. 15 is a flowchart showing the flow of the operation of the data rearrangement designation unit.
- the operation of the data reordering unit 122 at the time of Nth slot transmission will be described with reference to this flowchart.
- the power calculation circuit 128 takes the latest propagation path estimation result output from the propagation path estimation circuit 216 (FIG. 24) of the OFDMZMTPC demodulation circuit 209 (FIG. 24) as the propagation path estimation result at the time of the Nth slot transmission.
- the power of the propagation path estimation result for each subcarrier is calculated (step S31).
- the subcarriers are rearranged in descending order of the power of the propagation path estimation result, and the subcarrier numbers are written in the table (step S32).
- the data reordering specification circuit 132 specifies the reordering method so as to assign the MLI symbols to the corresponding subcarriers on the table (step S33).
- the data sorting circuit 231 sorts the MLI symbols in accordance with the data sorting designation signal (step S34).
- the data reordering circuit 129 reorders the power of the propagation path estimation result according to the data reordering designation signal. This corresponds to reordering the power of the channel estimation result at the time of Nth slot transmission in the order of MLI symbols (step S35).
- Adder circuit 130 calculates the power of the propagation path estimation result at the time of Nth slot transmission output from data reordering circuit 129 and the received power estimation value up to the (N-1) th slot output from storage circuit 131. Add the sum (step S36).
- the memory circuit 131 stores the output signal of the adder circuit 130 as the sum of the reception power estimated values up to the Nth slot (step S37).
- the MLI symbols are rearranged in ascending order of the sum of received power estimated values, and the MLI symbol number is written to the table (step S38). It is determined whether the frame processing has been completed (step S39).
- step S39 If it is determined in the step S39 that the frame processing has been completed and it is determined that the frame processing is completed, the process returns to the step S31 to prepare for the transmission of the (N + 1) th slot. Hereafter, it operates according to the above-mentioned rule. If it is determined as a result of step S39 that the frame processing has been completed, the data stored in the storage circuit 131 is discarded. And reset the table to the initial value (Reset: step S40).
- the present embodiment is a kind of sorting method in the seventh embodiment, and relates to a sorting method for reducing the amount of sorting notification information.
- the number of subcarriers is 32.
- An example of the sorting order notification information at this time is shown in FIG. From the left, correspondence between subcarrier numbers and data numbers at the time of transmission of the first slot, transmission of the second slot, and transmission of the third slot is shown.
- the present embodiment eight types of rearrangement methods up to 18 shown in FIG. 17 are set in advance as the rearrangement method, and this rearrangement method is also known on the receiving side.
- data rearrangement is performed so as to assign the MLI symbols to the corresponding subcarriers on the table, but in the present embodiment, after considering the created table, Select the most appropriate sorting method out of the set 8 sorting methods, and sort according to the sorting method.
- the subcarrier sort order notification information it is possible to transmit the sort method number of 3 bits (represented by "000", "0 0 ": L 11 "in FIG. 17) shown in the table. There is an advantage that the sort order notification information can be significantly reduced.
- the present embodiment is a sort of sorting method in the eighth embodiment, and is a sorting method for reducing the amount of sorting notification information.
- the subcarriers The number is 32 and 10 slots are one frame.
- eight combinations are set as shown in FIG. 18 as a combination of the reordering method performed in each slot up to the 10th slot also in the first slot power, and this reordering method is known on the receiving side as well.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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GB2428934A (en) * | 2005-07-26 | 2007-02-07 | Ovus Ltd | Orthogonal Frequency Division Multiplex (OFDM) Repeaters |
WO2009017225A1 (ja) * | 2007-08-02 | 2009-02-05 | Sharp Kabushiki Kaisha | 受信装置、通信システム及び受信方法 |
JP2012157015A (ja) * | 2006-07-28 | 2012-08-16 | Qualcomm Inc | ワイヤレス通信システムにおけるデータ伝送のためのシグナリングを送信する方法および装置 |
CN108574962A (zh) * | 2017-03-09 | 2018-09-25 | 中兴通讯股份有限公司 | 数据发送、接收方法及装置 |
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GB2428934A (en) * | 2005-07-26 | 2007-02-07 | Ovus Ltd | Orthogonal Frequency Division Multiplex (OFDM) Repeaters |
JP2012157015A (ja) * | 2006-07-28 | 2012-08-16 | Qualcomm Inc | ワイヤレス通信システムにおけるデータ伝送のためのシグナリングを送信する方法および装置 |
US8902861B2 (en) | 2006-07-28 | 2014-12-02 | Qualcomm Incorporated | Method and apparatus for sending signaling for data transmission in a wireless communication system |
WO2009017225A1 (ja) * | 2007-08-02 | 2009-02-05 | Sharp Kabushiki Kaisha | 受信装置、通信システム及び受信方法 |
CN108574962A (zh) * | 2017-03-09 | 2018-09-25 | 中兴通讯股份有限公司 | 数据发送、接收方法及装置 |
CN108574962B (zh) * | 2017-03-09 | 2023-01-24 | 中兴通讯股份有限公司 | 数据发送、接收方法及装置 |
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