WO2005036612A3 - Ferroelectric capacitor with a complex-oxide hard-mask top electrode and method for manufacturing the same - Google Patents
Ferroelectric capacitor with a complex-oxide hard-mask top electrode and method for manufacturing the same Download PDFInfo
- Publication number
- WO2005036612A3 WO2005036612A3 PCT/JP2004/014287 JP2004014287W WO2005036612A3 WO 2005036612 A3 WO2005036612 A3 WO 2005036612A3 JP 2004014287 W JP2004014287 W JP 2004014287W WO 2005036612 A3 WO2005036612 A3 WO 2005036612A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- manufacturing
- complex
- same
- top electrode
- ferroelectric capacitor
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
The present invention provides a method for manufacturing a semiconductor device equipped with a capacitor (3, 4, 5) in which a ferroelectric dielectric film (4) is used, wherein a complex oxide such as SrRuO3 is used as a mask material when the dielectric film is etched.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-336023 | 2003-09-26 | ||
JP2003336023A JP2005108876A (en) | 2003-09-26 | 2003-09-26 | Semiconductor device and its manufacturing process |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005036612A2 WO2005036612A2 (en) | 2005-04-21 |
WO2005036612A3 true WO2005036612A3 (en) | 2005-06-02 |
Family
ID=34430931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/014287 WO2005036612A2 (en) | 2003-09-26 | 2004-09-22 | Ferroelectric capacitor with a complex-oxide hard-mask top electrode and method for manufacturing the same |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2005108876A (en) |
WO (1) | WO2005036612A2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4596167B2 (en) * | 2006-02-24 | 2010-12-08 | セイコーエプソン株式会社 | Capacitor manufacturing method |
JP4553143B2 (en) * | 2006-02-24 | 2010-09-29 | セイコーエプソン株式会社 | Method for manufacturing piezoelectric actuator, ink jet recording head |
JP2008078417A (en) * | 2006-09-21 | 2008-04-03 | Toshiba Corp | Semiconductor memory device and manufacturing method thereof |
JP5347381B2 (en) * | 2008-08-28 | 2013-11-20 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
JP5549913B2 (en) * | 2009-09-01 | 2014-07-16 | 株式会社リコー | Method for manufacturing electromechanical transducer |
JP2014054802A (en) * | 2012-09-13 | 2014-03-27 | Ricoh Co Ltd | Electromechanical conversion element, droplet discharge head and droplet discharge device |
JP6347084B2 (en) | 2014-02-18 | 2018-06-27 | アドバンストマテリアルテクノロジーズ株式会社 | Ferroelectric ceramics and method for producing the same |
EP4190947A4 (en) * | 2020-07-28 | 2024-01-17 | Fujifilm Corp | Piezoelectric film-equipped substrate and piezoelectric element |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5650362A (en) * | 1993-11-04 | 1997-07-22 | Fuji Xerox Co. | Oriented conductive film and process for preparing the same |
US5889299A (en) * | 1996-02-22 | 1999-03-30 | Kabushiki Kaisha Toshiba | Thin film capacitor |
EP1039525A1 (en) * | 1997-11-10 | 2000-09-27 | Hitachi, Ltd. | Dielectric element and manufacturing method therefor |
JP2001144266A (en) * | 1999-11-11 | 2001-05-25 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method therefor |
US20020004249A1 (en) * | 2000-06-30 | 2002-01-10 | Takashi Kawakubo | Semiconductor memory device and manufacturing method thereof |
US6423592B1 (en) * | 2001-06-26 | 2002-07-23 | Ramtron International Corporation | PZT layer as a temporary encapsulation and hard mask for a ferroelectric capacitor |
US20020154532A1 (en) * | 2001-03-21 | 2002-10-24 | Hiromu Miyazawa | Ferroelectric memory element and electronic apparatus |
WO2003021656A2 (en) * | 2001-08-31 | 2003-03-13 | Infineon Technologies Ag | Improved material for use with ferroelectrics |
US20030058700A1 (en) * | 2001-06-29 | 2003-03-27 | Rainer Bruchhaus | Method for fabricating a semiconductor memory device |
US20030071294A1 (en) * | 2001-02-28 | 2003-04-17 | Shan Sun | Process and structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits |
US20030128570A1 (en) * | 2001-10-31 | 2003-07-10 | Masahiro Tanaka | Digital to analog converter including a ferroelectric non-volatile semiconductor memory, and method for converting digital data to analog data |
US6610549B1 (en) * | 1999-03-05 | 2003-08-26 | University Of Maryland, College Park | Amorphous barrier layer in a ferroelectric memory cell |
-
2003
- 2003-09-26 JP JP2003336023A patent/JP2005108876A/en active Pending
-
2004
- 2004-09-22 WO PCT/JP2004/014287 patent/WO2005036612A2/en active Application Filing
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5650362A (en) * | 1993-11-04 | 1997-07-22 | Fuji Xerox Co. | Oriented conductive film and process for preparing the same |
US5889299A (en) * | 1996-02-22 | 1999-03-30 | Kabushiki Kaisha Toshiba | Thin film capacitor |
EP1039525A1 (en) * | 1997-11-10 | 2000-09-27 | Hitachi, Ltd. | Dielectric element and manufacturing method therefor |
US6610549B1 (en) * | 1999-03-05 | 2003-08-26 | University Of Maryland, College Park | Amorphous barrier layer in a ferroelectric memory cell |
JP2001144266A (en) * | 1999-11-11 | 2001-05-25 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method therefor |
US6756262B1 (en) * | 1999-11-11 | 2004-06-29 | Hitachi, Ltd. | Semiconductor integrated circuit device having spaced-apart electrodes and the method thereof |
US20020004249A1 (en) * | 2000-06-30 | 2002-01-10 | Takashi Kawakubo | Semiconductor memory device and manufacturing method thereof |
US20030071294A1 (en) * | 2001-02-28 | 2003-04-17 | Shan Sun | Process and structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits |
US20020154532A1 (en) * | 2001-03-21 | 2002-10-24 | Hiromu Miyazawa | Ferroelectric memory element and electronic apparatus |
US6423592B1 (en) * | 2001-06-26 | 2002-07-23 | Ramtron International Corporation | PZT layer as a temporary encapsulation and hard mask for a ferroelectric capacitor |
US20030058700A1 (en) * | 2001-06-29 | 2003-03-27 | Rainer Bruchhaus | Method for fabricating a semiconductor memory device |
WO2003021656A2 (en) * | 2001-08-31 | 2003-03-13 | Infineon Technologies Ag | Improved material for use with ferroelectrics |
US20030128570A1 (en) * | 2001-10-31 | 2003-07-10 | Masahiro Tanaka | Digital to analog converter including a ferroelectric non-volatile semiconductor memory, and method for converting digital data to analog data |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 22 9 March 2001 (2001-03-09) * |
Also Published As
Publication number | Publication date |
---|---|
WO2005036612A2 (en) | 2005-04-21 |
JP2005108876A (en) | 2005-04-21 |
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