WO2004107587A1

WO2004107587A1 - Parallel encoding of cyclic codes

Info

Publication number: WO2004107587A1
Application number: PCT/EP2003/005638
Authority: WO
Inventors: Jürgen LERZER
Original assignee: Telefonaktiebolaget L M Ericsson (Publ)
Priority date: 2003-05-28
Filing date: 2003-05-28
Publication date: 2004-12-09
Also published as: AU2003245898A1

Abstract

A method and logic circuit for systemtic encoding of cyclic (n, k) block codes are described. The K information symbols are processed in tuples of p symbols, i.e.p information symbols are processed in parallel by the method and the circuit. This allows the logic circuit to merge p shift operations within a single clock cycle and to generate (n-k) parity symbols in K/p clock cycles.

Description

PARALLEL ENCODING OF CYCLIC CODES

[Field of the invention]

The present invention relates to a method of generating code symbols in an encoder, and to a logic circuit for generating code symbols in an encoder.

[Background of the invention]

In the field of error correction coding, it is known to input a k-tuple of information symbols (IQ Ii, •••, T- -l) into an encoder and to output an n-tuple of code symbols ( C_Q , C _ , . . . i C_n_]_) , where k and n are natural numbers (positive integers) and k is smaller than n. The information symbols I and the code symbols C are elements of a Galois field GF(2^m), m being a positive integer. For example, for m = 1, the symbols are bits, representable as 0 or 1.

In a polynomial representation, the k-tuple of information symbols can be represented as a (k-1) -degree polynomial

Equally, the n-tuple of code symbols can be represented by the (n-1) -degree polynomial

c(x) = C₀+C₁x¹+C₂x²+...+C_n_₁xⁿ-¹.

The function of the encoder can be represented in terms of a so-called generator polynomial g (x) of degree (n-k) :

g(^χ) = g_ux°+_Jιx-'-+... +g_n_k_ιx^n~-' -¹-+ ^n~k. The coefficients gj_ of the generator polynomial are also elements of GF(2^m), like the information symbols I and the code symbols C.

A simple coding rule can be represented as c (x) = i (x) g (x) . However, it is generally preferable to provide a so-called systematic encoding rule, in which the higher k code symbols (^cn-l' ^cn-2' •••/ ^cn-k) ^are equal to the k-tuple of information symbols (Ijζ-i, ^Ik-2' ■••/ ^Iθ) • ^In polynomial representation, the code word therefore has a form:

c (x) = x^n_k i (x) -Ft (x) ,

where

t (x) = rem (xⁿ"-^i (x) , g (x) ) .

In other words, the function t (x) is the remainder or residue of ^n~ki (x) divided by g(x) . This is basically well known in the art and does not need to be described in further detail here .

[Object of the present invention]

The object of the present invention is to provide a method of generating an n-tuple of code symbols on the basis of a k- tuple of information symbols, which method is on the one hand fast in terms of operation speed and on the other hand simple in terms of hardware implementation.

[Summary of the present invention]

This object is achieved by the method of claim 1 and the logic circuit of claim 7. Advantageous embodiments are described in the dependent claims. In accordance with the present invention, the information symbols are grouped into p-tuples, and the processing is also achieved in terms of p-tuples, where p is a factor of (n-k) and k, and p is greater than 1. In other words (n-k) /p is an integer and k/p is an integer. Furthermore, p is smaller than k. In other words, instead of processing the information symbols in single symbol fashion, i.e. one symbol at the time, the present invention proposes processing p-tuples in parallel, but not all k information symbols at once. In this way, a significant increase in speed with respect to processing one symbol at the time is achieved, but without at the same time having the increased hardware requirements of a fully parallel processing of all k information symbols at once. For example, the processing speed can already be doubled by selecting p = 2, but the hardware requirements for implementing the corresponding methods are only slightly greater than when processing one symbol at the time.

The present method can be applied to any coding operation, regardless of the length of the information word and the length of the code word involved. If a factor p for the given lengths can be found, then the application is straightforward. However, even if the given lengths do not provide immediate factorisation, this can readily and simply be achieved by appropriately expanding the information symbols by dummy symbols (zeros) and/or expanding the generator polynomial by dummy coefficients (zeros) .

[Brief description of Figures]

The present invention will now be described in more detail with reference to the accompanying figures in which

Fig. 1 shows one example of a logic circuit employing the method of the present invention, Fig. 2 shows an example of the logic circuit of Fig. 1 for p = 2 , and

Fig. 3 shows a single symbol processing logic circuit for the purpose of comparison with the present invention.

[Detailed description of embodiments]

In order to better understand the concept of the present invention, reference is first made to a logic circuit shown in Fig. 3, which does not implement the present invention, and which operates according to the principle of single symbol processing, in order to generate the code symbols in systematic form. The figure shows an input for inputting the information symbols I, starting with I^-i in the first shift, T-k-₂ iⁿ the second shift, and so on. The logic circuit comprises single symbol or scalar multiplication units 30_, 30₂, 3O₃ and 3O₄, which serve to multiply an input symbol by an indicated coefficient g-j_ of the generator polynomial.

Furthermore, single symbol storage units 31]_, 31₂, 3I₃ and 3I₄ are shown, which serve to store intermediate coefficients that result from the processing operation of the logdc circuit. Various adders are provided including an adder 32 for adding the output of the final storage element 3I4 to an input information symbol. Furthermore, a switch 34 is provided, which is operable to connect the output for outputting the code symbols either to the input or to the output of the adder 32. By holding circuit 34 in connection with the circuit input for the first k shifts of the logic circuit, the higher k code symbols C_n_ι, ... , C_n_k are set equal to the k-tuple of information symbols (Ik-1 • • • To) ' which are input individually. Furthermore, a switch 33 is provided which is opened for the last n-k shifts, in order to correctly output the final n-k code symbols, which correspond to the above-described remainder function t (x) . The upper part of the logic circuit in Fig. 3 is based on a known circuit for dividing by g (x) , see Fig. 6.11 in chapter 6.2 of "Theory and Practice of Error Control Codes" by Richard E. Blahut, Addison- esley Publishing Company, 1983, ISBN 0-201- 10102-5.

The storage elements 3I1-3I4, of which there generally are (n-k) store intermediate values h, which can be represented as :

h(x,i) = h₀ (i)+h_x (i)x¹+h₂ (i)x²+...+h_n_k_₁ (i) χn-k-1.

i represents the shift count. In other words, the coefficient hg (i) is to be found after the i-th shift in the lowest storage element 31]_, h]_ (i) is to be found in the next-to-left most storage element 312 after the i-th shift, etc. After k shifts h(x,k) equals t (x) . The logic circuit of Fig. 3 requires overall n shifts in order to generate the n-tuple of code symbols.

In contrast thereto, the concept of the present invention comprises on the one hand setting the higher k code symbols

C_n-l_>C_n_2 • • • Cjj.jj. equal to the k-tuple of information symbols

Ik-l>Ik-2' ■■■/!()' i-ⁿ o der to provide the code words in systematic form, but recursively calculating (n-k) /p p-tuples of intermediate coefficients h_j in k/p consecutive steps i', such that the following relationship is fulfilled:

h ^1}(i') = D^ •(F^(pxp) • (h ii '-1) +/ ^(i ')))+h_j' O'-l)

where q = n-k ,

represents a j ' -th p-tuple of intermediate coefficients after the i'-th step in (pxl) vector form,

represents a p-tuple of information symbols associated with the i'-th step in (pxl) vector form,

gj'p+p-1 gj'p+p-2 gj'p+2 gj'p+1 Sj'p gj'p+p-2 gj'p+p-3 gj'p+1 gj'p gj'p-1

_D(P^XP) _ • • j' gj'p+2 gj'p+1 gj'p-p+5 gj'p-p+4 gj'p-p+3 gj'p+1 . gj'p gj'p-p+4 gj'p-p+3 gj'p-p+2

1 S^j'P gj'p-1 gj'p-p+3 gj'p-p+2 gj'p-p+1 is a (pxp) matrix representation comprising the coefficients g of the generator polynomial, associated with the j ' -th p- tuple of intermediate coefficients, ^v\,2 ^Fl,p-2 tl,p-l ^Fl,

^F2,l ^2,2 ^F2,p-2 ^?2,p-l -2,P p(P^xP) _ fp-2,1 ^p-2,2 ^Fp-2,p-2 ^Fp-2,p-l ^Fp-2,p Fp-1,1 ^Fp-1,2 ^Fp-l,p-2 ^Fp-l,p-l ^Fρ-l,p

^1 ^PP,2 ^LP,P^" Pp,p-1 ^LP>P is a (pxp) matrix representation comprising coefficients g of the generator polynomial, where

p-a-l

^■a,l / iOα-D+a+b P-b,l for a=l,2 ,p-l

6=0

^a,c -^a+l,c-l for a=l,2,...,p and c=2,3, -P

R =0 Vx>l

^FP,1 ⁼¹ and setting the lower (n-k) code symbols C_n.j_c.ι,C_n.]_c.2, • • ■ , Co equal to the (n-k) intermediate coefficients ( h_j ) provided after k/p steps.

As can be seen, in accordance with the present invention, the above-mentioned intermediate coefficients h are grouped into p-tuples, just as the information symbols i are equally grouped into p-tuples. Therefore, it is possible to perform the coding operation in overall n/p steps.

The restriction that both n and k are divisible by p is not a _^ limitation with respect to the types of codes that may be used in connection with the concept of the present invention. Namely, it is very easily possible to expand the given number of information symbols to an appropriate k-tuple by adding dummy symbols (zeros) for the higher or more significant symbols in the k-tuple, and/or adding dummy coefficients

(zeros) at the lower or less significant end of the generator polynomial . In this way, appropriate numbers n and k can be provided, even when departing from an arbitrary initial code that has a number of information symbols and a number of code symbols that do not allow immediate factorisation. This shall be explained more closely in the following.

As an example, if a (n',k) code is given, and no desired factor is available for n' and k, one can expand the generator polynomial in the following way. One chooses n=n'+d, where d is a positive integer such that p is a factor of n and k. The above mentioned generator polynomial of degree (n-k) is then an expanded generator polynomial, and the (n-k) coefficients go_>gι, / • • ■ gn-k-1 °f said expanded generator polynomial g (x) are derived from the (n'-k) coefficients of the actual generator polynomial associated with the (n',k) code in the following way: the higher (n'-k) coefficients gd^gd+l • • • / gn-k-1 °f said first generator polynomial are identical to the coefficients of said second polynomial, and the lower d coefficients grjj i / • • • gd-l ^OI said first generator polynomial are all equal to zero. After applying the method with the expanded generator polynomial , of the lower (n-k) code symbols C_n.]_£.ι,C_rι.]_!-.2, • • ■ CQ equal to the (n-k) intermediate coefficients (h_j) provided after k/p steps, the lowest most d code symbols C^-i , ... , C_Q are dropped, in order to thereby provide the n' -tuple of code symbols associated with the actual (n',k) code.

Additionally or alternatively, one can also expand the number of information symbols with dummy symbols. The actual given code is referred to as (n", k') . The k-tuple of information symbols IQ-II , ... , Ik-l to be used is derived from the k' -tuple of actual information symbols IQ I # ... , Ik'-l where k=k'+e and e is a positive integer such that p is a factor of k, and the lower k' information symbols of the k-tuple of expanded information symbols are identical to the k' -tuple of actual information symbols, and the higher e information symbols I_k' _k'+_l i • • ■ i I -₁ °f the k-tuple of expanded information symbols are all equal to zero. The (n-k) coefficients g₀,gι /■••/g_n-_k-₁ °f ^an expanded generator polynomial g (x) are derived from the (n"-k') coefficients of the actual generator polynomial associated with the (n",k') code, where n=n"+2e.

The higher (n"-k') coefficients g_e,g_e+ι , ... , g_n-_k-i of the first generator polynomial are identical to the coefficients of said second polynomial, and the lower e coefficients gø,g_l , ... , g_e_ι of said first generator polynomial are all set to zero. After processing, of the lower (n-k) code symbols C_n-_k-_l'C_n-_k-₂' ■ • • Co equal to the (n-k) intermediate coefficients h_j provided after k/p steps, the lowest most e code symbols C_e_ι , ... , CQ are dropped, and of the higher k code symbols C_n_ι,C_n_₂ • • • C_n__k the highest e code symbols C_n.ι,C_n_₂, ... , C_n_ι__e are dropped, in order to provide an n" -tuple of code symbols associated with the actual (n",k') code.

It is noted that the present invention can be employed in connection with any type of linear block coding, but is preferably applied in the context of BCH encoders.

Now an example of a logic circuit for implementing the above- described methods will be described with reference to Fig. 1.

A logic circuit for generating the n-tuple of code symbols

C₀,C_j , ... , C_n__! in an encoder is shown, comprising: a circuit input for receiving the information symbols

I_θ,Iι , ... , -_\ in p-tuples and a circuit output for outputting the code symbols C_n_ι,C_n_₂ / • • • , C_Q.J_J. in p-tuples. q/p first to q/p-th storage elements, of which only three are shown and referred to as 10^ 10₂, 10₃, for each storing a p-tuple of intermediate coefficients (h) are provided. In other words, p symbols are stored in parallel, q/p first to q/p-th matrix multiplication units, of which only three are shown and referred to as 11-^ 11₂, 11₃, for each conducting a multiplication of a received p-tuple by a (pxp) matrix Oγ ^ are provided. Furthermore, (q/p-1) first to (q/p-1) -th p- tuple adders are provided, of which only two are shown and referred to as 16₁ and 16₂. The lines connecting the elements are all understood to be p symbols wide, i.e. p symbols are carried in parallel.

An output of the first matrix multiplication unit ll_x is connected to an input of the first storage element 10_!, an output of said first storage element ll_x is connected to the first p-tuple adder 16₁ , an output of each of the second to q/p-th matrix multiplication units 11₂, 11₃ is connected to an input of one of the first to (q/p-1) -th p-tuple adders lβ_{ι r} 16₂, and an output of each of said first to (q/p-1) -th p-tuple adders 16₁₇ 16₂ is connected to an input of one of the second to q/p-th storage elements 10₂, 10₃.

A further p-tuple adder 13 is connected to the output of the q/p-th storage element (10₃) and the circuit input. A further matrix multiplication unit 12 for conducting a multiplication of a received p-tuple by the (pxp) matrix F^^xp is provided, the input of the further matrix multiplication unit 12 being connected to the output of the further p-tuple adder 13. A switch 15 is provided for selectively connecting the output of the further matrix multiplication unit 12 with each input of the first to q/p-th matrix multiplication units ll_x, 11₂, 11₃, controlled to be open on the last (n-k) /p shifts of operation. A switch 14 is provided for selectively connecting said circuit output with said circuit input or with the output of said further p-tuple adder 13, controlled to be connected to the input for the first k/p shifts and to the output of the adder 13 on the last (n-k) /p shifts . The general embodiment of Fig. 1 relates to arbitrary values of p. Consequently, the matrix multiplication units must be appropriately arranged, which is well known to the skilled person. As an example, Fig. 2 shows the case for a logic circuit in which p is equal to 2. As a consequence, the matrix multiplication units perform (2 x 2) multiplications, and the storage units are arranged to store 2 intermediate coefficients in parallel. The details are expressed in terms of scalar elements, i.e. elements that only carry one symbol. In other words, in this example, the shown matrix

multiplication units all comprise scalar

multipliers referred to by the factor g with which they multiply. Each storage unit j ' is shown as consisting of two scalar storage elements, each for storing a corresponding intermediate factor h., .

Although the present invention has been described in the context of specific embodiments, these are only for the purpose of illustration and are not intended to be limiting, the scope of protection being determined by the appended claims. Reference numerals in the claims are not to be seen as limiting, but only intend to make the claims easier to read.

Claims

A method for generating an n-tuple of code symbols ( C₀,C_l , . . . , C_n__x ) in an encoder, n being a natural number, on the basis of a k-tuple of information symbols do,Iι / • • • / Ik-i ) / k being a natural number smaller than n, and an (n-k) -tuple of coefficients (go, ι /••■/ gn-k-1 ) °f ^a generator polynomial (g (x) ) , comprising:

- setting the higher k code symbols (C_n_ι,C_n_2_/ 'n-k equal to the k-tuple of information symbols dk-l'¹^' ... In) /

- recursively calculating (n-k) /p p-tuples of intermediate coefficients (h_j) in k/p consecutive steps

(i¹), p being a factor of (n-k) and k, and p>l, such that the following relationship is fulfilled:

h ^1}(i')

»(F^W •fe.₁ ¹⁾(z *-!)+/ ^ipxl)(i ^,)))+h_J ^(p_⁾(i'-l)

where q = n- ,

represents a ' -th p-tuple of intermediate coefficients after the i'-th step in (pxl) vector form,

gj'p+p-1 gj'p+p-2 gj'p+2 gj'p+1 SJ'P gj'p+p-2 gj'p+p-3 gj'p+1 gj'p gj'p-1

(pxp) ) gj'p+2 gj'p+1 gj'p-p+5 gj'p-p+4 gj'p-p+3 gj'p+1 gj'p gj'p-p+4 gj'p-p+3 gj'p-p+2

Sj'P gj'p-1 gj'p-p+3 gj'p-p+2 gj'p-p+1 is a (pxp) matrix representation comprising coefficients g of the generator polynomial, associated with the j ' -th p-tuple of intermediate coefficients,

is a (pxp) matrix representation comprising coefficients g of the generator polynomial , where p-a-l

^Fa,ι = ∑Sq-p₊a₊b -^F _P-b,ι ^for a=l , 2 , ... , p-1 b=0

^Fa,c ^=Fa+l,c-l ^for a=l,2,...,p and c=2,3,...,p

^F _P,X=0 V >l

^FP,1 ⁼¹ and

- setting the lower (n-k) code symbols

( C_n_k-i,C_n.k-25 • • • / Co) equal to the (n-k) intermediate coefficients ( h_j ) provided after k/p steps.

2. The method of claim 1, wherein the (n-k) coefficients (gO'Sl, / • • • / gn-k-1 ) ^of aid generator polynomial (g (x) ) are associated with a (n,k) code.

3. The method of claim 1, wherein said generator polynomial is a first generator polynomial, and the (n-k) coefficients (go_> ι /•••/ gn-k-1 ) °f said first generator polynomial (g(x)) are derived from (n'-k) coefficients of a second generator polynomial associated with a (n',k) code, where n=n'+d and d is a positive integer such that p is a factor of n and k, where the higher

(n'-k) coefficients ( gd>gd+l • • • / gn-k-1 ) °f said first generator polynomial are identical to the coefficients of said second polynomial, and the lower d coefficients ( O'Sl / • • • / §d-l ) °f said first generator polynomial are all equal to zero, and wherein of the lower (n-k) code symbols ( C_n_k_ι,C_n_ -2_> • • • / CQ) equal to the (n-k) intermediate coefficients (hi) provided after k/p steps, the lowest most d code symbols ( C_<} , ... , Co ) are dropped, in order to provide an n' -tuple of code symbols associated with said (n',k) code.

4. The method of claim 1, wherein

- said k-tuple of information symbols ( IQ.II , ... , I -₁ ) i^s derived from a k' -tuple of information symbols (I_Q,II , ... , I'-i) where k=k'+e and e is a positive integer such that p is a factor of k, and the lower k' information symbols of said k-tuple of information symbols are identical to said k' -tuple of information symbols, and the higher e information symbols d_k'_>I_k+_l ' ■ • • ' I_k-₁ ) °f said k-tuple of information symbols are all equal to zero,

- said generator polynomial is a first generator polynomial, and the (n-k) coefficients

( _O'S_l / • ■ ■ / g_n-_k-₁ ) °f said first generator polynomial (g(x)) are derived from (n"-k') coefficients of a second generator polynomial associated with a (n",k') code, where n"=n-2e, where the higher

(n"-k') coefficients ( g_e,g_e+ι , ... , g_n-_k-_l ) °f said first generator polynomial are identical to the coefficients of said second polynomial, and the lower e coefficients

( g_O'S_l ' ■ • • / S_e-₁ ) °f said first generator polynomial are all equal to zero, and

- wherein of the lower (n-k) code symbols

( C_n__k-i₅C_n_ __2> • • • / CQ) equal to the (n-k) intermediate coefficients (h_j) provided after k/p steps, the lowest most e code symbols ( C_e_ι , ... , CQ ) are dropped, and wherein of the higher k code symbols ( C_n_ι,C_n_₂ / • - . , C_n_k ) the highest e code symbols ( C_n_ι,C_n_₂, ■ .. , C_n_ι__e ) are dropped, in order to provide an n" -tuple of code symbols associated with said (n",k') code.

5. The method of one of claims 1 to 4, wherein said symbols and coefficients are elements of GF(2) .

6. The method of one of claims 1 to 5, wherein said encoder is a BCH encoder.

7. A logic circuit for generating an n-tuple of code symbols ( C₀,C_j , ... , C_n__ι ) in an encoder according to a method of one of claims 1 to 6, comprising:

- a circuit input for receiving said information symbols

(I₀,I_l , ... , I _ι) in p-tuples, - a circuit output for outputting said code symbols (C_n_ι,C_n_₂ , .. - , C_n_ ) in p-tuples,

- q/p first to q/p-th storage elements (10₁₇ 10₂, 10₃) for each storing a p-tuple of intermediate coefficients (h), - q/p first to q/p-th matrix multiplication units (ll^_., 11₂, 11₃) for each conducting a multiplication of a received p-tuple by a (pxp) matrix D⁽jp^xp-' ,

- (q/p-1) first to (q/p-1) -th p-tuple adders (16^ 16₂) ,

- where an output of the first matrix multiplication unit (ll_x) is connected to an input of the first storage element (lO , an output of said first storage element (ll_x) is connected to the first p-tuple adder (16. , an output of each of the second to q/p-th matrix multiplication units (11₂, 11₃) is connected to an input of one of the first to (q/p-1) -th p-tuple adders ( lβ₁ , 16₂) , and an output of each of said first to (q/p-1) -th p-tuple adders (16_x, 16₂) is connected to an input of one of the second to q/p-th storage elements (10₂, 10₃) ,

- a further p-tuple adder (13) connected to the output of the q/p-th storage element (10₃) and the circuit input ,

- a further matrix multiplication unit (12) for conducting a multiplication of a received p-tuple by the

(pxp) matrix F^^xp , the input of said further matrix multiplication unit (12) being connected to the output of said further p-tuple adder (13) ,

- a first switch (15) for selectively connecting the output of said further matrix multiplication unit (12) with each input of the first to q/p-th matrix multiplication units (ll_x, 11₂, 11₃) , and

- a second switch (14) for selectively connecting said circuit output with said circuit input or with the output of said further p-tuple adder (13) .