WO2004059851A1

WO2004059851A1 - An encoder for high rate parallel encoding

Info

Publication number: WO2004059851A1
Application number: PCT/IL2002/001053
Authority: WO
Inventors: Danny Lahav; Haim Moshe; Idan Alrod
Original assignee: Optix Networks Ltd.; Litsyn, Simon
Priority date: 2002-12-30
Filing date: 2002-12-30
Publication date: 2004-07-15
Also published as: AU2002361488A1

Abstract

A high-rate parallel Bose-Chaudhuri-Hocquenghen (BCH) encoder (200) is used for error correcting codes. The BCH encoder (200) produces the redundancy information (270) by calculating the remainder (210) of the input data by a generator polynomial. To allow parallel processing, the encoder operates in two phases: firstly, predicting the quotient (210), and secondly, calculating the remainder (220) corrrelated with the input data. This encoder implementation is particularly suitable for encoding data transmitted in high line rate networks, such as an optical networks.

Description

AN ENCODER FOR HIGH RATE PARALLEL ENCODING

FIELD AND BACKGROUND OF THE INVENTION

The present invention relates generally to encoding of data for the purpose of error detection and correction, and more particularly for the purpose of error detection and correction in data coded in accordance with a Bose-Chaudhuri-Hocquenghem (BCH) code.

A BCH code can be used for correcting error bits in input data. The BCH code is used in satellite communication links, optical networks, and similar applications where error correction can be employed to mitigate the effects of noise interference. Such a code, however, requires complex encoding and decoding algorithms. In prior art, the complex encoding and decoding algorithms have been typically implemented using special-purpose devices.

An encoder produces a parity word (i.e., redundancy information) from an input information word. The parity word together with the input information word form the codeword, which is transmitted to the destination through a communication channel. The notation for computing the parity word is based on calculating the remainder of the division of the input polynomial by a generator polynomial. Mathematically, this can be described as a "modulo operation" as follows:

R(x) = f(x x^M mod g(x); (1) where R(x) is the reminder polynomial with degree M-l, f(x) is the input information polynomial with degree K-l, and g(x) is the generator polynomial with degree M. The polynomials R(x), f(x), and g(x) are binary polynomials. The resulting codeword is of length N, where N=K+M. The mathematics underlying the BCH encoding are known to those skilled in the art of error coding, and are described in detail in "Error Correcting Codes" by W. Wesley Peterson and E. J. Weldon Jr., MIT 1972, pages 224-230 and 269-278.

Reference is now made to Fig. 1, which shows an exemplary diagram of a prior art BCH encoder 100. Encoder 100 is a serial implementation of the modulo operation, R(x) = f(x)-x^M mod g(x). Encoder 100 includes multipliers 110, shift registers 120, and exclusive-or (XOR) gates 130.The number of multipliers 110, shift registers 120, and XOR gates 130 is equal to the degree of the generator polynomial g(x). Each multiplier 110 includes an array of AND gates for a general serial encoder. In a practical case whereas the generator polynomial is provided, each multiplier 110 is replaced by a direct connection if the polynomial generator's coefficient (i.e. g,) equals to one, and eliminated if it equals to zero. In order to calculate the reminder R(x), the polynomial f(x) that has an information word as its k polynomial's coefficient is shifted into encoder 100. high order first, until the last coefficient is shifted in. After a total of K shifts, encoder 100 outputs the entire quotient on its output, and the reminder R(x) is present in shift registers 120.

This approach, however, is not suitable for parallel input and output data. To overcome this problem, suitable codewords have also been generated by look-up table encoding schemes, which serve to map the K bits of the input information to M parity bits. These M parity bits are then appended to the K bits of the input information to form a codeword uniquely associated with each input stream. Standard look-up table encoding, however, requires memory devices with 2 address locations. Such encoding schemes are thus impractical for medium length input words, and prohibitively complex and expensive when K is large. In addition, implementation of an encoder circuit at high speeds is extremely difficult, mainly because the propagation delay of the combinational logic. The high rate encoders found in the art axe usable only for data rates of up to 1 Giga bits per second (Gbps), while only relatively short codewords are employed. An example for such an encoder is provided in US Patent number 5,040,179, entitled "High Rate BCH Encoder", to Carson Chen. The encoder suggested by Chen includes storage means (e.g., read only memory (ROM)) to hold a parity matrix derived from the BCH generator matrix (i.e., the generator polynomial), a logical shift function, and a XOR gate tree. The parity matrix is of a number of rows equal to the codeword size N, and a number of columns equal to the number of parity bits M. Each clock, a column of the parity matrix is ANDed with the input bit, and the result is fed into the XOR gate tree. The XOR gate tree consolidates the N bits by combinational logic into a single bit, producing as an output a serial bit stream corresponding to the parity word of the codeword. After M clocks, the complete codeword is output. This encoder, however, uses a serial implementation, does not provide parallel output data other than through storage in a shift register, and it is not useful with long codewords. The address space required for ROM in such solutions is the code length multiplied by the redundancy length.

References relevant to prior art include US Patents Nos. 4,312,069, 4,623,999, 5,040,179 5,359,610, 5,699,368 and 5,912,905. In view of the limitations of the conventional approaches to the handling of the BCH encoding problem, it is apparent that what is needed is an approach to encode any length BCH and similar codes at speeds that are limited by the redundancy length and not by the conventional memory limitations that correspond to the code length as described in some of the above references. Furthermore, there is a need to develop encoders capable of processing data for BCH encoding at rates of lOGbps and above, in particular for the purpose of supporting the new and upcoming speeds of OTNs.

SUMMARY OF THE INVENTION According to the present invention there is provided a high rate parallel encoder for encoding an error correction code and for producing redundancy information, comprising: a first adder operative to perform a first logical operation, a quotient computation logic (QCL) connected to the first adder and operative to estimate an intermediate quotient value, a remainder computation logic (RCL) coupled to the QCL and operative to calculate an intermediate reminder, a second adder coupled to the RCL and operative to perform a second logical operation and to output second adder bit values, and a register coupled to the second adder and the RCL and operative to store the calculated intermediate reminder, whereby the encoder is operative to encode a Bose-Chaudhuri-Hocquenghem error correcting code and to produce redundancy information.

According to the present invention there is provided a parallel encoder designed to reduce the propagation delay when encoding an error correction code, the encoder capable of producing redundancy information, the encoder comprising a first adder operative to perform a first logical operation, a quotient computation logic (QCL) connected to the first adder and operative to estimate an intermediate quotient value, a buffer connected to the QCL, a remainder computation logic (RCL) coupled to the buffer and operative to calculate an intermediate reminder, a second adder coupled to the RCL and operative to perform a second logical operation and to output second adder bit values, and a register coupled to the second adder and the RCL and operative to store the calculated reminder, whereby the encoder is operative to reduce the propagation delay when encoding a Bose-Chaudhuri-Hocquenghem error correcting code and to produce redundancy information. According to the present invention there is provided an optical network device for high-rate parallel encoding, comprising a first adder coupled to an input channel and configured to receive at least one input information block through the input channel, a quotient computation logic (QCL) connected to the first adder and capable of computing an intermediate quotient, a remainder computation logic (RCL) coupled to the QCL and capable of computing an intermediate reminder, a second adder coupled to the RCL and capable of performing logical exclusive OR (XOR) operations, and a register coupled to both the RCL the second adder and configured to output an encoded output information word to an output channel, whereby the optical network device is capable of producing redundancy information correlated with the at least one input information word.

According to the present invention there is provided a method for high rate parallel encoding comprising the steps of receiving an input information word that includes a plurality of data words in a first adder, and, for each data word, performing a first logical operation in the first adder, estimating an intermediate quotient value in a quotient computation logic (QCL) connected to the first adder, calculating a intermediate reminder value in a remainder computation logic (RCL) coupled to the QCL, performing a second logical operation in a second adder coupled to the RCL, the second logical operation resulting in output second adder bit values, and storing the intermediate calculated reminder in a register coupled to the second adder and the RCL, whereby the method can be used to encode a Bose-Chaudhuri-Hocquenghem error correcting code and to produce redundancy information. BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

Figure 1 - is an exemplary diagram of serial implementation of a BCH encoder (prior art); Figure 2 - is an exemplary block diagram of a BCH encoder in accordance with one embodiment of this invention;

Figure 3 - is an exemplary flowchart describing the method for BCH encoding in accordance with one embodiment of this invention;

Figure 4 - is a diagram of the matrix representations of g(x) and g^_1(x); Figure 5 - is a step-by-step example of the encoding method and the corresponding matrices G and G^"1 that represent the implementation of the multiplication by polynomials g(x) and g(x)^"1;

Figure 6 - is an exemplary block diagram of a BCH encoder in accordance with another embodiment of this invention;

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference is now made to Fig. 2, which shows a schematic block diagram of a

BCH encoder 200, in accordance with one embodiment of this invention. Encoder 200 is a high speed encoder, which is capable of operating at speeds of 10 Gbps and beyond. Higher bit rates might be supported with the progress of silicon design technology. The design is suitable for any code length and generator length of size of at least 1,000 bits.

Encoder 200 is designed to perform parallel encoding of BCH codewords, unlike prior art BCH encoders, e.g. that disclosed in Carson (US patent number 5,040,179). That is, encoder 200 is a parallel implementation of the modulo operation, R(x) = f(x) -χ^M mod g(x). Encoder 200 produces the parity word after receiving the entire input information word. The input information word is received as 'n' consecutive words of 'p' bits each, hence, encoder 200 outputs the parity word, i.e., the redundancy information after only 'n' cycles. In comparison, in prior art solutions it would take at least 'nxp' cycles to reach the same result. In order to understand the operation of encoder 200, a brief explanation of the underlying mathematics of the encoding scheme is helpful. The aim of encoder 200 is to calculate the remainder (hereinafter "R(x)") resulting from dividing the input polynomial (hereinafter "f(x)") by the generator polynomial (hereinafter "g(x)"), i.e., performing the modulo operation described in equation (1).

Assume for the purpose of this invention that f(x) comprises 'n' input words u₀(x) , uι(x), ..., u_n._!(x). The length of u_;(x) is ^cp', the length of f(x) is 'pxn', the length of R(x) is M, and the degree of g(x) is M. Since in each cycle encoder 200 receives 'p⁹ bits in parallel, the present invention uses a different approach than the prior art approach. In the first step, an intermediate quotient (hereinafter "qi(x)") is estimated using the current input word (hereinafter "Uj(x)") and the 'p' most significant bits (MSBits) of the previously calculated R(x) (hereinafter "Rj-ι(x)"). Then, in the second step, the reminder R_.(x) is updated by multiplying between qi(x) and g(x), followed by adding the 'M-p' MSBits of the result to the M-p least significant bits (LSBits) of the previously calculated RM(X). This process is repeated 'n' times, i.e., for "i" starting at zero and ending at 'n-1'. Mathematically, this approach can be described by the following steps:

The estimation of q;(x) is calculated by using the equation:

_qi(x) = {ui(x) + r(x)}*g-¹(x)|_p-MSBits (2)

where the polynomial r(x) includes the p-MSBits of the previously calculated R(x) as its coefficients. The sign '*' denotes polynomial modulo-2 multiplication. The 'p-1' degree binary polynomial g^_1(x) is the reciprocal polynomial of the generator polynomial g(x). The coefficients of the polynomial g^_1(x) are derived from the polynomial g(x) and are constant. The g^_1(x) coefficients are predetermined using the equation:

g-¹(x)*g(x) |_p-MSBits = X^P_1 (3)

The reminder is calculated by using the equations: R-(x) = q-(x)*g(x) |M-LSBit- (4) and,

Rj(X) = [R(x)j |(M-p)MSBits © R i-l (X)| (M-p)LSBits] - ^P © R i(x)|p-LSBits (5) where Rj-_!(x) represents the previously calculated R(x). Encoder 200 includes: a first adder 230 for performing XOR logical operations involving MSBits of R(x) and 'p' bits of current input word u;(x); a quotient computation logic (QCL) 210 connected to first adder 230 for estimating intermediate quotient qs(x); a remainder computation logic (RCL) 220 connected to QCL 210 and used for calculating reminder Ri(x); a second adder 240 connected to RCL 220 and used for performing XOR logical operations involving (M-p) LSBits of a previous

and (M-p) MSBits of a new Ri(x); and a register 270 connected to RCL 220, second adder 240 and first adder 230 and used for saving the (M-p) MSBits resulting from second adder 240 along with the p LSBits resulting from RCL 220. QCL 210 and RCL 220 include combinational logic of XOR gates. First adder 230 includes an array of 'p' XOR gates, while second adder 240 includes an array of 'M-p' XOR gates. At startup,^' register 270 is set to zero value. First adder 230 receives the p-MSBits of the previously calculated Ri-ι(x) from register 270 together with 'p' input bits of u;(x), and performs a bit-by-bit XOR operation between these quantifies. QCL 210 estimates the quotient q;(x) by multiplying the output of adder 230 by g^'^x), namely, QCL 210 implements equation (2) above. The coefficients of the polynomial g^_1(x) are predetermined according to equation (3) and thus determine the combinational logic of XOR operations within QCL 210. The coefficients of g^_1(x) may be represented by a matrix as shown in Fig. 4A. RCL 220 calculates R(x) by modulo-2 multiplication between the output of QCL 210 (i.e., qi(x)) and the coefficients of g(x). Namely, RCL 220 implements equation (4). The coefficients of the g(x) are provided from the BCH code definition, and thus determine the combinational logic of XOR operations within RCL 220. The coefficients of g(x) may be represented as a 'G' matrix shown in Fig. 4B. As mentioned, the (M-p) MSBits of the newly calculated Rj(x) are XORed with the (M-p) LSBits of the previously calculated Ri-ι(x) by means of adder 240. The result is inserted into register 270 as its (M-p) MSBits. The p-LSBits resulting from the calculation performed by RCL 220 are inserted into register 270 as its p-LSBits. Now, register 270 includes the updated reminder as a result of the division of uι(x) by g(x). After 'n' cycles, register 270 holds the reminder of the division operation of the entire input polynomial f(x) by g(x), i.e., the redundancy bits. Reference is now made to Fig. 3, which shows an exemplary flowchart 300 describing the method for parallel encoding by encoder 200, in accordance with one embodiment of this invention. Each cycle encoder 200 receives 'p' bits of u;(x) and produces a temporary redundancy information. An index "i" and the content of register 270 are both set to zero in a step 305. In a step 310, encoder 200 receives the current Uj(x) to process. In a step 320, the 'p' MSBits of the previously calculated R(x) are XORed with the 'p' bits of Uj(x), using adder 230. In a step 330, encoder 200 calculates (x) by multiplying between the output of adder 230 and the polynomial g^"*(x). In the embodiment of Fig. 4A, the polynomial g^_1(x) may be represented as a matrix (G^"1) having 'p' rows and 'p' columns, where the matrix elements are composed from the coefficients of g^_1(x). The result is a p-bit vector of qi(x). In a step 340, q;(x) and g(x) are multiplied. The M-LSBits of the multiplication provide the M bits of the intermediate reminder R;(x). In the embodiment of Fig. 4B, g(x) may be represented as a matrix "G" having 'M' rows and 'p' columns, where the matrix's elements are composed from the g(x) polynomial coefficients. In a step 350, a XOR operation is performed between the 'M-p' LSBits of the previously calculated Rj-ι(x) and the 'M-p' MSBits results from the calculation performed in step 340. In a step 360, the outcome of adder 240 is saved into register 270 as its 'M-p' MSBits, and furthermore, the 'p' LSBits of the result received in step 340 are saved into register 270 as ^' its 'p' LSBits. In a step 365, the index "i" is increased by one. In a step 370, it is determined whether there are more input words u,(x) to process, i.e., if the index "i" equals n-1. If there are more input words, i.e. "i" is smaller than 'n', the method continues to step 310, otherwise the method continues to a step 380. In step 380, after receiving the entire input information word encoder 200 outputs the content of register 270 as redundancy bits, i.e. the resulting reminder.

Reference is now made to Fig. 5, which shows a step-by-step example of the encoding procedure. Here, M=10, p=4, n=3, and the length of the input information word 'K' equals 12. The input data includes three input blocks uo = 1101, uι = 1101, and u = 0011. Each 4-bit input block uses MSBit (left bit) first notation. The generator polynomial g(x) is x¹⁰+x⁸+x³+l, and the computed g^_1(x) polynomial is x³+x. Fig. 5 A shows the content of register 270 after each cycle. QCL 210 multiplies between its input and the G^"1 matrix shown in Fig. 5B. The multiplication is done according to

modulo-2, where φ and wj are column vectors holding the coefficients of qι(x) and w;(x) polynomials respectively. The vector Wj holds the result of the operation performed by adder 230. The coefficient representing the LSBit of the polynomial is the first (upper) element in the respective column vector, while the coefficient representing the MSBit of the polynomial is the last (bottom) element in the respective column vector. RCL 220 multiplies between its input and the G(x) matrix shown in Fig. 5C. The multiplication is done according to Rj = G-qi modulo-2. Here qi and R; are column vectors holding the coefficients of the q;(x) and R,(x) polynomials respectively. The coefficient representing the LSBit of the polynomial is the first (upper) element in the respective column vector, while the coefficient representing the MSBit of the polynomial is the last (bottom) element in the respective column vector. After three cycles, register 270 contains the transmitted redundancy information which is (MSBit 1^st): 1010 0010 10.

One of the problems faced in the implementation of systems having a high clock rate utilizing a generator polynomial with a high degree, is the propagation delay. The propagation delay is the time required for a signal to flow through a combinational logic. For example, if a combinational logic consists of "c" logic gates in series, then the propagation delay is "c" times the delay of a single logic gate, while for a tree structure connection the propagation delay is log2(c) times the delay of a single logic gate. Reducing the propagation delay can be achieved by using a pipeline implementation. Reference is now made to Fig. 6, which shows an exemplary block diagram of a BCH encoder 600, designed to reduce the propagation delay. Encoder 600 includes the elements of encoder 200, and further includes a buffer 680. Buffer 680 buffers between a QCL 610 and a RCL 620, allowing the operation of logical circuits QCL 610 and RCL 620 to act as a pipeline process. Firstly, encoder 600 estimates the quotient qι(x) and stores the result in a buffer 680. Secondly, encoder 600 calculates the reminder Ri(x) using the previously calculated quotient i.e., qi-ι(x). The value of q--_(x) is obtained from buffer 680. The calculation of q_ι(x) and Rj(x) are described in detail above. However, in this embodiment, QCL 610 multiplies between '2p' coefficients of

and thus qi(x) includes '2p' bits. Therefore, 'p' is replaced by '2p' in the calculation of g^_1(x). The coefficients of g (x) determine the logic of QCL 610 and are derived using the following equation:

g ¹(x)*g(x) |₂._P-MSBits = x^{2 p"1} (6)

Using this approach, the propagation delay is the time required to output reminder R(x), which is equal to max(t_l3t₂). The time t is the propagation delay of a first adder 630 and QCL 610. In some cases, the time ti includes the propagation delay results from the interfaces of encoder 200 components. The time t₂ is the sum of the propagation delays of RCL 620 and a second adder 640, as opposed to encoder 200, where the propagation delay equals to the sum of propagation delay time of encoder 200, adder 230, QCL 220, RCL 210 and adder 240. The inventors wish to point out that adding more pipeline stages, i.e. adding additional buffers, reduces the propagation delay at the expense of increased hardware size

This invention may have a particular use as a BCH encoder described in co-pending PCT patent application filed December 10, 2002, "An Apparatus for Processing OTN Frames Utilizing an Efficient Forward Error Correction" in the name of Optix Networks Ltd., which is hereby incorporated by reference.

Encoder 200 in used in the apparatus to produce the redundancy information residing in an optical transport network (OTN) frame. Encoder 200 receives two input information words "A" and "B" and produces the redundancy correlated with these information words. For processing the input word "A", each cycle encoder 200 receives 128 bits of word "A" and after 120 cycles outputs 1,015 bits of the redundancy information. For processing the input w^rord "B", each cycle encoder 200 receives 128 bits of word "B" and after 119 cycles outputs 1,015 bits of the redundancy information. The lengths of input information words "A" and "B" are 128*120 (i.e., 15,360) bits and 128*119 (i.e., 15,232) bits respectively.

Encoder 200 described herein is designed to encode input information when the length of the generator polynomial (i.e., M) is greater than the length of the current input word (i.e., p). However, a person skilled in the art could easily adapt encoder 200 to operate when the M is smaller than, or equal to, p. The invention has now been described with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art. For example, the invention has been described with respect to a BCH code. The invention can be modified to apply to special cases of error correcting codes having similar characteristics, such as Reed-Solomon codes, which are non-binary subsets of BCH codes. In addition, the invention applies to a wide variety of linear cyclic invariant codes whose generator polynomials can be factored.

All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention.

Claims

WHAT IS CLAIMED IS

1. A high rate parallel encoder for encoding an input information word and for producing redundancy information, comprising: a) a first adder operative to perform a first logical operation; b) a quotient computation logic (QCL) connected to said first adder and operative to estimate an intermediate quotient value; c) a remainder computation logic (RCL) coupled to said QCL and operative to calculate an intermediate reminder; d) a second adder coupled to said RCL and operative to perform a second logical operation and to output second adder bit values; and, e) a register coupled to said second adder and said RCL and operative to store said calculated intermediate reminder, whereby the encoder is operative to encode an information word into a Bose-Chaudhuri-Hocquenghem error correcting code and to produce redundancy information

2. The parallel encoder of claim 1, wherein said first adder includes an array of 'p' exclusive OR (XOR) gates used to perform said first logical operation.

3. The parallel encoder of claim 1, wherein said QCL includes a combinational logic of XOR gates used to estimate said intermediate quotient.

4. The parallel encoder of claim 1, wherein said RCL includes a combinational logic of XOR gates used to calculate said intermediate reminder.

5. The parallel encoder of claim 1, wherein said second adder includes an array of ^cM-p' XOR gates used to perform said second logical operation.

6. The parallel encoder of claim 1, wherein said encoder operability to produce redundancy information includes: i. receiving an input information word comprising a plurality of data blocks in said first adder; for each said data block: ii. iteratively computing current data block temporary redundancy information in said RCL; and, iii. producing the redundancy information after receiving the entire said plurality of said data blocks of said input information word.

7. The parallel encoder of claim 6, wherein said iterative computation of said temporary redundancy information values further mcludes calculating an intermediate reminder by the division of said current data block by a generator polynomial.

8. The parallel encoder of claim 7, wherein said intermediate reminder calculation further includes i. estimating said intermediate quotient using said current data block and

'p' MSBits of a previously calculated reminder ; and ii. updating said intermediate reminder by using said intermediate quotient and said previously calculated intermediate reminder.

9. The parallel encoder of claim 8, wherein said operability to estimate an intermediate quotient value further includes:

i. performing said first logical operation in said first adder, said first logical operation including a XOR operation between said current input data block and said 'p' MSBs of said previously calculated temporary reminder; and

ii. multiplying the result of said first logical operation with coefficients of a reciprocal generator polynomial according to equation 2.

10. The parallel encoder of claim 9, wherein the step of multiplying comprises performing a polynomial multiplication.

11. The parallel encoder of claim 9, wherein said 'p' is equal to the length of said current data block.

12. The parallel encoder of claim 9, wherein said previously calculated reminder is obtained from said register.

13. The parallel encoder of claim 8, wherein said updating of said intermediate reminder further includes: a. multiplying between said intermediate quotient and coefficients of a generator polynomial according to equation 4; b. performing said second logical operation in said second adder, said second logical operation including a XOR operation between 'L' MSBs of the result of equation 4 and 'L' least significant bits (LSBs) of said previously calculated intermediate reminder to provide said second adder bits; and c. saving said second adder bit values along with the 'p' least significant bit values of said multiplication results in said register.

14. The parallel encoder of claim 13, wherein said 'L' is equal to the degree of said generator polynomial minus the length of said current data block.

15. The parallel encoder of claim 13, wherein the length of said generator polynomial is at least 1,000 bits.

16. The parallel encoder of claim 13, wherein said previously calculated reminder is obtained from said register.

17. The parallel encoder of claim 1, wherein said encoder is designed to operate at rates in excess of 10 Gigabits per second.

18. The parallel encoder of claim 1, wherein said encoder operability to produce redundancy information further includes operability to produce redundancy information of at least 1,000 bits.

19. The parallel encoder of claim 1 , implemented in an integrated circuit.

20 A parallel encoder for encoding an input information word using a pipeline implementation, the encoder capable of producing redundancy information, the encoder comprising: a) a first adder operative to perform a first logical operation; b) a quotient computation logic (QCL) connected to said first adder and operative to estimate an intermediate quotient value; c) a buffer connected to said QCL and a remainder computation logic; d) a remainder computation logic (RCL) coupled to said buffer and operative to calculate an intermediate reminder; e) a second adder coupled to said RCL and operative to perform a second logical operation and to output second adder bits ; and, f) a register coupled to said second adder and said RCL and operative to store said calculated reminder, whereby the encoder is operative to reduce the propagation delay when encoding information word into a Bose-Chaudhuri-Hocquenghem error correcting code, and to produce redundancy information.

21. The parallel encoder of claim 20, wherein the encoder is a feedback system.

22. The parallel encoder of claim 20, wherein said first adder includes an array of ^cp' exclusive OR (XOR) gates used to perform said first logical operation.

23. The parallel encoder of claim 20, wherein said QCL includes a combinational logic of XOR gates used to estimate said intermediate quotient.

24. The parallel encoder of claim 20, wherein said RCL includes a combinational logic of XOR gates used to calculate said reminder.

25. The parallel encoder of claim 20, wherein said second adder includes an array of 'M-p' XOR gates used to perform said second logical operation.

26. The parallel encoder of claim 20, wherein said encoder operability to produce redundancy information includes: i. receiving an input information word comprising a plurality of data blocks in said first adder; for each said data block: ii. iteratively computing temporary redundancy information in said RCL; and, iii. producing the redundancy information after receiving the entire said plurality of said data blocks of said input information word.

27. The parallel encoder of claim 26, wherein said iterative computation of said temporary redundancy information values further includes calculating an intermediate reminder of the division of said current data block by a generator polynomial.

28. The parallel encoder of claim 27, wherein said reminder calculation further includes: i. estimating said intermediate quotient using said current data using said current data block and 'p' MSBits of a previously calculated reminder; ii. saving said intermediate quotient in said buffer; and iii. updating said intermediate reminder using said intermediate calculated quotient and said previously calculated intermediate reminder.

29. The parallel encoder of claim 28, wherein said estimating and said updating are performed concurrently.

30. The parallel encoder of claim 29, wherein said operability to estimate an intermediate quotient value further includes: i. performing said first logical operation in said first adder, said first logical operation including a XOR operation between said current input data block and said 'p' MSBs of said previously calculated temporary reminder; and

31. The parallel encoder of claim 29, wherein said step of multiplying comprises performing a polynomial multiplication.

32. The parallel encoder of claim 30, wherein said 'p' is equal to the length of said current data block.

33. The parallel encoder of claim 30, wherein said previously calculated reminder is obtained from said register.

34. The parallel encoder of claim 28, wherein said updating of said reminder further includes: a. multiplying between said intermediate quotient and coefficients of a generator polynomial according to equation 4; b. performing said second logical operation in said second adder, said second logical operation including a XOR operation between 'L' MSBs of the result of equation 4 and 'L' least significant bits (LSBs) of said previously calculated intermediate reminder to provide said second adder bits; and c. saving said second adder bit values along with the 'p' least significant bit values of said multiplication results in said register.

35. The parallel encoder of claim 34, wherein said 'L' is equal to the degree of said generator polynomial minus the length of said current data block.

36. The parallel encoder of claim 34, wherein the length of said generator polynomial is at least 1,000 bits.

37. The parallel encoder of claim 34, wherein said previous calculated reminder is obtained from said register.

38. ' The parallel encoder of claim 34, wherein said previously calculated quotient is obtained from said buffer.

39. The parallel encoder of claim 20, wherein said encoder is designed to operate at rates in excess of 10 Gigabits per second.

40. The parallel encoder of claim 20, wherein said encoder operability to produce redundancy information further includes operability to produce redundancy information of at least 1,000 bits.

41. The parallel encoder of claim 20, implemented in an integrated circuit.

42. An optical network device for high-rate parallel encoding, comprising: a) a first adder coupled to an input channel and configured to receive at least one input information word through said input channel; b) a quotient computation logic (QCL) connected to said first adder and capable of computing an intermediate quotient; c) a remainder computation logic (RCL) coupled to said QCL and capable of computing a current reminder; d) a second adder coupled to said RCL and capable of performing logical exclusive OR (XOR) operations; and e) a register coupled to both said RCL said second adder and configured to output an encoded output information word to an output channel, whereby the optical network device is capable of producing redundancy information correlated with said at least one input information word.

43. The optical network device of claim 42, wherein said input channel is coupled to a source optical network.

44. The optical network device of claim 42, wherein said output channel is coupled to a destination optical network.

45. The optical network device of claim 43, wherein said source destination network is selected from the group consisting of a SONET/SDH network and an optical transport network (OTN).

46. The optical network device of claim 44, wherein said destination network is selected from the group consisting of a SONET/SDH network and an optical transport network (OTN).

47. The optical network device of claim 42, wherein said redundancy information is at least 1,000 bits long.

48. The optical network device of claim 42, wherein said redundancy information is transmitted at a rate of at least 10 Gigabits per second

49. The optical network device of claim 42, wherein said at least one input information word is encoded in accordance with a BCH code.

50. The optical network device parallel encoder of claim 42, implemented in an integrated circuit.

51. A method for high rate parallel encoding comprising the steps of : a) receiving an input information word that includes a plurality of data blocks in a first adder; for each said data block: b) performing a first logical operation in said first adder; c) estimating an intermediate quotient value in a quotient computation logic (QCL) connected to said first adder; d) calculating a intermediate reminder in a remainder computation logic (RCL) coupled to said QCL; e) performing a second logical operation in a second adder coupled to said RCL, said second logical operation resulting in output second adder bits; and, f) storing said intermediate calculated reminder in a register coupled to said second adder and said RCL, whereby the method can be used to encode an input information word into a Bose-Chaudhuri-Hocquenghem error correcting code and to produce redundancy information.

52. The method of claim 51, wherein said producing of said redundancy information values further includes calculating a reminder through the division of said information word by a generator polynomial.

53. The method of claim 51, wherein said step of performing a first logical operation further includes performing a XOR operation between said data block and said 'p' MSBs of a previously calculated temporary reminder.

54. The method of claim 53, wherein said 'p' is equal to the length of said current data block.

55. The method of claim 51, wherein said step of estimating an intermediate quotient value further includes multiplying the result of said first logical operation with coefficients of a reciprocal generator polynomial according to equation 2.

56. The method of claim 51, wherein said step of calculating said temporary reminder further includes multiplying between said intermediate quotient and coefficients of a generator polynomial according to equation 4.

57. The method of claim 56, wherein the step of multiplying comprises a performing polynomial multiplication.

58. The method of claim 51, wherein said step of performing said second logical operation further includes performing a XOR operation between 'L' MSBits of the result of equation 4 and 'L' least significant bits of said previously calculated reminder to provide said second adder bit values.

59. The method of claim 58, wherein said 'L' is equal to the degree of said generator polynomial minus the length of said current data block.

60. The method of claim 59, wherein the length of said generator polynomial is at least 1,000 bits.