WO2004105113A1 - Corps de polissage pour le polissage cmp, appareil de polissage cmp, procede de polissage cmp et procede de production d'un dispositif a semi-conducteur - Google Patents

Corps de polissage pour le polissage cmp, appareil de polissage cmp, procede de polissage cmp et procede de production d'un dispositif a semi-conducteur Download PDF

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Publication number
WO2004105113A1
WO2004105113A1 PCT/JP2004/006859 JP2004006859W WO2004105113A1 WO 2004105113 A1 WO2004105113 A1 WO 2004105113A1 JP 2004006859 W JP2004006859 W JP 2004006859W WO 2004105113 A1 WO2004105113 A1 WO 2004105113A1
Authority
WO
WIPO (PCT)
Prior art keywords
polishing
cmp
wafer
elastic member
cmp polishing
Prior art date
Application number
PCT/JP2004/006859
Other languages
English (en)
Japanese (ja)
Inventor
Susumu Hoshino
Norio Yoshida
Yuko Kitade
Osamu Shimoda
Takeya Yabuki
Original Assignee
Nikon Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corporation filed Critical Nikon Corporation
Priority to JP2005506353A priority Critical patent/JPWO2004105113A1/ja
Publication of WO2004105113A1 publication Critical patent/WO2004105113A1/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/24—Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials

Definitions

  • Polishing body for CMP polishing for CMP polishing, CMP polishing apparatus, CMP polishing method, and semiconductor device manufacturing method.
  • the present invention relates to a polishing body for CMP polishing, a CMP polishing apparatus, a method of flattening a surface of Si 2 formed on a surface of a Si substrate by polishing by CMP polishing, and a semiconductor device using the method. It relates to a manufacturing method of the. Background art
  • the surface state of semiconductor devices is not necessarily flat.
  • the presence of a step on the surface causes disconnection of the wiring, a local increase in the resistance value, etc., which leads to disconnection and a reduction in current capacity.
  • the insulation film may lead to deterioration of withstand voltage and generation of leak.
  • the light source wavelength of optical lithography has become shorter with the increase in integration and miniaturization of semiconductor integrated circuits, and the numerical aperture, or NA, has become larger. I'm getting better. In order to cope with the shallow focal depth, flattening of the device surface is required more than ever.
  • FIG. 6 is a conceptual diagram of a planarization technique in a semiconductor manufacturing process, and is a cross-sectional view of a semiconductor device.
  • Fig 6 11 is a silicon wafer
  • 12 is an interlayer insulating film made of SiO 2
  • 13 is a metal film made of A1
  • 14 is a semiconductor device.
  • FIG. 6 (a) shows an example of flattening the interlayer insulating film 12 on the surface of the semiconductor device.
  • FIG. 6B shows an example in which a metal film 13 on the surface of a semiconductor device is polished to form a so-called damascene.
  • CMP chemical mechanical polishing
  • CMP has been developed based on a mirror polishing method for silicon wafers, and is performed using a CMP apparatus as shown in FIG.
  • Reference numeral 15 denotes a head for rotating the wafer 16 while holding the wafer 16 to be polished, and has a rotation drive mechanism 17.
  • These polishing pad 18, rotary platen 19, and rotary drive mechanism are provided.
  • 20 is given swinging by the rotary actuator 21 and is driven up and down.
  • the polishing pad 18 and other members may be combined and used in place of the polishing pad 18 shown in FIG. 7. Are referred to as "polishing bodies".
  • the wafer 16 and the polishing pad 18 are rotated at a high speed, and the rotary swing arm 21 is lowered by a vertical drive mechanism (not shown). Then, the wafer 16 is pressurized by the polishing pad 18. Then, a slurry as an abrasive is supplied between the polishing pad 18 and the wafer 16. Further, the rotary swing arm 21 is swung by a swing drive mechanism (not shown) as shown by a broken arrow. Then, the wafer 16 is polished by the relative rotation and swing of the polishing node 18 and the wafer 16. Is performed, and the surface is flattened. That is, good polishing is performed by the synergistic action of mechanical polishing by relative movement between the polishing pad 18 and the wafer 16 and chemical polishing by slurry.
  • the surface of a wafer in which semiconductor integrated circuits are formed is not flat, and there is usually a step between the part where chips are formed and the part where chips are not formed. . Therefore, when such a wafer is polished, the wafer is polished uniformly along the irregularities (undulations), that is, along the irregularities (undulations) of a large cycle inevitably generated with the circuit formation. It is required to eliminate local irregularities (this is called “local pattern flatness”) while performing “wafer 'global' removal uniformity”.
  • a polishing pad that satisfies both “Ueno, 'global-removal uniformity” and “local' pattern flatness” is composed of a polishing pad, a hard elastic member, and a soft member stacked in this order.
  • a hard elastic member is sandwiched between the polishing pad and the soft member. Pattern flatness "can be satisfied.
  • an effective area of a wafer on which a circuit pattern is formed can be obtained. It can be polished flat. This effective area is defined as a part inside 3 mm from the outer periphery of the wafer. That is, no circuit pattern is formed in a portion within 3 mm from the outer periphery, and it is not necessary to polish this portion flat.
  • the polishing rate at the outer peripheral portion is higher than that at the inner portion, so that SiO 2
  • SiO 2 There is a problem that the two parts are completely polished and lost, and the underlying Si is exposed. If the Si is exposed, dust and the like tend to adhere, and the attached dust and the like enter the polished surface and cause problems such as contaminating and damaging the polished surface.
  • the retainer ring is arranged so as to surround the outer periphery of the wafer, and the outer peripheral surface of the wafer is protected by the retainer ring, thereby preventing the outer peripheral surface of the wafer from being excessively polished.
  • a retainer ring is a consumable item, so that not only does it cost much, but also it is difficult to adjust the height of the retainer ring. Disclosure of the invention
  • a first invention for achieving the above object is to provide a polishing body for CMP polishing suitable for use in a polishing method, a CMP polishing apparatus, and a method for manufacturing a semiconductor device using the CMP polishing method.
  • the polishing pad is formed by laminating a polishing pad, a hard elastic member, and a soft elastic member in this order, and a thickness of the soft elastic member is 1 to 2 or less of a thickness of the polishing pad. This is a polishing body for CMP polishing.
  • a second invention for achieving the above object is the first invention, wherein the thickness of the soft elastic member is 0.2mni ⁇ T ⁇ 0.5mm.
  • a polishing pad, a hard elastic member, and a soft elastic member are laminated in this order, and the soft elastic member has a thickness of 0.2111111 ⁇ 0.1 ⁇ 0.5111111.
  • Characteristic polishing body for CMP polishing It is.
  • a fourth invention for achieving the above object is a CMP polishing apparatus for performing polishing by moving a substrate relative to a polishing body while making contact with the polishing body.
  • a CMP polishing apparatus characterized by using any one of the polishing bodies for CMP polishing according to the third invention.
  • Fifth invention for achieving the above object, the Si_ ⁇ second surface formed on the Si substrate surface, a method of planarizing by polishing by CMP polishing, third from the first aspect of the present invention T is a CMP polishing method, characterized in that polishing is performed using the polishing body for CMP polishing according to any one of the inventions.
  • the sixth invention for achieving the above object is the fifth invention.
  • a method for manufacturing a semiconductor device comprising a step of polishing a wafer by a CMP polishing method.
  • a seventh invention for achieving the above object the surface of the Si O 2 formed on the Si substrate surface, a method of planarizing by polishing by CMP polishing, polishing the polishing pressure as follows 1 psi And a CMP polishing method.
  • An eighth invention for achieving the above object is the seventh invention, wherein the polishing body used for the CMP polishing is formed by laminating a polishing pad, a hard elastic member, and a soft elastic member in this order. It has a three-layer structure.
  • a ninth invention for achieving the above object is a method of manufacturing a semiconductor device, comprising a step of polishing a wafer by the CMP polishing method of the seventh invention or the eighth invention.
  • FIG. 1 is a diagram showing an outline of a polishing body having a three-layer structure.
  • FIG. 2 is a diagram showing the polishing rate at each position on the wafer using the thickness (mm) of the foamed polyurethane as a parameter.
  • FIG. 3 is a diagram showing the polishing rate at each position on the wafer, based on the polishing pressure (pressure for pressing the polishing body against the wafer) as a parameter.
  • FIG. 4 is a diagram showing a relationship between a polishing pressure and a polishing rate in a steady portion.
  • FIG. 5 is a flowchart showing a semiconductor device manufacturing process as an example of the embodiment of the present invention.
  • FIG. 6 is a conceptual diagram of a planarization technique in a semiconductor manufacturing process.
  • FIG. 7 is a diagram showing an outline of a CMP apparatus used for CMP polishing. BEST MODE FOR CARRYING OUT THE INVENTION
  • the number of revolutions of the polishing body was set at 301 rpm, and the number of revolutions of the wafer was set at ⁇ 10 rpm (reverse rotation with respect to the polishing body).
  • the starting position of the polishing body is 22 mm from the center of rotation of the wafer, the moving stroke is 45 mm, and the swing speed is 40 min / sec.
  • the slurry was supplied at a ratio of 100 ml / rniri using SS25 (trade name) manufactured by Cabot Corporation.
  • the polishing pressure (the pressure for pressing the polishing body against the wafer) was 2.0 psi.
  • Figure 2 shows the polishing rate at each position on the wafer, using the thickness of the foamed polyurethane as a parameter.
  • the horizontal axis represents a position on the wafer (the distance from the wafer center [mm])
  • the vertical axis represents the Si_ ⁇ 2 in the polishing rate (A (Ogusu Toromu) / niin).
  • the polishing rate at a position from the outer periphery of the wafer to 3 mm begins to decrease, and when the thickness of the polyurethane foam becomes thinner than 0.2 mm, on the contrary, the wafer edge portion The polishing rate tends to be lower than that inside. Even if the polishing rate is lowered at the wafer edge, there is no problem because no pattern is formed at that portion.
  • the thickness of the foamed polyurethane which is a soft elastic member, becomes 1 Z2 or less of the thickness of the polishing pad, the sharp polishing rate at a position up to 3 mm from the outer periphery of the wafer will increase. It can be estimated that the increase will no longer be seen.
  • the thickness of the foamed polyurethane which is a soft elastic member, is 0.5 mm or less, it can be estimated that a sharp increase in the polishing rate at a position up to 3 mm from the outer periphery of the wafer will not be observed.
  • the surface of SiO 2 formed on the surface of the Si substrate was A polishing body formed by laminating a polishing pad, a hard elastic member, and a soft elastic member in this order when flattening by polishing, wherein the thickness of the soft elastic member is If polishing is performed using a polished body with a thickness of 1/2 or less or a foamed polyurethane that is a soft elastic member with a thickness of 0.5 mm or less, polishing at the wafer edge will occur. It was found that the problem that Si was exposed due to the increase in the rate could be solved, and that the polishing rate in the wafer surface was not affected.
  • NPS 3301 NPS 3301 (NPS is a registered trademark)
  • the edge of the wafer is polished.
  • a 1.25 mm thick polishing pad IC1000 (trade name) manufactured by Rodel Co., Ltd. is bonded to a 0.2 mm thick SUS plate, and a 1.25 mm thick foamed polyurethane is further bonded onto the SUS plate.
  • the SUS plate was used in a sandwich shape.
  • This abrasive body has an outer diameter of 266 mm, and is a donut-shaped abrasive body having a hole with a diameter of 84 mm formed in the center. Retainer rings were not used during polishing.
  • the rotation speed of the polishing body was set at 181 rpm, and the rotation speed of the wafer was set at 201 rpm (reverse rotation from the polishing body).
  • the swinging start position of the polishing body was 27.5 mni from the center of rotation of the wafer, the rotating stroke was 85 mm, and the rotating speed was 40 mmZsec.
  • the slurry was supplied at a flow rate of 150 ml / min using SS25 (trade name) manufactured by Cabot Corporation.
  • Figure 3 shows the polishing rate at each position on the wafer, using the polishing pressure (the pressure at which the polishing body is pressed against the wafer) as a parameter.
  • the horizontal axis is a position on a wafer (the distance from the wafer center [mm]), the vertical axis represents the Si_ ⁇ second polishing rate (A (Ogusu Toromu) / min).
  • FIG. 4 shows the results.
  • the horizontal axis is the polishing pressure (psi)
  • the vertical axis is the average polishing rate of SiO 2 (A (ogstroms) / min).
  • the polishing rate decreases almost linearly, but the relationship between polishing rate and polishing pressure is proportional to what is generally known as Preston's equation.
  • FIG. 5 is a flowchart illustrating a semiconductor device manufacturing process according to an embodiment of the present invention.
  • an appropriate processing step is selected from the following steps S101 to S104. According to the selection, the process proceeds to any of steps S101 to S104.
  • Step S101 is an oxidation step for oxidizing the surface of the silicon wafer.
  • Step S102 is a CVD step of forming an insulating film on the surface of the silicon wafer by CVD or the like.
  • Step S103 is an electrode forming step of forming electrodes on the silicon wafer by steps such as vapor deposition.
  • Step 104 is an ion implantation step of implanting ions into the silicon wafer. 'After the CVD step or the electrode forming step, go to step S105.
  • step S105 it is determined whether or not to perform the CMP step, and if so, the process proceeds to step S106. If the CMP step is not performed, bypass S106.
  • the polishing apparatus performs planarization of the interlayer insulating film and formation of damascene S by polishing the metal film on the surface of the semiconductor device.
  • Step S107 is a photolithography process.
  • a resist is applied to a silicon wafer, a circuit pattern is printed on the silicon wafer by exposure using an exposure apparatus, and the exposed silicon wafer is developed.
  • the next step S108 is an etching step in which portions other than the developed resist image are removed by etching, and thereafter, the resist is peeled off, and the unnecessary resist after etching is removed.
  • step S109 it is determined whether or not all necessary processes have been completed. If not, the process returns to step S100, and the previous steps are repeated to form a circuit pattern on the silicon wafer. If it is determined in step S109 that all steps have been completed, the steps are terminated.
  • the CMP polisher according to the embodiment of the present invention is the same as the conventional CMP polisher shown in FIG. 7 except that the polishing body of the present invention is used, and therefore the description thereof is omitted.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

L'invention concerne un corps de polissage permettant un polissage chimique et mécanique CMP lequel est utilisé de préférence dans un procédé de polissage CMP permettant de prévenir un polissage excessif de la surface périphérique d'une plaquette. Ce corps de polissage CMP est constitué d'un tampon de polissage, d'un élément élastique dur et d'un élément élastique mou liés ensemble dans cet ordre, et l'épaisseur de l'élément élastique mou ne dépasse pas la moitié de l'épaisseur du tampon de polissage.
PCT/JP2004/006859 2003-05-26 2004-05-14 Corps de polissage pour le polissage cmp, appareil de polissage cmp, procede de polissage cmp et procede de production d'un dispositif a semi-conducteur WO2004105113A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005506353A JPWO2004105113A1 (ja) 2003-05-26 2004-05-14 Ｃｍｐ研磨用研磨体、ｃｍｐ研磨装置、ｃｍｐ研磨方法、及び半導体デバイスの製造方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2003-147834 2003-05-26
JP2003147834 2003-05-26
JP2003150285 2003-05-28
JP2003-150285 2003-05-28

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WO2004105113A1 true WO2004105113A1 (fr) 2004-12-02

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JP (1) JPWO2004105113A1 (fr)
TW (1) TW200513347A (fr)
WO (1) WO2004105113A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160145810A (ko) * 2014-04-23 2016-12-20 어플라이드 머티어리얼스, 인코포레이티드 화학 기계적 평탄화 후의 기판 세정을 위한 시스템, 방법 및 장치
CN108562470A (zh) * 2018-04-09 2018-09-21 大连理工大学 一种钨镍铁合金金相制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677185A (ja) * 1990-06-29 1994-03-18 Natl Semiconductor Corp <Ns> 半導体ウエハの研磨用パッド及び研磨方法
JPH07164308A (ja) * 1993-12-14 1995-06-27 Shin Etsu Handotai Co Ltd シート状研磨部材およびウエーハ研磨装置
JPH083540A (ja) * 1994-06-22 1996-01-09 Sony Corp 化学機械研磨用微粒子およびその製造方法ならびにこれを用いた研磨方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677185A (ja) * 1990-06-29 1994-03-18 Natl Semiconductor Corp <Ns> 半導体ウエハの研磨用パッド及び研磨方法
JPH07164308A (ja) * 1993-12-14 1995-06-27 Shin Etsu Handotai Co Ltd シート状研磨部材およびウエーハ研磨装置
JPH083540A (ja) * 1994-06-22 1996-01-09 Sony Corp 化学機械研磨用微粒子およびその製造方法ならびにこれを用いた研磨方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160145810A (ko) * 2014-04-23 2016-12-20 어플라이드 머티어리얼스, 인코포레이티드 화학 기계적 평탄화 후의 기판 세정을 위한 시스템, 방법 및 장치
KR102396676B1 (ko) * 2014-04-23 2022-05-12 어플라이드 머티어리얼스, 인코포레이티드 화학 기계적 평탄화 후의 기판 세정을 위한 시스템, 방법 및 장치
CN108562470A (zh) * 2018-04-09 2018-09-21 大连理工大学 一种钨镍铁合金金相制备方法

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JPWO2004105113A1 (ja) 2006-07-20
TW200513347A (en) 2005-04-16

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