WO2004091036A1 - 受動部品 - Google Patents
受動部品 Download PDFInfo
- Publication number
- WO2004091036A1 WO2004091036A1 PCT/JP2004/004765 JP2004004765W WO2004091036A1 WO 2004091036 A1 WO2004091036 A1 WO 2004091036A1 JP 2004004765 W JP2004004765 W JP 2004004765W WO 2004091036 A1 WO2004091036 A1 WO 2004091036A1
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- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- dielectric substrate
- dielectric
- passive component
- shield
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/20—Frequency-selective devices, e.g. filters
- H01P1/201—Filters for transverse electromagnetic waves
- H01P1/203—Strip line filters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/20—Frequency-selective devices, e.g. filters
- H01P1/201—Filters for transverse electromagnetic waves
- H01P1/203—Strip line filters
- H01P1/20327—Electromagnetic interstage coupling
- H01P1/20336—Comb or interdigital filters
- H01P1/20345—Multilayer filters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/20—Frequency-selective devices, e.g. filters
- H01P1/201—Filters for transverse electromagnetic waves
- H01P1/205—Comb or interdigital filters; Cascaded coaxial cavities
Definitions
- the present invention relates to passive components including a laminated dielectric filter and the like constituting a resonance circuit in a microphone mouthband of several hundred MHz to several GHz, and can effectively reduce the size of communication devices and electronic devices.
- passive components including a laminated dielectric filter and the like constituting a resonance circuit in a microphone mouthband of several hundred MHz to several GHz, and can effectively reduce the size of communication devices and electronic devices.
- Background art
- the wiring pattern formed on the wiring substrate and the input / output terminals formed on the side surfaces of the laminated dielectric passive component are soldered or the like. Electrical connection (side mounting).
- the present invention has been made in view of such a problem, and can solve various problems due to side mounting, and can effectively suppress characteristic fluctuations and effectively simplify a manufacturing process.
- the purpose is to provide parts. Disclosure of the invention
- the passive component according to the present invention is a passive component having a plurality of electrodes constituting a passive circuit and at least one terminal led out to the outside in a dielectric substrate formed by laminating a plurality of dielectric layers. In the component, the terminal is led out only to the lower surface of the dielectric substrate.
- the terminals formed only on the lower surface of the dielectric substrate may be mounted on the wiring board by a surface mounting method. Area can be made smaller than in the case of.
- the terminals are present only on the lower surface of the dielectric substrate, the area of the plurality of electrodes can be reduced, and it is difficult for stray capacitance to be formed between these terminals and the electrodes. Therefore, the isolation characteristics of passive components are improved.
- the one or more terminals include a plurality of terminals through which signals are input / output and one or more shield terminals, and a plurality of terminals through which the signals are input / output are provided on a lower surface of the dielectric substrate.
- the shield terminals are arranged between the terminals. This ensures isolation between a plurality of terminals through which the signal is input and output can do.
- the terminal may be an electrode formed by a via hole in the dielectric substrate. This can prevent the terminals from peeling off from the dielectric substrate, and can also suppress the occurrence of cracks in the electrodes. Further, since the electrodes can be formed simultaneously with the formation of the via holes in the dielectric substrate, the step of forming the electrodes on the lower surface of the dielectric substrate can be omitted, and the steps can be simplified. Further, since the thickness of the electrode can be increased, the same mechanical strength as that of the conventional side terminal can be obtained.
- the diameter of the electrode forming the terminal is set to be larger than the diameter of the via hole. It is preferable to set a large value. As a result, the facing area between the wiring pattern of the wiring board and the terminal can be increased, and generation of an unnecessary inductance component can be suppressed.
- the terminal may be formed by an electrode formed on a lower surface of the dielectric substrate, or a shield electrode may be formed in the dielectric substrate.
- the dielectric constant ⁇ r of the dielectric layer between the shield electrode and the lower surface of the dielectric substrate is set to ⁇ r ⁇ 20. May be. In this case, the occurrence of stray capacitance between the shield electrode and the terminal can be suppressed, and the isolation characteristics can be improved.
- the dielectric constant ⁇ r of the dielectric layer between the shield electrode and the lower surface of the dielectric substrate is set to ⁇ r> 20. Is also good.
- the shield electrode in the dielectric substrate and the wiring pattern of the wiring substrate can be electrically connected via a capacitor, it is necessary to form an external terminal corresponding to the shield electrode on the lower surface of the dielectric substrate. Disappears.
- the terminal dimensions must be reduced.However, since it is not necessary to form external terminals corresponding to the shield electrodes, the area of the terminals can be increased. As a result, the mechanical strength of the terminal can be improved.
- the passive circuit formed in the dielectric substrate is a filter having one or more resonators
- the resonator is formed by a peer hole, and one of the two end faces of the via hole is used. It may have a short-circuit end and an open end.
- FIG. 1 is an exploded perspective view showing the passive component according to the first embodiment.
- FIG. 2 is a longitudinal sectional view showing the passive component according to the first embodiment.
- FIG. 3 is an exploded perspective view showing a passive component according to the second embodiment.
- FIG. 4 is a longitudinal sectional view showing a passive component according to the second embodiment.
- FIG. 5 is an exploded perspective view showing a passive component according to the third embodiment.
- FIG. 6 is an exploded perspective view showing a passive component according to the fourth embodiment.
- FIG. 7 is an exploded perspective view showing a passive component according to the fifth embodiment.
- FIG. 8 is an explanatory diagram showing a pattern example of a terminal formed on the lower surface of the dielectric substrate.
- the passive component 1 OA has a structure in which a plurality of dielectric layers (S 1 to S 7) are laminated, fired and integrated, and Dielectric substrate 14 having inner shield electrodes 12a and 12b formed on the surfaces (one main surface of second dielectric layer S2 and one main surface of sixth dielectric layer S6), respectively. Having.
- the dielectric substrate 14 is configured by stacking a first dielectric layer S1 to a seventh dielectric layer S7 in order from the top. These first to seventh dielectric layers S1 to S7 are composed of one or a plurality of layers.
- the dielectric substrate 14 has a filter portion 16 that forms two quarter-wavelength resonators (an input side resonator 18 and an output side resonator 20).
- the filter portion 16 has an input-side resonance electrode 26 and an output-side resonance electrode 28 formed on one main surface of the fourth dielectric layer S4.
- One end of the input-side resonance electrode 26 (the end formed near the first side surface 14a of the dielectric substrate 14) and one end of the output-side resonance electrode 28 ( The end formed near the first side surface 14a) is electrically connected to the inner-layer shield electrodes 12a and 12b through via holes 22 and 24, respectively. That is, one end of the input-side resonance electrode 26 and the other end of the output-side resonance electrode 28 each constitute a short-circuit end.
- the input resonance electrode 26 has an input tap electrode 30 formed from a central portion thereof toward the second side surface 14 b (the side surface opposite to the output resonance electrode 28) of the dielectric substrate 14. Have been.
- the output-side resonance electrode 28 has an output tap electrode 32 formed from the central portion thereof toward the third side surface 14 c (the side opposite to the second side surface 14 b) of the dielectric substrate 14. Has been established.
- one main surface of the third dielectric layer S3 faces the open ends of the input-side resonance electrode 26 and the output-side resonance electrode 28, and the fourth side surface 14 of the dielectric substrate 14 d (the side opposite to the first side 14 a) and the degree of coupling between the inner-layer shield electrodes 34 and 36 formed near the input-side resonator 18 and the output-side resonator 20.
- a coupling adjustment electrode 38 for adjusting the coupling.
- One main surface of the fifth dielectric layer S5 is opposed to the open ends of the input-side resonance electrode 26 and the output-side resonance electrode 28, and the fourth side surface 14d of the dielectric substrate 14 is formed.
- the inner layer shield electrode 12 a is connected to the inner layer shield electrode via via holes 44 and 46 penetrating the second dielectric layer S 2 near the fourth side surface 14 d of the dielectric substrate 14.
- the inner shield electrode 12 b is electrically connected to 34 and 36, and the inner shield electrode 12 b is connected to a peer penetrating the fifth dielectric layer S 5 near the fourth side surface 14 d of the dielectric substrate 14. It is electrically connected to the inner layer shield electrodes 39 and 40 via the holes 45 and 47.
- the passive component 1 OA has one of the dielectric layers constituting the dielectric substrate 14, one of which constitutes an input terminal in the lowermost dielectric layer S 7.
- the input electrode layer 48, one output electrode layer 50 constituting the output terminal, and four shield electrode layers 52a to 52d constituting the shield terminal are formed by via holes.
- the input electrode layer 48 is formed near the second side surface 14 b of the dielectric substrate 14, the output electrode layer 50 is formed near the third side surface 14 c of the dielectric substrate 14, Of the four shield electrode layers 52a to 52d, two shield electrode layers 52a and 52b are formed near the first side surface 14a of the dielectric substrate 14, The other two shield electrode layers 52 c and 52 d are formed near the fourth side surface 14 d of the dielectric substrate 14.
- the input electrode layer 48 is located in the vicinity of the second side surface 14 b of the dielectric substrate 14, and has a via hole 5 4 and an input tap formed in the fourth to sixth dielectric layers S 4 to S 6. It is electrically connected to the input-side resonance electrode 26 via the electrode 30.
- the output electrode layer 50 is located in the vicinity of the third side surface 14 c of the dielectric substrate 14, and has a via hole 56 formed between the fourth to sixth dielectric layers S 4 to S 6 and an output tap. It is electrically connected to the output-side resonance electrode 28 via the electrode 32.
- the two shield electrode layers 52a and 52b are connected to the short-circuited ends of the inner-layer shield electrodes 12a and 12b and the input-side resonance electrode 26 and the output-side resonance via the via holes 22 and 24, respectively.
- the other two shield electrode layers 52c and 52d are electrically connected to the short-circuited end of the electrode 28, and the inner shield electrodes 39, 40, through the via holes 45 and 47. It is electrically connected to 1 2 b.
- the diameters of the input electrode layer 48, the output electrode layer 50, and the four shield electrode layers 52a to 52d are larger than the diameters of the via holes 22, 24, 44 and 46 described above. It is set to a large value.
- the input electrode layer 48 forming the input terminal, the output electrode layer 50 forming the output terminal, and the shield terminal are formed on the dielectric substrate 14 by forming the four shield electrode layers 52 a to 52 d constituting the element in the lowermost dielectric layer S 7 with via holes. Is led out only to the lower surface.
- the terminals formed only on the lower surface of the dielectric substrate 14 may be mounted on the wiring board by the surface mounting method.
- the mounting area can be made smaller than that of the side mounting.
- the input terminal, the output terminal, and the shield terminal exist only on the lower surface of the dielectric substrate 14, the distance between each terminal and a plurality of electrodes constituting the filter section 16 becomes long, and the terminals float between these terminals. The capacitance is hardly formed. Therefore, the isolation characteristics of the passive component 10 A are improved.
- the passive component is hardly affected by other components in contact with the shield plate installed near the 1 O A, and fluctuations in characteristics can be reduced.
- the input electrode layer 48, the output electrode layer 50, and the shield electrode layers 52 a to 52 d are formed in the dielectric substrate 14 via holes. Since these layers are formed, it is possible to prevent the electrode layers from peeling off from the dielectric substrate 14 and to suppress the occurrence of cracks in each electrode layer.
- the above-described electrode layers 48, 50, and 52 a to 52 d are formed. Since it can be formed, the step of forming terminals on the lower surface of the dielectric substrate 14 can be omitted, and the step can be simplified. In addition, since the thickness of each of the electrode layers 48, 50 and 52a to 52d can be increased, the same mechanical strength as the conventional side terminal (terminal formed on the side surface of the dielectric substrate 14) is obtained. Obtainable.
- each electrode layer 48, 50 and 52a to 52d should be set to be larger than the diameter of each via hole 22, 24, 44, 45, 46 and 47.
- Figure 2 As shown in the figure, the facing area between the input wiring pattern 62 of the wiring board 60 and the input electrode layer 48, the facing area between the output wiring pattern 64 and the output electrode layer 50, and the shield wiring pattern 66 The areas opposed to the shield electrode layers 52a to 52d can be respectively increased, and generation of unnecessary inductance components can be suppressed.
- a passive component 10B according to a second embodiment will be described with reference to FIGS.
- the passive component 10B according to the second embodiment has substantially the same configuration as the passive component 1OA according to the above-described first embodiment, as shown in FIGS.
- the difference is that the side resonator 18 and the output side resonator 20 are formed by via holes 70 and 72, respectively.
- the input side resonator 18 extends from the vicinity of the first side surface 14 a to the fourth side surface 14 d on the main surface of the third dielectric layer S 3.
- a first electrode 74 extending to the vicinity, and a fourth surface from the vicinity of the first side surface 14a of the dielectric substrate 14 on the main surface of the fifth dielectric layer S5.
- the second electrode 76 formed and extending through the third and fourth dielectric layers S 3 and S 4, and extending to the center of the first electrode 74. It has the above-described via hole 0.70 that connects to the central portion of the second electrode 76.
- Both ends of the first electrode 74 are electrically connected to the inner-layer shield electrode 12b via via holes 78 and 79, respectively.
- an input tap electrode 30 is formed from a central portion thereof toward the second side surface 14 b of the dielectric substrate 14. That is, the first electrode 74 forms a short-circuit end of the input-side resonator 18.
- the second electrode 76 has a form facing the inner-layer shield electrode 12 b with the dielectric layer interposed therebetween, and forms an open end of the input-side resonator 18.
- the output-side resonator 20 is similar to the input-side resonator 18, from the vicinity of the first side surface 14 a to the vicinity of the fourth side surface 14 d on the main surface of the third dielectric layer S 3. And a first electrode 80 forming a short-circuit end of the output-side resonator 20, and a vicinity of the first side surface 14 a on the main surface of the fifth dielectric layer S 5 And a second electrode 82 extending from the second side to the fourth side 14 d and forming an open end of the output-side resonator 20. And the above-described via hole 72 penetrating through the fourth dielectric layers S 3 and S 4 and electrically connecting the first electrode 80 and the second electrode 82.
- Both ends of the first electrode 80 are electrically connected to the inner-layer shield electrode 12b through via holes 84 and 86, respectively.
- an output tap electrode 32 is formed from a central portion thereof toward the third side surface 14c of the dielectric substrate 14.
- a first side surface 14a of the dielectric substrate 14 is formed, and the first electrode 74 of the input-side resonator 18 and the output A first coupling adjustment electrode 88 opposed to the first electrode 80 of the side resonator 20 with the third dielectric layer S 3 interposed therebetween, and a fourth side surface 14 of the dielectric substrate 14
- the first electrode 74 of the input-side resonator 18 and the first electrode 80 of the output-side resonator 20 opposing the third dielectric layer S 3 are formed near d.
- two coupling adjustment electrodes 90 are formed near d.
- the passive component 10 B includes a single input electrode film 9 2 constituting an input terminal on the back surface of the seventh dielectric layer S 7 (the lower surface of the dielectric substrate 14). And one output electrode film 94 forming an output terminal, and two shield electrode films 96 and 98 forming a shield terminal.
- the input electrode film 92 is formed near the second side surface 14 b of the dielectric substrate 14, and the output electrode film 94 is formed near the third side surface 14 c of the dielectric substrate 14
- one shield electrode film 96 is located near the first side surface 14a of the dielectric substrate 14 and the second side surface.
- the shield electrode film 98 is formed so as to extend from the vicinity of 14 b to the vicinity of the third side surface 14 c, and the other shield electrode film 98 is in the vicinity of the fourth side surface 14 d of the dielectric substrate 14. Further, it is formed to extend from the vicinity of the second side surface 14b to the vicinity of the third side surface 14c.
- the input electrode film 92 is located near the second side surface 14 b of the dielectric substrate 14, and has a via hole 100 formed over the fifth and sixth dielectric layers S 5 and S 6.
- the output electrode film 94 is located in the vicinity of the third side surface 14 c of the dielectric substrate 14, and is a via hole 10 formed over the fifth and sixth dielectric layers S 5 and S 6. It is electrically connected to the second electrode 82 of the output-side resonator 20 via 2 and the output tap electrode 32.
- one shield electrode film 96 is located near the first side surface 14 a of the dielectric substrate 14 and has a via hole 1 that penetrates the second to seventh dielectric layers S 2 to S 7.
- the other two shield electrode films 98 are electrically connected to the inner-layer shield electrodes 12 a and 12 b through the fourth and first side surfaces 14 d and 14 d, respectively.
- the sixth and seventh dielectric layers S between the inner shield electrode 12 b and the lower surface of the dielectric substrate 14. 6 and S7 are made of a material having a dielectric constant of sr ⁇ 20.
- the passive component 10 B includes an input electrode film 92 forming an input terminal, an output electrode film 94 forming an output terminal, and two components forming a shield terminal.
- the shield electrode films 96 and 98 are formed on the back surface of the lowermost dielectric layer S7, the input terminals, output terminals and shield terminals are led out only to the lower surface of the dielectric substrate 14. I have.
- the mounting area of the passive component 10B can be made smaller than that in the case of side mounting.
- the isolation characteristics of the passive component 10B are improved.
- the manufacturing process is simplified, and the manufacturing cost can be reduced. Variations in characteristics can be reduced.
- the input-side resonator 18 and the output-side resonator 20 are formed by via holes 70 and 72, respectively, and the short-circuited end of the input-side resonator 18 is formed at one end of the via hole 70. It consists of electrodes 74, and the open end of input side resonator 18 is connected to the other end of via hole 70.
- the output side resonator 20 is constituted by the formed second electrode 76, the short-circuited end of the output side resonator 20 is constituted by the first electrode 80 formed at one end of the peer hole 72, and the output side resonator 20 is opened. Since the end is constituted by the second electrode 82 formed at the other end of the via hole 72, the following operation can be obtained.
- a portion of the input-side resonator 18 or the output-side resonator 20 that requires a capacitance for example, a connection between the first and second coupling adjustment electrodes 88 and 90 and the first electrodes 74 and 80.
- the Q value of the input side resonator 18 and the output side resonator 20 is increased by making the material with the rate ⁇ r (> 20) and making other dielectric layers with the material with high Q value. And low loss characteristics can be obtained.
- the passive component 10C according to the third embodiment has substantially the same configuration as the passive component 10B according to the above-described second embodiment.
- the shield electrode films 96 and 98 are not formed on the lower surface of the plate 14 and the inner shield electrode of the dielectric layers S1 to S7 constituting the dielectric substrate 14
- the sixth and seventh dielectric layers S 6 and S 7 between 12 b and the lower surface of the dielectric substrate 14 are made of a material having a dielectric constant of r (> 20). Different.
- the inner-layer shield electrode 12 b in the dielectric substrate 14 and the shield wiring pattern 66 of the wiring substrate 60 can be electrically connected via the capacitor.
- shield electrode films 96 and 98 constituting the shield terminals on the lower surface of the dielectric substrate 14.
- the dimensions of input terminals, output terminals, and shield terminals must be reduced, but in the third embodiment, it is necessary to form shield electrode films 96 and 98. Therefore, the dimensions of the input electrode film 92 and the output electrode film 94 can be increased. Thereby, the mechanical strength of the input electrode film 92 and the output electrode film 94 can be improved.
- a passive component 10D according to a fourth embodiment will be described with reference to FIG.
- the passive component 10D according to the fourth embodiment has substantially the same configuration as the passive component 1OA according to the first embodiment described above. 14 in that it has a filter section 16 and an unbalanced-to-balanced conversion section 120 (hereinafter simply referred to as a conversion section).
- the passive component 10 D includes a second dielectric layer S 2, a sixth dielectric layer S 6, a ninth dielectric layer S 9, and a first dielectric layer Inner-layer shield electrodes 12a, 122, 124 and 12b are respectively formed on the main surfaces of S11, and DC electrodes are formed on the main surface of the 10th dielectric layer S10. 1 2 6 is formed.
- a balanced input / output terminal 128 is formed on the lower surface of the second dielectric layer S 12 near the third side surface 14 c of the dielectric substrate 14, and the second side surface 14 2
- An unbalanced input / output terminal 130 and a DC terminal 132 are formed near b, and a shield terminal 134 is formed in the center.
- first to third resonators 13 6, 13 8, and 140 are respectively formed, and the first side surface 1 of the dielectric substrate 14 is respectively provided.
- the first to third resonance electrodes 14 2, 14 4 and 14 6 extending from the vicinity of 4 a to the vicinity of the fourth side surface 14 d, and the first resonance electrode 14 2 to the second And a lead electrode 148 extending toward the side surface 14b.
- the main surface of the third dielectric layer S3 faces the open ends of the first to third resonance electrodes 144, 144, and 146, and the fourth side surface of the dielectric substrate 14 Adjust the degree of coupling between the three inner-layer shield electrodes 15 0, 15 2 and 15 4 formed close to 14 d, and the first and second resonators 13 6 and 13 8 And a first coupling adjustment electrode 156 are formed.
- the ends near the first side surface 14 a of the dielectric substrate 14 are the second to sixth dielectric electrodes, respectively. It is connected to the inner-layer shield electrodes 12 a and 122 through via holes 158, 160 and 162 penetrating the body layers S 2 to S 6.
- the three inner-layer shield electrodes 15 0, 15 2, and 15 4 are respectively connected to the second to sixth dielectric layers S 2 to S at portions adjacent to the fourth side surface 14 d of the dielectric substrate 14. 6 are connected to the inner layer shield electrodes 12 a and 122 through via holes 16 6, 16 68 and 170.
- the inner shield electrode 1 2 2 is formed in the vicinity of the first side surface 14 a of the dielectric substrate 14 ′ in a via hole 1 7 2 penetrating through the sixth to 12th dielectric layers S 6 to S 12. And via holes penetrating through the sixth to 12th dielectric layers S6 to S12 in the vicinity of the fourth side surface 14d of the dielectric substrate 14 Through these steps, they are electrically connected to the inner shield electrodes 124 and 12b and to the shield terminals 134 formed on the lower surface of the dielectric substrate 14.
- the main surface of the fifth dielectric layer S5 has a second coupling adjustment electrode 180 for adjusting the degree of coupling between the second and third resonators 1380 and 140. And an output capacitance electrode 182 that overlaps with the third resonance electrode 146 and the fourth dielectric layer S4 interposed therebetween.
- a first stripline electrode 184 constituting the conversion section 120 is formed, and on the main surface of the eighth dielectric layer S8, Second and third strip line electrodes 186 and 188 that constitute the part 120 are formed.
- One end of the first strip line electrode 18 4 is electrically connected to the output capacitance electrode 18 2 through a via hole 190 passing through the fifth and sixth dielectric layers S 5 and S 6 .
- the other end of the first stripline electrode 184 is open.
- a region for insulating the via hole 190 that is, a region where the electrode film is not formed is secured.
- One end of the second stripline electrode 186 and one end of the third stripline electrode 188 are connected to via holes 192 and 199 both passing through the eighth and ninth dielectric layers S8 and S9. 4 is electrically connected to the DC electrodes 1 26.
- the other end of the second strip line electrode 186 and the other end of the third strip line electrode 188 are both located near the third side surface 14 c of the dielectric substrate 14, Electrically connected to the balanced input / output terminals 1 28 formed on the lower surface of the dielectric substrate 14 through the via holes 1 96 and 1 98 penetrating the first and second dielectric layers S 8 to S 12 I have.
- the DC electrode 126 has an overhanging electrode 200 projecting toward the second side surface 14 b of the dielectric substrate 14. Is electrically connected to a DC terminal 132 formed on the lower surface of the dielectric substrate 14 through a via hole 202 penetrating through the dielectric layers S10 to S12.
- the mounting area of the passive component 10D can be made smaller than that in the case of side mounting. it can.
- the isolation characteristics of the passive component 10D are improved.
- the manufacturing process is simplified, and the manufacturing cost can be reduced. Variations in characteristics can be reduced.
- the passive component 10E according to the fifth embodiment has substantially the same configuration as the passive component 1OA according to the first embodiment described above, as shown in FIG. The difference is that there is a lumped constant filter part 210 in 14.
- the inner shield electrode 212 is formed on the main surface of the 10th dielectric layer S10. Also, of the lower surface of the first dielectric layer S 11, a corner portion 2 1 4 including the first side surface 14 a and the third side surface 14 c of the dielectric substrate 14, Shield terminal at the part including the center of the side 14a, the corner part 2 16 including the second side 14b and the fourth side 14d, and the part including the center of the fourth side 14d. 2 18 a to 2 18 d are formed, and the input terminal 2 2 2 is connected to the part 2 220 including the third side 14 c and the fourth side 14 d of the dielectric substrate 14. An output terminal 226 is formed at a corner portion 224 of the formed dielectric substrate 154, which includes a first side surface 414a and a second side surface 414b.
- first to fifth inductor electrodes 228a to 228e for forming inductance are formed on the main surfaces of the second to fifth dielectric layers S2 to S5.
- the first to fifth inductor electrodes 228a to 228e are formed in a coil shape via via holes 230, 232, 234, and 236, respectively.
- first to fourth capacitor electrodes 238a to 238d for forming capacitors are formed on the main surfaces of the seventh to ninth dielectric layers S7 to S9.
- the first capacitor electrode 2 38 a is formed on the main surface of the seventh dielectric layer S 7 at a corner portion including the first side surface 14 a and the second side surface 14 b of the dielectric substrate 14.
- the second capacitor electrode 238 b is formed closer to 2 24, and the third side surface 14 c of the dielectric substrate 14 and the fourth side of the fourth surface of the main surface of the eighth dielectric layer S 8.
- the corner portion including the side surface 14 d is formed closer to 220.
- the third capacitance electrode 2 3 8 c is formed on the main surface of the ninth dielectric layer S 9 near the corner 2 2 4 of the dielectric substrate 14, and the fourth capacitance electrode 2 3 8 d is formed on the main surface of the ninth dielectric layer S9 near the corner part 220.
- One end of the first inductor electrode 2 28 a is located near the corner portion 220 of the second dielectric layer S 2, and the second to eleventh dielectric layer S 2
- the second capacitor electrode 238 b, the fourth capacitor electrode 238 d, and the input terminal 2 2 2 formed on the lower surface of the dielectric substrate 14 through a via hole 240 penetrating through 2 to S 11. Connected.
- the fifth inductor electrode 228 e is located close to the corner portion 224 of the sixth dielectric layer S 6, and the sixth to eleventh dielectric layer S 6 to S 11 through a via hole 2 42 to the first capacitor electrode 2 38 a, the third capacitor electrode 2 38 c and the output terminal 2 2 6 formed on the lower surface of the dielectric substrate 14.
- the mounting area of the passive component 10E can be made smaller than that in the case of side mounting. it can.
- the isolation characteristics of the passive component 10 E are improved. Manufacturing The process is simplified, and the manufacturing cost can be reduced. Variations in characteristics can be reduced.
- the input terminal 222 and the output terminal 226 are diagonal.
- An example is shown in which the shield terminals 218 a to 218 d are arranged on the upper part and other parts are arranged.
- eight terminals are provided on the lower surface of the dielectric substrate 14.
- I / O terminals 250a to 250d and shield terminals 252a to 252d may be arranged in a pin arrangement.
- the isolation between the input / output terminals 250a to 250d must be ensured because the distance between the input / output terminals 250a to 250d is far and the adjacent terminals are the shield terminals 252a to 252d. Can be.
- the passive component according to the present invention is not limited to the above-described embodiment, and may adopt various configurations without departing from the gist of the present invention.
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- Control Of Motors That Do Not Use Commutators (AREA)
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Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/551,273 US7348868B2 (en) | 2003-04-01 | 2004-04-01 | Passive component having stacked dielectric layers |
CN200480009029A CN100594631C (zh) | 2003-04-01 | 2004-04-01 | 无源元件 |
EP04725162.4A EP1610408B1 (en) | 2003-04-01 | 2004-04-01 | Passive component |
EP16176336.2A EP3098900B1 (en) | 2003-04-01 | 2004-04-01 | Passive component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2003098608A JP2004312065A (ja) | 2003-04-01 | 2003-04-01 | 受動部品 |
JP2003-098608 | 2003-04-01 |
Publications (1)
Publication Number | Publication Date |
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WO2004091036A1 true WO2004091036A1 (ja) | 2004-10-21 |
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Family Applications (1)
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PCT/JP2004/004765 WO2004091036A1 (ja) | 2003-04-01 | 2004-04-01 | 受動部品 |
Country Status (6)
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US (1) | US7348868B2 (ja) |
EP (2) | EP3098900B1 (ja) |
JP (1) | JP2004312065A (ja) |
KR (1) | KR100744203B1 (ja) |
CN (1) | CN100594631C (ja) |
WO (1) | WO2004091036A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1816701A1 (en) * | 2004-11-26 | 2007-08-08 | Soshin Electric Co. Ltd. | Passive part |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004312065A (ja) | 2003-04-01 | 2004-11-04 | Soshin Electric Co Ltd | 受動部品 |
US7369018B2 (en) * | 2004-08-19 | 2008-05-06 | Matsushita Electric Industrial Co., Ltd. | Dielectric filter |
JP4640218B2 (ja) * | 2006-02-28 | 2011-03-02 | Tdk株式会社 | 積層型誘電体共振器およびバンドパスフィルタ |
JP3883565B1 (ja) * | 2006-02-28 | 2007-02-21 | Tdk株式会社 | チップアンテナ |
KR100712419B1 (ko) * | 2006-06-08 | 2007-04-27 | 전자부품연구원 | 대역통과필터 |
US7649431B2 (en) * | 2006-10-27 | 2010-01-19 | Samsung Electro-Mechanics Co., Ltd. | Band pass filter |
US8330555B2 (en) * | 2007-08-29 | 2012-12-11 | Kyocera Corporation | Bandpass filter, and wireless communication module and wireless communication apparatus which employ the bandpass filter |
JP4506903B2 (ja) * | 2008-01-17 | 2010-07-21 | 株式会社村田製作所 | 積層型共振器および積層型フィルタ |
JP5545369B2 (ja) * | 2010-07-06 | 2014-07-09 | 株式会社村田製作所 | 方向性結合器 |
CN203734631U (zh) * | 2011-11-09 | 2014-07-23 | 株式会社村田制作所 | 层叠型lc滤波器 |
WO2014045648A1 (ja) * | 2012-09-19 | 2014-03-27 | 株式会社村田製作所 | フィルタ |
CN108370082B (zh) * | 2015-12-16 | 2021-01-08 | 库姆网络公司 | 时延滤波器 |
WO2018070145A1 (ja) | 2016-10-11 | 2018-04-19 | 株式会社村田製作所 | 電子部品 |
JP7232083B2 (ja) * | 2019-03-05 | 2023-03-02 | 太陽誘電株式会社 | フィルタ |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06104606A (ja) * | 1992-09-24 | 1994-04-15 | Tdk Corp | バンドパスフィルタ |
WO2001069710A1 (fr) * | 2000-03-15 | 2001-09-20 | Matsushita Electric Industrial Co., Ltd. | Composant electronique multicouche, duplexeur d'antenne multicouche, et appareil de communication |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1541990B2 (de) * | 1967-10-12 | 1976-09-23 | Siemens AG, 1000 Berlin und 8000 München | Mikrowellenfilter in gedruckter schaltungstechnik |
JPH0385903A (ja) * | 1989-08-30 | 1991-04-11 | Kyocera Corp | 帯域通過フィルタ |
JP2996510B2 (ja) * | 1990-11-30 | 2000-01-11 | 株式会社日立製作所 | 電子回路基板 |
JP2851966B2 (ja) | 1992-03-27 | 1999-01-27 | 日本碍子株式会社 | 積層型誘電体フィルター |
JPH06132706A (ja) * | 1992-09-07 | 1994-05-13 | Murata Mfg Co Ltd | 誘電体共振部品 |
JP2860018B2 (ja) | 1992-09-16 | 1999-02-24 | 日本碍子株式会社 | 誘電体フィルタ |
JPH077306A (ja) | 1993-06-17 | 1995-01-10 | Ube Ind Ltd | 誘電体フィルタ及びその実装方法 |
JPH0832308A (ja) | 1994-07-15 | 1996-02-02 | Toko Inc | 誘電体フィルタとその特性調整方法 |
JPH0887787A (ja) | 1994-09-14 | 1996-04-02 | Toshiba Corp | 磁気記録再生装置 |
JP3434937B2 (ja) * | 1995-07-07 | 2003-08-11 | 京セラ株式会社 | フィルター |
JP3127792B2 (ja) | 1995-07-19 | 2001-01-29 | 株式会社村田製作所 | Lc共振器およびlcフィルタ |
JPH09214204A (ja) | 1996-02-01 | 1997-08-15 | Sumitomo Kinzoku Electro Device:Kk | 積層フィルタ |
US6133809A (en) * | 1996-04-22 | 2000-10-17 | Murata Manufacturing Co., Ltd. | LC filter with a parallel ground electrode |
JPH1028006A (ja) | 1996-07-10 | 1998-01-27 | Kyocera Corp | 積層共振器および積層誘電体フィルタならびに積層誘電体フィルタの共振特性調整方法 |
JP4023698B2 (ja) | 1996-11-15 | 2007-12-19 | シチズン電子株式会社 | 下面電極付き側面使用電子部品の製造方法 |
US5834994A (en) * | 1997-01-17 | 1998-11-10 | Motorola Inc. | Multilayer lowpass filter with improved ground plane configuration |
JPH10335903A (ja) | 1997-05-28 | 1998-12-18 | Sharp Corp | 電圧制御通過帯域可変フィルタ、電圧制御共振周波数可変共振器およびそれらを用いる高周波回路モジュール |
US5977850A (en) * | 1997-11-05 | 1999-11-02 | Motorola, Inc. | Multilayer ceramic package with center ground via for size reduction |
JPH11346104A (ja) | 1998-05-29 | 1999-12-14 | Philips Japan Ltd | 誘電体フィルタ |
JP2000151206A (ja) | 1998-11-06 | 2000-05-30 | Ngk Insulators Ltd | 積層型誘電体フィルタ |
JP2000165171A (ja) | 1998-11-30 | 2000-06-16 | Murata Mfg Co Ltd | Lc共振器部品及びlcフィルタ |
JP2001189605A (ja) | 1999-10-21 | 2001-07-10 | Matsushita Electric Ind Co Ltd | セラミック積層rfデバイス |
JP2001217607A (ja) * | 2000-02-03 | 2001-08-10 | Ngk Insulators Ltd | アンテナ装置 |
KR20010094784A (ko) * | 2000-04-06 | 2001-11-03 | 윤종용 | 커패시터 보상회로를 갖는 콤라인 구조의 무선필터 |
JP2002261643A (ja) | 2001-02-28 | 2002-09-13 | Tdk Corp | 無線通信モジュール |
JP2002280805A (ja) | 2001-03-15 | 2002-09-27 | Matsushita Electric Ind Co Ltd | 誘電体フィルタおよびそれを用いたアンテナ共用器と通信機器 |
JP2002270465A (ja) * | 2001-03-08 | 2002-09-20 | Soshin Electric Co Ltd | 積層電子部品の端子電極 |
US7023301B2 (en) * | 2001-05-16 | 2006-04-04 | Matsushita Electric Industrial Co., Ltd. | Laminated filter with a single shield conductor, integrated device, and communication apparatus |
EP1265358A3 (en) * | 2001-05-25 | 2008-11-12 | Toko Kabushiki Kaisha | Laminated electronic component |
JP2003087008A (ja) * | 2001-07-02 | 2003-03-20 | Ngk Insulators Ltd | 積層型誘電体フィルタ |
US6483404B1 (en) | 2001-08-20 | 2002-11-19 | Xytrans, Inc. | Millimeter wave filter for surface mount applications |
JP2003078103A (ja) | 2001-08-31 | 2003-03-14 | Kyocera Corp | 回路基板 |
JP2003086755A (ja) | 2001-09-11 | 2003-03-20 | Sony Corp | ハイブリッドモジュール |
JP2003087005A (ja) | 2001-09-12 | 2003-03-20 | Koa Corp | 多層バンドパスフィルタ及びその製造方法 |
JP2004297764A (ja) * | 2003-03-07 | 2004-10-21 | Murata Mfg Co Ltd | バンドパスフィルタ |
JP2004312065A (ja) | 2003-04-01 | 2004-11-04 | Soshin Electric Co Ltd | 受動部品 |
US20050088258A1 (en) * | 2003-10-27 | 2005-04-28 | Xytrans, Inc. | Millimeter wave surface mount filter |
-
2003
- 2003-04-01 JP JP2003098608A patent/JP2004312065A/ja active Pending
-
2004
- 2004-04-01 US US10/551,273 patent/US7348868B2/en not_active Expired - Lifetime
- 2004-04-01 EP EP16176336.2A patent/EP3098900B1/en not_active Expired - Lifetime
- 2004-04-01 WO PCT/JP2004/004765 patent/WO2004091036A1/ja active Application Filing
- 2004-04-01 CN CN200480009029A patent/CN100594631C/zh not_active Expired - Lifetime
- 2004-04-01 EP EP04725162.4A patent/EP1610408B1/en not_active Expired - Lifetime
- 2004-04-01 KR KR1020057018527A patent/KR100744203B1/ko active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06104606A (ja) * | 1992-09-24 | 1994-04-15 | Tdk Corp | バンドパスフィルタ |
WO2001069710A1 (fr) * | 2000-03-15 | 2001-09-20 | Matsushita Electric Industrial Co., Ltd. | Composant electronique multicouche, duplexeur d'antenne multicouche, et appareil de communication |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1816701A1 (en) * | 2004-11-26 | 2007-08-08 | Soshin Electric Co. Ltd. | Passive part |
EP1816701A4 (en) * | 2004-11-26 | 2007-11-21 | Soshin Electric | PASSIVE PART |
CN101065879B (zh) * | 2004-11-26 | 2013-03-27 | 双信电机株式会社 | 无源部件 |
Also Published As
Publication number | Publication date |
---|---|
EP1610408A1 (en) | 2005-12-28 |
US20060192637A1 (en) | 2006-08-31 |
EP1610408B1 (en) | 2017-06-21 |
KR20050122228A (ko) | 2005-12-28 |
EP1610408A4 (en) | 2006-08-30 |
CN1768444A (zh) | 2006-05-03 |
EP3098900A1 (en) | 2016-11-30 |
JP2004312065A (ja) | 2004-11-04 |
CN100594631C (zh) | 2010-03-17 |
EP3098900B1 (en) | 2020-05-06 |
KR100744203B1 (ko) | 2007-08-01 |
US7348868B2 (en) | 2008-03-25 |
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