WO2004040581A1 - メモリ装置、動きベクトルの検出装置および検出方法 - Google Patents
メモリ装置、動きベクトルの検出装置および検出方法 Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/43—Hardware specially adapted for motion estimation or compensation
- H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/144—Movement detection
- H04N5/145—Movement estimation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/20—Analysis of motion
- G06T7/223—Analysis of motion using block-matching
- G06T7/231—Analysis of motion using block-matching using full search
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/43—Hardware specially adapted for motion estimation or compensation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
- H04N19/51—Motion estimation or motion compensation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/10—Image acquisition modality
- G06T2207/10016—Video; Image sequence
Definitions
- the present invention relates to a memory device, a motion vector detection device, and a detection method. More specifically, the present invention activates a plurality of word lines at the same time, combines the charges stored in the capacitors of a plurality of memory cells connected to the plurality of word lines on one bit line, and responds to the total amount of the charges.
- the present invention relates to a memory device capable of simultaneously reading data and performing calculations by outputting a digital signal having a calculated value, thereby improving the calculation speed and reducing costs by reducing the number of processing units. is there.
- the present invention stores the pixel data of the first frame in a unit of a plurality of memory cells arranged in the direction in which the bit lines extend in a straight binary format, and stores the pixel data of the second frame in the direction in which the bit lines extend.
- the data is stored in a unit consisting of a plurality of memory cells arranged in a two's complement format, and the code lines relating to the pixel data of the first and second frames are simultaneously activated and connected to the plurality of code lines.
- the present invention relates to a memory device which can obtain the difference data at high speed and at low cost.
- data is stored in units of a plurality of memory cells arranged in a direction in which a bit line extends, and word lines relating to a plurality of data are simultaneously activated.
- word lines relating to a plurality of data are simultaneously activated.
- the present invention generates, for each pixel of the reference frame, an absolute difference value between the pixel data and the pixel data at a plurality of search positions in the search frame, and uses the generated absolute difference value to generate the reference frame.
- For each reference block in Generates a sum of absolute differences between a plurality of candidate blocks in the search range of the search frame corresponding to the reference block of the reference frame, and, for each reference block of the reference frame, based on the plurality of sums of the generated difference absolute values.
- the present invention relates to a motion vector detecting device and a detecting method which can detect a motion vector at high speed and at low cost by adopting a configuration for detecting a motion vector corresponding to this reference block. It is. Background art
- FIG. 1 shows a configuration example of a conventional memory block 300.
- the memory block 300 has a memory cell array 310, a storage data input / output port 30, a row address decoder 330, and a control circuit 340.
- the memory cell array 310 has a plurality of bit lines BL extending in a row direction (row direction) for transferring data and a plurality of bit lines BL extending in a column direction (column direction). It consists of orthogonal word lines WL and memory cells ML connected to these bit lines BL and word lines WL and arranged in a matrix.
- the memory cell ML has a DRAM structure and includes an access transistor and a capacitor C. One end of the capacitor C is grounded, and the other end is connected to the bit line BL via the access transistor T. Further, the gate of the access transistor T is connected to a lead line WL. Reading and writing to the memory cell ML are performed by activating the word line WL to turn on the access transistor T, as is well known in the art.
- the storage data input / output port 320 includes a column address decoder 321, an address buffer 322, and an I / O buffer 332.
- the column address decoder 321 includes an IZO gate (column switch), a sense amplifier, and the like. The column address is input to the column address decoder 321 via the address buffer 322.
- the column address decoder 321 corresponds to the column address supplied via the address buffer 322, and stores a plurality of bits connected to a plurality of predetermined memory cells ML in the column direction of the memory cell array 310. Secure connection with line BL, 1 0 Through the buffer 223 and the column address decoder 321, storage data can be written to and read from a predetermined memory cell ML in the column direction.
- an address is input to the row address decoder 330 via the address buffer 331.
- the row address decoder 330 connects the read line WL connected to a predetermined memory cell ML in the opening direction of the memory cell array 310 in accordance with the row address supplied via the address buffer 331. It is activated to enable writing and reading of storage data to and from a predetermined memory cell ML in the row direction through the I / O buffer 32 3 and the column address decoder 32 1.
- the control circuit 340 controls the operation of each of the above-described circuits of the memory block 300 based on the control input.
- motion vector detection is one of the important elements, and a typical method is block matching. This means that for a certain pixel block (reference block) that constitutes a part of a certain frame (reference frame), the same shape pixel block (candidate block) at various positions in a different time frame (search frame) The relative displacement between the target block and the target block with the highest correlation is regarded as the motion vector in the reference block.
- the area where the candidate block is assumed is the search range.
- the sum of the absolute values of the difference in pixel data between the pixels corresponding to the reference block and the candidate block for each pixel in the block that is, the sum of the absolute differences is often used.
- the sum of the absolute differences of the candidate blocks within the search range for one reference block is obtained, and the portion having the smallest sum of the absolute differences is regarded as the motion vector in pixel units.
- FIG. 3 shows a configuration example of a conventional motion vector detection circuit 200.
- the motion vector detection circuit 200 includes an input terminal 201 to which the image signal Di of the reference frame is input, a reference frame memory 202 for storing the image signal Di of the reference frame, and a search frame. And a search frame memory 203 for accumulating the image signals.
- the image signal Di of a certain frame is supplied from the input terminal 201 to the frame memory 202 and written therein, the image signal of the previous frame stored in the frame memory 202 is read out. Then, it is supplied to the frame memory 203 and written.
- the motion vector detection circuit 200 calculates the pixel data of the reference block from the frame memory 202 and the pixels of a plurality of candidate blocks in the search range corresponding to the reference block from the frame memory 203. And an arithmetic circuit for inputting the data and calculating, for each of the plurality of candidate blocks, the absolute difference between the pixel data of the candidate block and the pixel data of the reference block for each corresponding pixel data, and outputting the calculated absolute value. have.
- the arithmetic circuit 204 adds the pixel data of the reference block and the pixel data of the target block converted from straight binary data to two's complement data by the two's complement converter 204a.
- the difference data is obtained by adding in the unit 204b, and the absolute value of the difference data is obtained in the absolute value conversion unit 204c to obtain the absolute value of the difference.
- the motion vector detection circuit 200 accumulates the difference absolute value of each pixel data corresponding to each of the plurality of weather trap blocks output from the arithmetic circuit 204 to obtain the sum of the difference absolute values.
- An arithmetic unit 205 and an absolute difference sum holding unit 206 for holding the sum of absolute differences for each of the plurality of detection blocks obtained by the sum calculating unit 205 are provided.
- the motion vector detection circuit 200 also calculates a motion vector based on the difference absolute value sum for each of the plurality of candidate blocks held in the difference absolute value sum holding unit 206.
- the minimum value determination unit 207 detects the position of the candidate block that generates the minimum sum of absolute differences as a motion vector.
- the image signal Di input to the input terminal 201 is supplied to the reference frame memory 202 and stored as a reference frame image signal. At this time, the image signal of the previous frame stored in the frame memory 202 is read out, supplied to the frame memory 203, and accumulated as the image signal of the search frame.
- Image data of the reference block is read from the frame memory 202 and supplied to the arithmetic circuit 204. Further, pixel data of a plurality of candidate blocks in a search range corresponding to the reference block is read and supplied to the arithmetic circuit 204. Then, the arithmetic circuit 204 calculates and outputs, for each of the plurality of candidate blocks, the absolute difference between the pixel data of the candidate block and the pixel data of the reference block for each corresponding pixel data. .
- the absolute difference values of the pixel data corresponding to each of the plurality of candidate blocks, which are output from the arithmetic circuit 204, are sequentially supplied to the summation operation unit 205 to obtain the sum of absolute difference values.
- the sum of absolute difference values for each of the plurality of candidate blocks from the sum operation unit 205 is supplied to and held by the sum of absolute difference value storage unit 206.
- the minimum value determining unit 206 generates the minimum difference absolute value sum based on the difference absolute value sums of the plurality of candidate blocks held in the difference absolute value holding unit 206 as described above.
- the position of the weather trap block is detected as a motion vector, and the motion vector is held in the motion vector holding unit 208.
- Pixel data of a plurality of reference blocks in the reference frame is sequentially supplied from the frame memory 202 to the arithmetic circuit 204. Then, pixel data of a plurality of candidate blocks is supplied from the frame memory 203 to the arithmetic circuit 204 in correspondence with the pixel data of each reference block. Therefore, for each reference block, the arithmetic circuit 204, the summation operation unit 205, the difference absolute value sum holding unit 206, the minimum value judgment unit 207 and The operation described above is repeated in the motion vector holding unit 208, and accordingly, the minimum value judging unit 208 sequentially detects the motion vector corresponding to each reference block, and the motion vector is stored in the motion vector holding unit. The values are sequentially stored in 208.
- the motion vectors corresponding to the respective reference blocks held in the motion vector holding unit 208 are sequentially read.
- the read motion vector MV is output to the output terminal 209.
- the motion vector MV output in this way is used, for example, for motion compensation processing when performing motion compensation prediction coding.
- the flowchart of FIG. 4 shows the procedure of the motion vector MV detection process in the motion vector detection circuit 200 described above.
- step ST21 the processing is started.
- step ST22 the image signal stored in the reference frame memory 202 is read out, and this image signal is used as the image signal of the search frame in the search frame memory.
- step ST23 the image signal Di of the reference frame is input from the input terminal 201, and the image signal is written in the reference frame memory 202.
- step ST24 the pixel data of the reference block is read from the reference frame memory 202, and in step ST25, it is within the search range corresponding to the reference block from the search frame memory 203.
- the pixel data of the candidate block is read out and converted from straight binary data to two's complement data by a two's complement converter 204a.
- step ST27 the difference data is obtained by adding the pixel data of the reference block and the pixel data of the catch block converted into the data of the 2's catch format in the straight binary format.
- step ST28 the absolute value of the difference data is obtained, and the difference absolute value between the pixel data of the reference block and the candidate block is generated.
- step ST 29 the sum of absolute differences between a certain reference block and a predetermined candidate block is calculated by the sum calculation unit 205 and stored in the holding unit 206. Then, in step ST31, it is determined whether or not the generation of the sum of absolute differences between a certain reference block and all the candidate blocks has been completed. If not, the process returns to step ST25 to generate the sum of absolute differences between a certain reference block and the next candidate block. Move on to the processing to be performed. On the other hand, when the operation has been completed, the process proceeds to step ST32.
- step ST32 the position of the candidate block that generates the minimum sum of absolute differences is detected as a motion vector based on the sum of absolute differences held in the holding unit 206 corresponding to a certain reference block. Then, in step ST33, the detected moving vector is stored in the moving vector holding unit 208.
- step ST34 it is determined whether or not the above-described motion vector detection processing has been completed for all reference blocks of the reference frame. If not, the process returns to step ST24 to move to the process of detecting a motion vector corresponding to the next reference block.
- step ST35 the motion vectors MV corresponding to the respective reference blocks held in the motion vector holding unit 208 are sequentially output, and the process ends in step ST36.
- Another object of the present invention is to provide a memory device that can obtain difference data of pixel data of the first and second frames at high speed and at low cost. It is still another object of the present invention to provide a memory device capable of obtaining additional data of a plurality of data at high speed and at low cost.
- a memory device is a memory device capable of coupling, on a single bit line, charges accumulated in capacitors of a plurality of memory cells connected to a plurality of activated word lines. Activating means for simultaneously activating the capacitors of the plurality of memory cells connected to the plurality of ground lines activated by the activating means. 13204
- a signal output means for outputting a digital signal having a value corresponding to the total amount of charge obtained by combining the stored charges on one bit line.
- a plurality of word lines are activated simultaneously.
- the charges stored in the capacitors of the memory cells connected to the activated word lines are combined on one bit line.
- a digital signal having a value corresponding to the total charge is output.
- a digital signal having a value corresponding to the total charge is obtained by converting the total charge into a voltage signal having a value corresponding to the total charge, and then converting the voltage signal from an analog signal to a digital signal.
- converting a voltage signal into a digital signal it is possible to obtain a digital signal of any gradation depending on the function of the AZD converter.
- the operation results of the two or more data are obtained as digital signals by simultaneously activating the plurality of lead lines related to the two or more data.
- data to be added is stored in a unit including a plurality of memory cells connected to a plurality of read lines related to each data, a result of addition of the data is stored as a digital signal. can get.
- a unit composed of a plurality of memory cells connected to a plurality of word lines related to each data stores the subtrahend data or the subtrahend data, thereby obtaining a subtraction result of the data as a digital signal.
- the minuend data is data in straight binary format
- the minuend data is data in two's complement format.
- a plurality of word lines are simultaneously activated, the charges stored in the capacitors of the plurality of memory cells connected to the plurality of word lines are combined on one bit line, and a value corresponding to the total amount of the charges is combined. It is configured to output a digital signal, which enables simultaneous processing of data reading and calculation, thereby improving calculation speed and reducing costs by reducing the number of calculation units.
- the number of memory cells for storing one data can be reduced by including a plurality of memory cells connected to one bit line having different capacitances of capacitors. For example, if one piece of data is N-bit data (N is an integer for control), the number of word lines related to this one piece of data is N.
- the capacitors of the N memory cells connected to the lead line have a capacity corresponding to the weight of each bit of the N-bit data.
- the number of memory cells for storing N-bit data is N.
- the capacity of each memory cell capacitor is the same, 2 N — 1 memory cells are needed to store N-bit data.
- a memory device includes a plurality of memory cells connected to a bit line and a word line and arranged in a matrix, and includes a first frame memory unit that stores an image signal of a first frame.
- a first frame memory comprising a plurality of memory cells each connected to a bit line and a word line, arranged in a matrix, and storing an image signal of a second frame.
- the second frame memory section and the second frame memory section are formed continuously in the row direction, which is the direction in which the bit lines extend, and in the first frame memory section and the second frame memory section,
- the first frame memory unit and the second frame memory can be coupled with each other in the plurality of memory cells connected to the plurality of activated ground lines.
- the unit is divided into a plurality of memory cells connected to each bit line into units of a predetermined number of memory cells connected to a predetermined word line, and each of the divided units has one pixel data.
- each unit of the first frame memory unit in the form of a straight binary in each of the pixel data constituting the image signal of the first frame
- each unit of the second frame memory unit is stored in the unit.
- the pixel data constituting the image signal of the second frame is stored in the form of 2's complement, and a plurality of word lines related to the predetermined data of the first frame memory section and the second frame memory section.
- Activating means for simultaneously activating a plurality of lead lines relating to predetermined data; bit line selecting means for selecting any one of the plurality of bit lines; Tsu the total amount of charges obtained on the selected bit line by preparative line selecting means is shall further comprising a signal output means for outputting a digital signal having a value corresponding.
- the present invention includes first and second frame memory units.
- Each of these frame memory sections is connected to a bit line and a word line, and is composed of a plurality of memory cells arranged in a matrix.
- These frame memory sections In this technology, it is possible to combine the charges stored in the capacitors of a plurality of memory cells connected to a plurality of activated ground lines on one bit line.
- These frame memory sections are formed continuously in a row direction in which the bit lines extend.
- a plurality of memory cells connected to each bit line are divided into units for each of a predetermined number of memory cells connected to a predetermined number of word lines, and each divided unit is divided into units. Each pixel data is stored.
- Pixel data constituting the image signal of the first frame is stored in each unit of the first frame memory unit in a straight binary format, and each unit of the second frame memory unit is stored in the second unit.
- the pixel data constituting the image signal of the frame is stored in the form of a census of two.
- each bit line By simultaneously activating a plurality of read lines related to predetermined data in the first frame memory unit and a plurality of read lines related to predetermined data in the second frame memory unit, each bit line Thus, the charges stored in the capacitors of the memory cells connected to the activated word lines are combined. Then, a digital signal having a value corresponding to the total charge obtained on one selected bit line is output.
- each unit of the first frame memory unit stores pixel data constituting the image signal of the first frame in a straight binary format
- each unit of the second frame memory unit stores the pixel data. Since the pixel data that constitutes the image signal of the second frame is stored in the form of a census of two, the total amount of charge obtained on each bit line is the pixel data of the first and second frames. It corresponds to the difference value of. Thereby, a subtraction result of the pixel data of the first and second frames is obtained as the above-described digital signal.
- the pixel data of the first frame is stored in a unit of a plurality of memory cells arranged in the direction in which the bit lines extend in a straight binary format
- the pixel data of the second frame is stored in the direction in which the bit lines extend.
- the data is stored in a unit composed of a plurality of memory cells arranged in a row in the form of two's complement data, and the read lines associated with the pixel data of the first and second frames are simultaneously activated and connected to the read lines.
- the difference data of the frame pixel data can be obtained at high speed and at low cost.
- a predetermined line in the first frame is It is possible to obtain the result of subtracting the pixel data from the line of the second frame at a position shifted by a predetermined number of lines in the vertical direction (row direction).
- N is a positive integer
- the number of code lines related to this one data is N
- the number of N lines connected to the N number of line lines is N.
- the capacitor of the memory cell has a capacity corresponding to the weight of each bit of N-bit data.
- the number of memory cells for storing N-bit data is N.
- each memory cell has the same capacitor, 2 N -1 memory cells are required to store N-bit data.
- the memory device includes a memory unit including a plurality of memory cells arranged in a matrix, each of which is connected to a bit line and a word line. Multiple connected to multiple activated lead lines It is possible to couple the accumulated charges of the capacitors of the memory cells of the memory cells, and the memory section is configured such that a plurality of memory cells connected to each bit line are connected to a predetermined number of word lines and a predetermined number of memory cells are connected.
- Activating means for simultaneously activating the code lines relating to a plurality of data, and one of the plurality of bit lines, wherein one unit of data is stored in each of the divided units.
- Bit line selecting means for selecting one bit line, and signal output means for outputting a digital signal having a value corresponding to the total amount of charge obtained on the bit line selected by the bit line selecting means. ⁇ .
- a memory section comprising a plurality of memory cells arranged in a matrix and connected to a bit line and a word line, respectively.
- this memory section it is possible to combine the charges stored in the capacitors of a plurality of memory cells connected to a plurality of activated word lines on one bit line.
- a plurality of memory cells connected to each bit line are divided into units for each of a predetermined number of memory cells connected to a predetermined number of word lines, and one unit is assigned to each of the divided units. Pieces of data are stored.
- the accumulated charges of the capacitors of the plurality of memory cells connected to the plurality of activated pad lines are coupled on each bit line. You. Then, a digital signal having a value corresponding to the total amount of electric charge obtained on one selected bit line is output. This digital signal corresponds to the result of adding a plurality of data.
- data is stored in each of the units composed of a plurality of memory cells arranged in the direction in which the bit lines extend, and the code lines associated with the plurality of data are simultaneously activated, so that the plurality of word lines connected to the plurality of word lines are
- the addition of multiple data can be performed at high speed and at low cost Can be obtained.
- the memory unit has units corresponding to a plurality of pixel positions of one frame in a row direction in which a bit line extends, and corresponds to a search position in a column direction in which a word line extends. Have the number of units specified.
- the duplication of each row in this memory section In the numerical cut, data of the absolute value of the difference between the pixel data at the pixel position of the corresponding reference frame and the pixel data at a plurality of search positions of the search frame is stored.
- the motion vector detecting device uses the image signal of the reference frame and the image signal of the search frame, and for each pixel of the reference frame, the pixel data and the image of a plurality of search positions of the search frame.
- a difference absolute value generation means for generating a difference absolute value with respect to data; and a reference absolute value generated by the difference absolute value generation means, for each reference block of the reference frame, the reference block and the reference.
- a motion vector detecting means for detecting a motion vector corresponding to the reference block based on a plurality of sums of absolute differences generated by the generating means.
- the motion vector detection method uses the image signal of the reference frame and the image signal of the search frame, and for each pixel of the reference frame, the pixel data and the pixels at a plurality of search positions in the search frame. Generating a difference absolute value from the data; and using the generated difference absolute value, for each reference block of the reference frame, a plurality of search blocks corresponding to the reference block and a search frame corresponding to the reference block within a search range. Generating a sum of absolute differences between each of the candidate blocks of the reference frame; and, for each reference block of the reference frame, a motion vector corresponding to the reference block based on the plurality of sums of the generated absolute differences. And a step of detecting
- the image signal of the reference frame and the image signal of the search frame are used, and for each pixel of the reference frame, the absolute difference between the pixel data and the pixel data at a plurality of search positions in the search frame is calculated. Generated. In this case, all difference absolute values required to obtain the motion vectors of all the reference blocks of the reference frame by the block matching method are generated. The generated absolute difference value is used to determine, for each reference block of the reference frame, the absolute difference between the reference block and each of a plurality of candidate blocks within the search range of the search frame corresponding to the reference block. A sum of values is generated. In this case, for example, it is possible to obtain the sum of absolute differences by adding the absolute values of the differences between the reference block and the predetermined candidate block at once.
- a motion vector corresponding to the reference block is detected based on the generated sums of the absolute values of the differences.
- the position of the candidate block corresponding to the sum of absolute values of the differences between the minimum values is detected as a motion vector.
- the absolute value of the difference between the pixel data and the pixel data at a plurality of search positions in the search frame is generated, and the generated absolute value of the difference is used as a reference.
- a sum of absolute differences between this reference block and each of a plurality of candidate blocks within the search range of the search frame corresponding to this reference block is generated, and each reference block of the reference frame is generated.
- FIG. 1 is a block diagram showing a configuration example of a conventional memory block.
- FIG. 2 is a diagram showing a part of a memory cell array in a conventional memory block.
- FIG. 3 is a block diagram showing a configuration of a conventional motion vector detection circuit.
- FIG. 4 is a flowchart showing a processing procedure of a conventional motion vector detection.
- FIG. 5 is a block diagram showing a configuration of the motion-compensated prediction encoding apparatus according to the embodiment.
- FIG. 6 is a diagram for explaining the block matching method.
- FIGS. 7A and 7B are diagrams for explaining the block matching method.
- FIG. 8A, FIG. 8B and FIG. 8C are diagrams for explaining the block matching method.
- FIG. 9 is a diagram for explaining the block matching method.
- FIG. 10 is a block diagram showing the configuration of the motion vector detection circuit.
- FIG. 11 is a block diagram illustrating a configuration example of a memory block.
- FIG. 12 is a diagram for explaining the configuration of the memory cell array.
- FIG. 13A and FIG. 13B are diagrams showing the configuration of unit A and unit B, respectively, which constitute the memory cell array.
- FIG. 14 is a diagram for explaining a specific example of the subtraction operation.
- Figure 15 shows the relationship between the total bit line charge and the output value (in the case of subtraction, there is absolute value conversion).
- Figure 16 is a diagram showing the relationship between the total bit line charge and the output value (in the case of subtraction, no absolute value conversion is performed).
- FIG. 17 is a diagram for explaining the generated absolute difference value.
- FIG. 18 is a diagram for explaining the difference calculation process.
- FIG. 19 is a diagram for explaining the difference calculation process.
- FIG. 20 is a block diagram illustrating a configuration example of a memory block.
- FIG. 21 is a diagram for explaining the configuration of the memory cell array.
- FIG. 22 is a diagram for explaining the configuration of the memory cell array.
- FIG. 23 is a diagram for explaining a specific example of the addition operation.
- FIG. 24 is a diagram showing the relationship (in the case of addition) between the total bit line charge and the output value.
- FIG. 25 is a flowchart showing a processing procedure of motion vector detection. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 5 shows a configuration of a motion-compensated prediction encoding apparatus 100 as an embodiment.
- This encoding device 10 ⁇ is supplied from an input terminal 101 for inputting an image signal Di, an image signal Di supplied to the input terminal 101, and a motion compensation circuit 110 described later.
- Subtractor 102 for calculating the difference from the predicted image signal to be calculated DCT circuit 103 for performing DCT (discrete cosine transform) on the difference signal obtained by the subtractor 102, and DCT circuit 1 0 Quantization circuit that performs quantization on DCT coefficients obtained in 3 1
- an output terminal 105 for outputting the coded signal Do obtained by the quantization circuit 104.
- the encoding device 100 includes an inverse quantization circuit 106 that performs inverse quantization on the encoded signal Do obtained by the quantization circuit 104, and an inverse quantization circuit 10 6, an inverse DCT circuit 107 that performs an inverse DCT on the output signal of 6 to obtain a difference signal, and a difference signal obtained by the inverse DCT circuit 107 and a prediction image signal obtained by the motion compensation circuit 110. And an image adder 108 for restoring the original image signal by adding the same, and a frame memory 109 for storing the image signal restored by the adder 108.
- the encoding device 100 reads the image signal stored in the frame memory 109 and converts the image signal into a motion vector MV from a motion vector detection circuit 111 described later.
- the motion compensation circuit 110 that supplies the predicted image signal to the subtractor 102 and the adder 108 as described above, and the image signal D input to the input terminal 101 a motion vector detection circuit 111 that detects the motion vector MV of i and supplies the motion vector MV to the motion compensation circuit 110.
- the image signal Di input to the input terminal 101 is supplied to the subtractor 102 and the motion vector detection circuit 111.
- the subtracter 102 calculates the difference between the image signal Di and the predicted image signal supplied from the motion compensation circuit 110.
- the difference signal obtained by the subtractor 102 is supplied to the DCT circuit 103 and subjected to discrete cosine conversion.
- the DCT coefficient obtained by the DCT circuit 103 is supplied to a quantization circuit 104 and quantized. Then, the encoded signal Do obtained by the quantization circuit 104 is output to the output terminal 105.
- the coded signal Do obtained by the quantization circuit 104 is supplied to the inverse quantization circuit 106 and inversely quantized, and the output signal of the inverse quantization circuit 106 is inversely transformed by DCT.
- the signal is supplied to the path 107 and subjected to inverse DCT to restore the difference signal.
- the difference signal and the predicted image signal from the motion compensation circuit 110 are added by the adder 108 to restore the original image signal, and the restored image signal is stored in the frame memory 109. Is done.
- the motion compensation circuit 110 in a certain frame, the image signal stored in the frame memory 109 is read in the previous frame, and the motion vector detection is performed.
- the motion is compensated based on the motion vector MV from the output circuit 111, and a predicted image signal is obtained.
- the predicted image signal is supplied to the subtractor 102 to obtain a difference signal, and is also supplied to the adder 108 to restore the image signal.
- the motion vector detection circuit 111 detects a motion vector by a block matching method. This involves moving the candidate block of the search frame within a predetermined search range and detecting the candidate block that best matches the reference block of the reference frame, as shown in Fig. 6, to determine the motion vector. Things.
- one image for example, an image of one frame of horizontal H pixels and vertical V lines is subdivided into blocks of P pixels XQ lines as shown in Fig. 7B. Is done.
- c is the center pixel position of the block.
- FIGS. 8A, 8B, and 8C show examples of the positional relationship between a reference block having c as a central pixel and a trap block having c-1 as a central pixel, respectively.
- the reference block whose center pixel is c is a certain reference block of interest in the reference frame, and a candidate block of a search frame that matches the reference block is located at a block centered on c ′ in the search frame.
- a motion vector is detected by finding a candidate block that best matches a reference block within a search range.
- FIG. 8A a motion vector of +1 pixel in the horizontal direction and +1 line in the vertical direction, that is, (+1, +1) is detected.
- FIG. 8B a (+3, +3) motion vector MV is detected, and in FIG. 8C, a (+2, 11) motion vector is detected.
- the motion vector is obtained for each reference block of the reference frame.
- the reference block sets the center c at ⁇ S horizontally and ⁇ T away from its center c. Needs to be compared to the candidate blocks that have.
- FIG. 9 is a diagram showing the center of a candidate block to be compared with a reference block when the search range is a small number of pixels in the horizontal direction and a ground line in the vertical direction.
- the position of the center c of the reference block with the reference frame is R, it may be necessary to compare with (2S + 1) X (2T + 1) candidate blocks of the search frame to be compared.
- 2S + 1) X (2T + 1) candidate blocks of the search frame to be compared.
- the motion vector is detected by detecting the minimum value in the sum of absolute differences obtained by the comparison within the search range.
- the search range in FIG. 9 is the region where the center of the candidate block is located.
- the size of the search range that includes the entire target block of size XQ pixels is (2S + P) X (2 T + Q).
- FIG. 10 shows the configuration of the motion vector detection circuit 111.
- the motion vector detection circuit 1 1 1 includes an input terminal 1 2 1 for inputting the image signal D i as a reference frame signal to the memory unit 1 2 2, an image signal D i of the reference frame and an image of the search frame. And a memory section 122 for storing signals.
- the memory unit 122 constitutes a difference absolute value generation unit.
- the memory unit 122 uses the image signals of the reference frame and the search frame to generate, for each pixel of the reference frame, an absolute difference between the pixel data and the pixel data at a plurality of search positions in the search frame. belongs to.
- the memory section 122 includes a reference frame memory section 122 for storing the image signal Di of the reference frame, a search frame memory section 122 for storing the image signal of the search frame, and a search frame memory section 122 for storing the image signal of the search frame. It has cache memories 122c and 122d.
- the cache memories 122c and 122d respectively store the data of the predetermined line when obtaining the absolute difference value using the storage data of the predetermined line of the frame memory 122a and 122b. Constitutes an evacuation unit for temporarily evacuation.
- the image signal D i of a certain frame is supplied from the input terminal 1 2 1 to the reference frame memory 1 2 2 a of the memory 1 2 2 and written therein, the image signal Di is stored in the reference frame memory 1 2 2 a.
- the image signal of the previous frame is read out, supplied to the search frame memory section 122b, and written.
- the 8-bit straight binary format pixel data read from the reference frame memory unit 122 a is converted to a two's complement conversion unit 123 provided outside the memory unit 122. Is converted to pixel data of the format, Is written to the search frame memory unit 122b.
- the reason why the data in the form of 2's complement is 9 bits is that when the data of 8 bits is “00000000”, the data in the form of 2's census becomes “100000000”. It is.
- the number-of-two conversion unit 123 may be provided inside the memory unit 122.
- FIG. 11 shows a configuration of the memory block 10 forming the reference frame memory unit 122a and the search frame memory unit 122b.
- the memory block 10 includes a memory cell array 20, a storage data input / output port 30, a row address decoder 40, a calculation data output port 50, and a control circuit 80.
- the memory cell array 20 includes a memory cell array section 20a corresponding to the reference frame memory section 122a and a memory cell array section 20b corresponding to the search frame memory section 122b.
- the memory cell array section 20a is connected to a bit line BL and a word line WL, and is composed of a plurality of memory cells ML arranged in a matrix.
- the bit line BL is a line extending in the row direction (row direction) for transferring data.
- the word line WL is a line extending in the column direction (column direction) and orthogonal to the plurality of bit lines BL.
- the memory cell array section 20b is composed of a plurality of memory cells ML connected to the bit line BL and the word line WL and arranged in a matrix form.
- the memory cell ML is not shown in FIG. 12, the memory cell ML constitutes units A and B as described later.
- the memory cell array section 20a, 2Ob includes a memory cell ML having, for example, a DRAM structure, and a plurality of memories connected to a plurality of activated word lines WL on one bit line BL. It is possible to combine the charges stored in the capacitor C of the cell ML.
- FIG. 13A shows the configuration of unit A.
- This unit A is connected to eight word lines WL and is composed of eight memory cells ML.
- the memory cell ML has a DRAM structure and includes an access transistor T and a capacitor C. One end of the capacitor C is grounded, and the other end is connected to the bit line BL via the access transistor T. The gate of the access transistor T is connected to the word line WL. Reading and writing to the memory cell ML are performed by activating the word line WL to turn on the access transistor T, as is conventionally known.
- Each of the eight memory cells ML of unit A stores each bit of one 8-bit data.
- the capacitor C of the eight memory cells ML has a capacity corresponding to the weight of each bit of the above-mentioned 8-bit data.
- the upper side is the LSB (Least Significant Bit) side
- the lower side is the MSB (Most Significant Bit) side.
- the capacitance of the capacitor C of the eight memory cells ML constituting the unit A is doubled sequentially from the LSB side to the MSB side. That is, assuming that the capacitance of the capacitor C of the LSB is p, the capacitance of the capacitor C of the eight memory cells ML is p, 2 P, 4 p, 8 p, 16 p, 32 p, 64 p, 128 p.
- FIG. 13B shows the configuration of unit B.
- This unit B is connected to nine word lines WL and is composed of nine memory cells ML.
- the memory cell ML has a DRAM structure and includes an access transistor T and a capacitor C. One end of the capacitor C is grounded, and the other end is connected to the bit line BL via the access transistor T. The gate of the access transistor T is connected to the word line WL. Reading and writing to the memory cell ML are performed by activating the word line WL to turn on the access transistor T, as is conventionally known.
- Each of the nine memory cells ML of unit B stores each bit of one 9-bit data.
- the capacitor C of the nine memory cells ML has a capacity corresponding to the weight of each bit of the above-mentioned 9-bit data.
- the upper side is the LSB side
- the lower side is the MSB side.
- the capacitance of the capacitor C of the nine memory cells ML constituting the unit B is sequentially doubled from the LSB side to the MSB side. That is, assuming that the capacity of the capacitor C of the LSB is p, the capacity of the capacitor C of the nine memory cells ML is p, 2 p, 4 p, 8 p, 16 p, 32, 64p, 128, 256p.
- the memory cell array unit 20a has at least W units A in the column direction and H units A in the row direction.
- the memory cell array unit 20b also has a structure in which at least W units B are arranged in the column direction and H units B are arranged in the row direction.
- the storage data input / output port 3 ⁇ includes a storage data column address decoder 31, an address buffer 32 and an I / O buffer 33.
- the column address decoder 31 includes an I / O gate (column switch), a sense amplifier, and the like. The column address is input to the column address decoder 31 via the address buffer 32.
- the column address decoder 31 secures the connection with the bit line BL connected to the predetermined memory cell ML in the column direction of the memory cell array 20 in accordance with the power address supplied via the address buffer 32. Through the O-buffer 33 and the column address decoder 31, it is possible to write and read stored data to and from a predetermined memory cell ML in the column direction.
- the row address is input to the row address decoder 40 via the address buffer 41.
- the row address decoder 40 activates a word line WL connected to a predetermined memory cell ML in the row direction of the memory cell array 20 in accordance with the row address supplied via the address buffer 41, and the IZO buffer 33 Through the column address decoder 31, it is possible to write and read stored data to and from a predetermined memory cell ML in the port direction.
- the operation data output port 50 includes an operation data output column address decoder 51, an address buffer 52, and an AZD converter 53.
- the column address decoder 51 includes a ⁇ / ⁇ gate (column switch), a sense amplifier, and the like.
- the column address is input to the column address decoder 51 via the address buffer 52.
- the column address decoder 51 constitutes bit line selection means.
- the column address decoder 51 and the AZD converter 53 constitute signal output means.
- the column address decoder 51 connects to one bit line BL connected to a predetermined memory cell ML in the column direction of the memory cell array 20 in accordance with the power address supplied through the address buffer 52. And outputs a voltage signal having a value corresponding to the total amount of charges obtained on the one bit line BL.
- the A / D converter 53 converts a voltage signal (analog signal) output from the column address decoder 51 into a predetermined bit, for example, an 8-bit digital signal and outputs the digital signal.
- control circuit 80 controls the operation of each circuit described above of the memory block 10 based on the control input.
- the memory block 10 can write and read stored data to and from a predetermined memory cell ML of the memory cell array 20 only at a portion other than the operation data output port 50.
- the column address is input to the column address decoder 31 via the address buffer 32.
- the column address decoder 31 secures the connection with the bit line BL connected to the predetermined memory cell ML in the column direction of the memory cell array 20 in accordance with the column address.
- the row address is input to the row address decoder 40 via the address buffer 41.
- the row address decoder 40 activates a word line WL connected to a predetermined memory cell ML in the row direction of the memory cell array 20 in accordance with the row address.
- the storage data is written to and read from a predetermined memory cell ML in the row direction.
- each bit of the 8-bit pixel data in the straight binary format is stored in each of the eight memory cells ML of each cut A in the memory cell array section 20a of the memory cell array 20.
- each of the nine memory cells ML of each unit B of the memory cell array section 20 b of the memory cell array 20 stores each bit of 9-bit pixel data in 2's complement format. You.
- the row address is input to the address decoder 40 via the address buffer 41.
- the row address decoder 40 corresponding to this row address, stores pixel data of one line of each of the memory cell array units 20a and 20b constituting the memory cell array 20, that is, a plurality of pixel data related to the unit of each row. Are activated at the same time. As a result, on each bit line BL, the charges accumulated in the capacitors C of the plurality of memory cells ML connected to the plurality of potential lines WL related to the two activated pixel data are coupled.
- the total bit line charge Qb is It looks like an expression. That is, the total bit line charge Qb is proportional to the total charge Qc stored in the capacitors C of the plurality of memory cells ML.
- the column address is input to the column address decoder 51 via the address buffer 52.
- the column address decoder 51 secures a connection with one bit line BL connected to a predetermined memory cell ML in the column direction of the memory cell array 20 corresponding to the column address.
- the column address decoder 51 outputs a voltage signal having a value corresponding to the total charge obtained on the bit line BL to which the connection has been secured. Therefore, from the A / D converter 53, a digital signal having a value corresponding to the total charge obtained on the bit line BL for which the connection is secured is obtained.
- each unit A of the memory cell array unit 20a stores the pixel data constituting the image signal Di of the reference frame in a straight binary format, and stores each unit of the memory cell array unit 20b.
- the pixel data constituting the image signal of the search frame is stored in the form of a 2 census. Therefore, the total amount of charges obtained on each bit line BL corresponds to the difference value between the pixel data of the reference frame and the pixel data of the search frame.
- the A / D converter 53 performs the absolute value conversion together with the conversion from the analog signal to the digital signal. Therefore, as described above, the digital signal obtained from the A / D converter 53 becomes a difference absolute value obtained by further converting the difference data obtained by subtracting the pixel data of the search frame from the pixel data of the reference frame into an absolute value. . '
- the absolute difference value corresponding to each bit line BL portion can be sequentially obtained from the A / D converter 53. That is, the absolute value of the difference of one line between the predetermined line of the reference frame and the predetermined line of the search frame is sequentially obtained.
- unit A 8-bit data as subtracted data is stored as it is in a straight binary format. This 8-bit data is "10000 0 0 1 0 1", and is "1 3 3" in the decimal notation.
- unit B stores 9-bit data obtained by converting 8-bit data as subtraction data into data in the form of a census of two. The 8-bit data is “0 0 0 1 0 1 0 0”, which is “2 0” in decimal notation. The 9-bit data after being converted to the 2's complement format is "0 1 1 1 0 1 1 0 0".
- the data of the minuend and the minuend are stored in the unit A and the unit B, respectively, so that only the capacitor C which is not notched out of the memory C of the unit A and the unit B stores the electric charge. It will be in the state that was done.
- the total amount of charge stored in all the capacitors C of the eight memory cells ML of the unit A is q, where the charge stored in the capacitor C of the memory cell ML of the LSB is q. And 1 3 3 q.
- the total amount of charges stored in all capacitors C of the nine memory cells ML of the unit B is 236 q.
- the column address decoder 51 outputs a voltage signal having a value corresponding to the total amount of charge “369”.
- "3 6 9" is "1 0 1 1 1 0 0 0 1” in binary notation.
- MSB is a sign bit, which indicates positive when “1” and negative when “0”. Therefore, the AZD converter 53 performs AZD conversion in consideration of the sign bit, and obtains the absolute value of the difference between the data stored in the two units A and B.
- FIG. 15 shows the relationship between the total bit line charge and the output value of the A / D converter 53.
- the bit line charge amounts from “1” to “2 5 5", “2 5 5" to “1”, and “2 5 6" to “5 1 1” correspond to "0" to "5". 2 5 5 ”digital signal is output.
- the total bit line charge on the horizontal axis in FIG. 15 is normalized so that q X Cb / (Cm + Cb) becomes 1. The same applies to the total bit line charge on the horizontal axis in Figs. 16 and 24 described later.
- the relationship between the total bit line charge and the output value of the AZD converter 53 is set as shown in FIG. 16, and the difference data is obtained from the A / D converter 53. It is also conceivable to convert to an absolute value by an absolute value conversion circuit. In this case, the A / D converter 53 outputs a digital signal of “1255j” to “255” corresponding to the total bit line charge “1” to “511”.
- the minuend data is 8-bit data, it can take a value in the range of "0" to "255" in decimal, but if the minuend data is also 8-bit data, it can be in decimal notation. Values can range from “0" to "2 5 5".
- the data of the minuend and the minuend are correctly stored in unit A and unit B, respectively. If the plurality of word lines WL related to the unit B are simultaneously activated, the total bit line charge is ⁇ 1 '' to ⁇ 5 1 1 '' in decimal notation, and may not be ⁇ 0 ''. impossible. Therefore, in FIGS. 15 and 16, conversion is performed even when the total bit line charge is “OJ”, but the converted digital value itself has no particular meaning.
- a plurality of read lines WL related to pixel data of one line of each of the memory cell array units 20a and 20b constituting the memory cell array 20 are simultaneously activated. This makes it possible to obtain the absolute value of the difference of one line between the predetermined line of the reference frame and the predetermined line of the search frame.
- the predetermined line of the reference frame and the vertical direction thereof are changed.
- the absolute value of the difference between the pixel data and the line of the search frame at a position shifted by a predetermined number of lines (in the row direction) can be obtained.
- a predetermined pixel of the reference frame can be moved horizontally. It is possible to obtain the absolute value of the difference between the pixel data and the pixel of the search frame at a position shifted by a predetermined number of pixels in the direction.
- the cache memories 122c and 122d described above are used. When used as storage memory.
- the memory unit 122 uses the image signals of the reference frame and the search frame, and, for each pixel of the reference frame, stores the pixel data and the pixel data of a plurality of search positions of the search frame. Generates the absolute value of the difference.
- the image size of one frame is WXH pixels.
- the search range sw is sw pixels in the horizontal direction (here, + xa to one xb) and sh pixels in the vertical direction (here, + ya to one yb).
- an absolute difference value between the pixel data and the pixel data of swXsh search positions of the search frame is generated.
- the difference absolute value a Is the pixel data between the pixel at (x, y) in the reference frame and the pixel at (x, y) in the mining frame.
- the absolute value of the difference is shown, and the absolute value of the difference a, y), (+ xa, + ya), ⁇ ( ⁇ , y), (— xb , + ya) , a (x, y), ( + X a , — yb), a (x, y), (— xb, one yb) f3 ⁇ 4, the face element at the (X, y) position of the reference frame and (x + xa, y + ya ), ( ⁇ - ⁇ b, y + ya), (x + x3 ⁇ 4, yyb), and the absolute value of the pixel data difference between the pixels at the positions (x-xb, yyb).
- the absolute value of the difference in the pixel data between the pixel at the position (x, y) in the reference frame and the pixel at the position (x + xa, y) to (: s-xb, y) in the search frame is As shown in FIG. 18, for example, the storage position of the pixel data at the position (x, y) of the search frame stored in the memory cell array section 20b is set to xa to + xb in the horizontal direction (column direction). You can get by just moving.
- the absolute value of the difference in pixel data between the pixel at the position (X, y) of the reference frame and the pixel at the position (X, y + ya) to (x, yyb) of the search frame Can be obtained by changing the position of the line activated in the memory cell array section 20b to y + ya to y-yb, as shown in FIG.
- the motion vector detection circuit 111 includes a difference absolute value holding unit 124 that holds the difference absolute value generated in the memory unit 122.
- the absolute value of this difference constitutes a difference absolute value sum generation unit.
- the difference absolute value holding unit 124 uses the difference absolute value generated in the memory unit 122 to store, for each reference block of the reference frame, the reference block and the search frame corresponding to the reference block within the search range.
- s wX Generates the sum of absolute differences between each of the sh candidate blocks.
- FIG. 20 shows a configuration of the memory block 60 constituting the absolute difference value holding unit 124.
- the memory block 60 includes a memory cell array 70, a storage data input / output port 30, a row address decoder 40, an operation data output port 50, and a control circuit 80.
- the memory block 60 has the same configuration as the memory block 10 (see FIG. 11) constituting the above-described reference frame memory section 122a and search frame memory section 122b except for the memory cell array 70. Therefore, here, the portion of the memory cell array 70 will be described in detail, and the description of the other portions will be omitted as appropriate.
- the memory cell array 70 is connected to a bit line BL and a lead line WL, and is composed of a plurality of memory cells ML arranged in a matrix.
- the memory cell ML is not shown in FIG. 21, the memory cell ML constitutes a unit A as described later.
- the memory cell ML has, for example, a DRAM structure, and a capacitor of a plurality of memory cells ML connected to a plurality of activated word lines WL on one bit line BL. Coupling of the accumulated charge of C is possible.
- T has a plurality of memory cells ML connected to each bit line BL divided into eight units A, and each unit A has one difference absolute value (straight binary). Format 8-bit data) is stored.
- Unit A is configured as shown in FIG. 13A, as described above.
- the memory cell array 70 has at least s wX sh pixels in the column direction.
- the structure is such that WXH units A are arranged in the row direction.
- an absolute difference value between the pixel data and the pixel data of swXsh search positions of the search frame is generated. Is done.
- the memory cell array 70 described above as shown in FIG.
- each unit A in the row direction corresponds to the position of WXH pixels in the reference frame, and the position of each unit A in the column direction Correspond to sw X sh search positions in the search frame.
- Each unit A of the memory cell array 70 holds a corresponding absolute difference value.
- the absolute value of the difference from the swXsh search position pixel data in the range of y + ya to y-yb in the vertical direction is held.
- This memory block 60 is capable of writing and reading stored data to and from a predetermined memory cell ML of the memory cell array 70 only at a portion other than the operation data output port 50.
- the column address is input to the column address decoder 31 via the address buffer 32.
- the column address decoder 31 secures a connection with the bit line BL connected to a predetermined memory cell ML in the column direction of the memory cell array 70 in accordance with the column address.
- the row address is input to the row address decoder 40 via the address buffer 41.
- the row address decoder 40 activates the word line WL connected to a predetermined memory cell ML in the row direction of the memory cell array 70 in accordance with the row address.
- writing and reading of storage data to and from predetermined memory cells ML in the column and row directions are performed.
- An address is input to the address decoder 40 via an address buffer 41.
- the row address decoder 40 responds to this row address by A plurality of word lines WL related to the unit A in the row direction corresponding to bw X bh pixel positions of a predetermined reference block of the memory cell array 70 are simultaneously activated (see FIG. 22).
- bw indicates the number of pixels in the reference block in the horizontal direction
- bh indicates the number of pixels in the reference block in the vertical direction.
- the column address is input to the column address decoder 51 via the address buffer 52.
- the column address decoder 51 secures a connection with one bit line BL connected to a predetermined memory cell ML in the column direction of the memory cell array 70 in accordance with the column address.
- the column address decoder 51 outputs a voltage signal having a value corresponding to the total charge obtained on the bit line BL to which the connection has been secured. Therefore, from the A / D converter 53, a digital signal having a value corresponding to the total charge obtained on the bit line BL whose connection is secured is obtained.
- the plurality of read lines WL related to the unit A in the row direction corresponding to the bwXbh pixel positions of the predetermined reference block in the memory cell array 70 are simultaneously activated. Therefore, the total amount of charge obtained on each bit line BL is bw X bh differences between a predetermined reference block and a predetermined candidate block within a search range of a search frame corresponding to the predetermined reference block. This corresponds to the result of adding the absolute value. Therefore, from the AZD converter 53, an absolute difference sum (digital signal) indicating the result of the addition is obtained.
- the A / D converter 53 searches for a predetermined reference block and a search frame corresponding to the predetermined reference block.
- the sum of absolute differences between each of the sw X sh candidate blocks in the range is sequentially obtained.
- a plurality of read lines WL related to the unit A in the mouth direction corresponding to bw X bh pixel positions to be activated in the memory cell array 70 shall correspond to other reference blocks.
- the sum of absolute differences of other reference blocks can be obtained.
- Unit A1 stores 8-bit data as augend data. This 8-bit data is “00010100”, which is “20” in decimal notation. On the other hand, unit A2 stores 8-bit data as addend data. This 8-bit data is “10000101”, which is “133” in decimal notation.
- the data of the augend and the addend are stored in each of the units A 1 and A 2, so that only the capacitor C which is not hatched among the memory cells ML of these units Al and A 2 has a charge. Is stored.
- the total amount of charge stored in all the capacitors C of the eight memory cells ML of the cut A1 is 20 q, where q is the charge stored in the capacitor C of the LSB memory cell ML. It becomes.
- the total amount of charges stored in all the capacitors C of the eight memory cells ML of the unit A2 is 133 q.
- the column address decoder 51 outputs a voltage signal having a value corresponding to the total charge “153”.
- the A / D converter 53 obtains addition data corresponding to the addition result of the data stored in the units A 1 and A 2.
- FIG. 24 shows an example of the relationship between the total bit line charge and the output value (addition data) of the AZD converter 53 having an 8-bit output. In the case of FIG. 24, such a conversion characteristic causes Can be converted to 256 gradations.
- FIG. 24 shows an example of the relationship between the total bit line charge and the output value (addition data) of the AZD converter 53 having an 8-bit output. In the case of FIG. 24, such a conversion characteristic causes Can be converted to 256 gradations.
- the motion vector detection circuit 111 also stores a plurality of difference absolute value sums generated by the difference absolute value holding unit 124 for each reference block. It has a sum holder 125.
- the motion vector detection circuit 111 detects a motion vector for each reference block based on a plurality of difference absolute value sums for each reference block held in the difference absolute value sum holding unit 125.
- the minimum value judging unit 1 26, the motion vector holding unit 127 holding the motion vector detected by the minimum value judging unit 126, and the motion vector holding unit 127 It has an output terminal 128 for sequentially outputting the motion vector MV of each reference block.
- the minimum value determining unit 126 detects the position of the candidate block that generates the minimum sum of absolute differences as a motion vector.
- the image signal Di input to the input terminal 122 is stored as a reference frame image signal in the reference frame memory 122 a constituting the memory 122.
- the image signal of the previous frame stored in the reference frame memory unit 122 b is read out and stored in the search frame memory unit 122 as the image signal of the search frame.
- the 8-bit straight binary format pixel data read from the reference frame memory unit 122a is converted to a two's complement number by the two's complement conversion unit 123 provided outside the memory unit 122.
- the reference frame memory section 122a and the search frame memory section 122b are composed of memory blocks 10 (see FIG. 11). And the memory cell array
- Reference numeral 20 denotes a memory cell array section 20a corresponding to the reference frame memory section 122a and a memory cell array section 20b corresponding to the search frame memory section 122b (see FIG. 12).
- the p memory cell array sections 20a and 2Ob are formed continuously in the row direction (row direction) in which the bit line B extends.
- the plurality of read lines WL related to the pixel data of one line of each of the memory cell array units 20a and 20b are simultaneously activated, so that each of the activated read lines 2 is activated on each bit line BL.
- the charges stored in the capacitors C of the plurality of memory cells ML connected to the plurality of read lines WL related to one pixel data are combined.
- the column address decoder 51 secures a connection with one bit line BL connected to a predetermined memory cell ML in the column direction of the memory cell array 20, and the total amount of electric charge obtained on the secured bit line BL. And outputs a voltage signal having a value corresponding to. Then, from the AZD converter 53, a digital signal having a value corresponding to the total charge amount is obtained. .
- This digital signal is stored in each unit A of the memory cell array section 20a in the form of a straight binary in the form of pixel data constituting the image signal Di of the reference frame.
- the pixel data constituting the image signal of the search frame is stored in the form of a two's complement, and the converter 70 converts the analog signal into a digital signal.
- the difference data obtained by subtracting the pixel data of the search frame from the pixel data of the reference frame is further converted into the absolute value of the difference.
- the absolute difference value corresponding to each bit line BL portion can be sequentially obtained from the AZD converter 53. That is, the difference absolute value of one line between the predetermined line of the reference frame and the predetermined line of the search frame is sequentially obtained.
- the memory cell array section 20a is activated by the memory cell
- the position of the line activated in the array section 20b is changed, and the position between the predetermined line of the reference frame and the line of the search frame at a position shifted by a predetermined number of lines in the vertical direction (row direction) from this line is changed.
- An absolute difference value of the pixel data is obtained.
- the storage position of the pixel data stored in the memory cell array unit 20a or the memory cell array unit 20b is moved in the horizontal direction (column direction), and the predetermined number of pixels in the reference frame and the predetermined number of pixels in the horizontal direction are shifted.
- the absolute value of the difference between the pixel data and the pixel of the search frame at the shifted position is obtained.
- a difference absolute value between the pixel data and the pixel data at a plurality of search positions in the search frame is generated.
- the image size of one frame is WXH pixels
- the search range is sw pixels (+ xa to 1xb) in the horizontal direction and sh pixels (+ yayb) in the vertical direction
- the reference frame For each pixel of the WXH pixel, an absolute difference between the pixel data and the pixel data of the search frame at s wX sh search positions is generated (FIG. 17 corresponds to the activated word line WL).
- the pixel data for one line stored in the memory cells ML of the plurality of memory cell array sections 20a and 20b are stored in the cache memories 122c and 122d before the activation of the word line WL (see FIG. Then, as described above, after the absolute value of the difference for one line is obtained from the AZD converter 53, the data stored in the cache memories 122c and 122d are used as described above. The meaningless storage data of the plurality of memory cells ML is restored.
- the absolute difference value generated in the memory 122 is supplied to and held in the absolute difference holding unit 124.
- the absolute difference holding unit 124 is configured by the memory block 60 (see FIG. 20).
- the image size of one frame is WXH pixels and the search range is sw pixels in the horizontal direction and sh pixels in the vertical direction, at least swX sh pixels in the column direction.
- the structure is such that W XH units A are arranged in the row direction (see FIG. 21).
- each unit A ′ in the row direction corresponds to the position of WXH pixels in the reference frame, and the position of each unit A in the column direction is Added support for s wX sh search positions in search frame It is assumed.
- Each unit A of the memory cell array 20 holds a corresponding absolute difference value (see FIG. 17).
- Each of the plurality of bit lines WL associated with the row-direction Uet A corresponding to the bw X bh pixel positions of the predetermined reference block of the memory cell array 70 is simultaneously activated, so that each bit line BL Above, the accumulated charges of the capacitors C of the plurality of memory cells ML connected to the plurality of lead lines WL of the activated bw X bh units A are respectively coupled.
- the column address is input to the column address decoder 51 via the address buffer 52.
- the column address decoder 51 secures a connection with one bit line BL connected to a predetermined memory cell ML in the column direction of the memory cell array 70 in accordance with the column address.
- the column address decoder 51 outputs a voltage signal having a value corresponding to the total charge obtained on the bit line BL to which the connection has been secured. Therefore, from the AZD converter 53, a digital signal having a value corresponding to the total charge obtained on the bit line BL whose connection is secured is obtained.
- This digital signal is obtained by calculating the total amount of charge obtained on each bit line BL between a predetermined reference block and a predetermined candidate block within a search range of a search frame corresponding to the predetermined reference block by bw X bh Since the result corresponds to the result of adding the absolute value of the difference, the absolute difference ⁇ direct sum indicating the result of the addition is obtained.
- the A / D converter 53 searches for a predetermined reference block and a search frame corresponding to the predetermined reference block.
- the sum of absolute differences between each of the sw X sh candidate blocks in the range is sequentially obtained.
- the plurality of read lines WL related to the unit A in the row direction corresponding to bw X bh pixel positions to be activated in the memory cell array 70 to correspond to other reference blocks, Is obtained.
- the absolute difference value sum storage unit 124 outputs, for each reference block of the reference frame, the reference block and each of the sw X sh candidate blocks within the search range of the search frame corresponding to this reference block. Is generated.
- the plurality of difference absolute value sums for each reference block are supplied to and held by the difference absolute value sum holding unit 125.
- the minimum value determining unit 126 determines, for each reference block, the candidate block that generates the minimum sum of absolute differences based on the plurality of sums of absolute differences stored in the sum of absolute difference values 125 in this way.
- the position is detected as a motion vector.
- the motion vector detected in this way is held in the motion vector holding unit 127.
- the motion vector MV output in this way is supplied to the above-described motion compensation circuit 110 (see FIG. 5) and used for motion compensation processing.
- the flowchart of FIG. 25 shows the procedure of the detection processing of the motion vector MV in the motion vector detection circuit 111 described above.
- step ST1 the process is started, and in step ST2, the image signal Di stored in the reference frame memory unit 122a of the memory unit 122 is read out, and the two's complement conversion unit 123 outputs a straight binary format.
- the data is converted into two's complement format data, and then written into the search frame memory section 122b of the memory section 122 as a search frame image signal.
- step ST3 the image signal Di of the reference frame is input from the input terminal 121, and the image signal is written to the reference frame memory 122a of the memory unit 122.
- step ST4 in order to simultaneously activate a plurality of read lines WL related to the pixel data of one line of each of the memory cell array units 20a and 20b corresponding to the frame memory units 122a and 122b, Each line of pixel data (reference line data and search line data) is read from the memory cell array units 20a and 20b and saved in the cache memories 122c and 122d.
- step ST5 a plurality of read lines WL relating to the pixel data of one line of each of the memory cell array units 20a and 20b are simultaneously activated, and the reference line data and the search line data) are simultaneously read out.
- the difference absolute value for the line is obtained and held in the difference absolute value holding unit 124.
- step ST6 the reference line data saved in the cache memory 122c is written to the reference frame memory unit 122a.
- step ST7 the search line data saved in the cache memory 122d is moved in the horizontal direction (column direction) to the storage position, and is written back to the search frame memory unit 122b.
- step ST8 it is determined whether or not the process of obtaining the absolute value of the difference between the target reference line data and all the search line data corresponding to the search range has been completed. For one reference line data, it is necessary to finally generate an absolute difference value for swX sh lines (see Fig. 17). If the processing has not been completed, the process returns to step ST4 and shifts to processing for obtaining the absolute value of the difference between the target reference line data and the next search line data.
- step ST8 it is determined whether or not the processing for obtaining the absolute difference values of all the reference line data has been completed. If not completed, the process returns to step ST4 and shifts to the process of obtaining the absolute difference value of the next reference line data.
- step ST10 the difference absolute value holding unit 124 calculates the sum of the difference absolute values between the reference block and each of the catch blocks in the search range for the target reference block. These are sequentially obtained and stored in the difference absolute value sum storage unit 125.
- step ST11 based on the plurality of sums of the difference absolute values of the reference block of interest held in the sum of absolute difference values holding unit 125, the detection block that generates the minimum sum of the difference absolute values is determined. The position is detected as a motion vector. Then, in step ST12, the detected motion vector is held in the motion vector holding unit 127.
- step ST13 it is determined whether or not the above-described motion vector detection processing has been completed for all reference blocks of the reference frame. If not, the process returns to step ST10 to proceed to the process of detecting a motion vector corresponding to the next reference block. On the other hand, when the processing ends, in step ST14, the motion vectors MV corresponding to the respective reference blocks held in the motion vector holding unit 127 are sequentially output, and the process ends in step ST15.
- each image of the reference frame is stored in the memory unit 122.
- the memory unit 122 stores pixel data of the reference frame in a unitary binary format in a unit A including a plurality of memory cells ML arranged in the direction in which the bit line BL extends, and stores pixel data of the search frame in the bit line BL.
- a unit B consisting of a plurality of memory cells ML arranged in the direction of extension
- the data is stored in the form of two's complement, and the word lines WL related to the pixel data of the reference frame and the search frame are simultaneously activated.
- the stored charges of the capacitors C of the plurality of memory cells ML connected to the line WL are combined on one bit line BL, and a digital signal having a value corresponding to the total charge is obtained as a difference absolute value.
- the process of obtaining the absolute value of the difference between the pixel data of the reference frame and the search frame is performed simultaneously with the reading of the pixel data, and the absolute value of the difference can be obtained at high speed.
- a subtractor and an absolute value circuit are not separately required, and can be configured at a low cost.
- the difference absolute value holding unit 124 stores, for each reference block of the reference frame, a plurality of candidates in the search range of the reference frame and the search frame corresponding to the reference block. Generate the sum of absolute differences between each of the blocks.
- the difference absolute value holding unit 124 stores a difference absolute value in each of the units A including a plurality of memory cells ML arranged in the direction in which the bit line BL extends, and stores a code line related to a plurality of difference absolute values.
- Activate WL at the same time combine the charges stored in the capacitors C of the memory cells ML connected to the plurality of read lines WL on one bit line BL, and subtract the digital signal of the value corresponding to the total charge. It is obtained as the sum of absolute values. Therefore, the addition of a plurality of difference absolute values is performed simultaneously with the reading of the difference absolute values, and the sum of the difference absolute values can be obtained at high speed. Further, an adder is not separately required, and can be configured at a low cost.
- the AZD converter 53 can perform gradation conversion, if the A / D converter 53 can change the number of bits of the output digital signal, a dedicated circuit is used. It is possible to easily perform the gradation operation without providing an image.
- each pixel of the reference frame is stored in the memory unit 122.
- a difference absolute value between the pixel data and the pixel data at a plurality of search positions in the search frame is generated.
- the difference absolute value holding unit 124 uses the generated difference absolute value to generate a reference frame. For each reference block of, a sum of absolute differences between this reference block and each of a plurality of candidate blocks within the search range of the search frame corresponding to this reference block is generated, and each of the reference frames is generated. A motion vector corresponding to the reference block is detected based on a plurality of generated sums of absolute differences for each reference block, so that a motion vector can be detected at high speed and at low cost. Become like
- the memory cells ML of the memory cell arrays 20 and 70 have a DRAM structure.
- the present invention is not limited to this. In short, it is only necessary that the charge accumulated in the capacitors of the plurality of memory cells connected to the plurality of activated word lines be combined on one bit line.
- the first frame is a reference frame and the second frame is a search frame, which is applied to motion vector detection.
- the present invention is not limited to this. Not something.
- the unit A or unit B that stores one data is configured by eight or nine memory cells ML.
- the unit A or unit B is configured.
- the number of memory cells ML is not limited to this.
- the capacity of the capacitor C of the memory cell ML storing the data of each bit is set to a size corresponding to the weight of the bit, so that the unit A storing the data of 8 bits is provided. It can be configured with only eight memory cells ML. However, if the capacitance of the capacitor C of the memory cell ML is all the same, it is necessary to allow the accumulation of charge amount of 2 5 6 gradations, 2 8 - 1 Memorise Le ML du -Can configure A. The same is true for unit B.
- the unit A storing 8-bit data may be configured with fewer memory cells ML instead of the eight memory cells ML.
- unit A can be composed of four memory cells ML.
- the first memory cell ML stores “01” from the LSB side, that is, the charge corresponding to the charge amount corresponding to “1” in decimal
- the memory cell ML of the first cell stores ⁇ 0100 '', that is, the amount of charge corresponding to the decimal number ⁇ 4 ''
- the third memory cell ML stores ⁇ 00 0000 '', that is, the decimal number ⁇ 0 ''
- the fourth memory cell ML may store a charge of "10000000", that is, a charge corresponding to "128" in decimal.
- the capacitance of the capacitor C of the four memory cells ML is p
- the capacitance of the capacitor C of the first memory cell ML is p
- the second is 4 p
- the third is 16 p
- the fourth is It should be 64 p.
- the capacitor C of the memory cell ML that stores the digit of 1 stores the charge of the charge amount corresponding to ⁇ 5 '' and stores the digit of 10
- the capacitor C of the memory cell ML that stores the electric charge corresponding to “3 ⁇ 10” is stored in the capacitor C. Is stored.
- the capacitor C of the memory cell ML corresponding to each digit must have a capacity capable of storing the maximum accumulated charge amount of each digit.
- addition and subtraction are described as examples of operations.
- multiplication and division can be performed.
- M is copied into N units, and then the above-described addition operation is performed on the N units.
- a plurality of word lines are simultaneously activated, and charges accumulated in capacitors of a plurality of memory cells connected to the plurality of word lines are coupled on one bit line, and the total amount of the charges is reduced. It is designed to output a digital signal of the corresponding value, enabling simultaneous processing of data reading and calculation, improving calculation speed, T JP2003 / 013204
- Costs can be reduced by reducing the number of arithmetic units.
- the memory device stores the pixel data of the first frame in a straight binary format in a unit consisting of a plurality of memory cells arranged in the direction in which the bit line extends, and stores the pixel data of the second frame.
- Data is stored in a unit consisting of a plurality of memory cells arranged in the direction in which the bit lines extend in the form of a 2's number, and the code lines relating to the pixel data of the first and second frames are simultaneously activated.
- the charge stored in the capacitors of the plurality of memory cells connected to the plurality of read lines is combined on one bit line, and a digital signal having a value corresponding to the total amount of the charges is output.
- the difference data of the pixel data of the frame can be obtained at high speed and at low cost.
- data is stored in each of units formed of a plurality of memory cells arranged in the direction in which the bit lines extend, and the read lines associated with the plurality of data are simultaneously activated.
- ⁇ Combines the charges stored in the capacitors of multiple memory cells connected to a single line on a single bit line and outputs a digital signal with a value corresponding to the total charge. Can be obtained at high speed and at low cost.
- the motion vector detecting device and the detecting method according to the present invention generate, for each pixel of the reference frame, an absolute difference value between the pixel data and the pixel data at a plurality of search positions of the search frame. For each reference block of the reference frame, the difference absolute value between the reference block and each of a plurality of candidate blocks within the search range of the search frame corresponding to the reference block using the obtained difference absolute value. A sum is generated, and for each reference block of the reference frame, a motion vector corresponding to the reference block is detected based on a plurality of sums of the generated absolute difference values. It can be performed at low cost. Industrial applicability
- the memory device, the motion vector detection device, and the detection method according to the present invention can be applied to, for example, the use of detecting a motion vector by a motion compensation prediction encoding device.
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Abstract
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Priority Applications (4)
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CN2003801015682A CN1706001B (zh) | 2002-10-15 | 2003-10-15 | 存储器器件和检测运动向量的设备和方法 |
US10/531,005 US7626847B2 (en) | 2002-10-15 | 2003-10-15 | Memory device, motion vector detection device, and detection method |
EP03756622A EP1557840B1 (en) | 2002-10-15 | 2003-10-15 | Memory device, motion vector detection device, and detection method |
US12/559,212 US8073058B2 (en) | 2002-10-15 | 2009-09-14 | Memory device and device and method for detecting motion vector |
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- 2003-10-15 US US10/531,005 patent/US7626847B2/en not_active Expired - Fee Related
- 2003-10-15 KR KR1020057006476A patent/KR100966129B1/ko not_active IP Right Cessation
- 2003-10-15 TW TW092128571A patent/TWI240278B/zh not_active IP Right Cessation
- 2003-10-15 EP EP03756622A patent/EP1557840B1/en not_active Expired - Fee Related
- 2003-10-15 WO PCT/JP2003/013204 patent/WO2004040581A1/ja active Application Filing
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2009
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Also Published As
Publication number | Publication date |
---|---|
TW200506944A (en) | 2005-02-16 |
EP1557840A4 (en) | 2010-04-07 |
EP1557840A1 (en) | 2005-07-27 |
US7626847B2 (en) | 2009-12-01 |
US20060062483A1 (en) | 2006-03-23 |
KR100966129B1 (ko) | 2010-06-25 |
KR20050084851A (ko) | 2005-08-29 |
TWI240278B (en) | 2005-09-21 |
US20100002774A1 (en) | 2010-01-07 |
EP1557840B1 (en) | 2012-12-05 |
US8073058B2 (en) | 2011-12-06 |
CN1706001A (zh) | 2005-12-07 |
CN1706001B (zh) | 2012-03-21 |
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