WO2004036636A1

WO2004036636A1 - A film stack having a silicon germanium layer and a thin amorphous seed layer

Info

Publication number: WO2004036636A1
Application number: PCT/US2003/032966
Authority: WO
Inventors: Shulin Wang; Li Fu; Xianzhi Tao; Kevin L. Cunningham; Lee Luo; Aihua Chen; Paul L. Meissner
Original assignee: Applied Materials, Inc.
Priority date: 2002-10-18
Filing date: 2003-10-16
Publication date: 2004-04-29
Also published as: AU2003284272A1

Abstract

A semiconductor device and methods of forming the same is described. The semiconductor device comprises a semiconductor substrate having a first conducting type. A gate dielectric layer (104) formed over the semiconductor substrate. A gate electrode formed directly on the gate dielectric. The gate electrode includes an amorphous silicon layer (106), a silicon germanium layer (108), and an amorphous silicon cap layer (110), wherein the amorphous silicon layer is less than 10 Å thick and is deposited directly over the gate dielectric, wherein the silicon-germanium layer is deposited directly over the amorphous silicon layer. The silicon germanium layer has about 5 % to 50 % atomic count of germanium.

Description

A FILM STACK HAVING A SILICON GERMANIUM LAYER AND A THIN AMORPHOUS SEED LAYER

BACKGROUND OF THE INVENTION

1). Field of the Invention

[0001] The invention relates generally to a film stack having a silicon germanium layer and a thin amoφhous seed layer that can be used to form a gate electrode of a semiconductor device.

2). Discussion of Related Art

[0002] Integrated circuits are usually manufactured in and on silicon and other semiconductor wafers or substrates. An integrated circuit of this kind may have literally millions of interconnected metal-oxide-semiconductor (MOS) transistors. Such a transistor typically has a gate dielectric layer that is formed on the semiconductor material of the substrate, and a gate electrode on the gate dielectric layer. The gate electrode is usually made of silicon or another semiconductor material. The gate electrode is further doped with a dopant such as boron, phosphorus, or arsenic. The substrate is subsequently heated to activate the dopant and make the gate electrode conductive. [0003] For better transistor functioning, it is required that the gate dielectric layer be as thin as possible. Thinner gate dielectric layers have more capacitance than thicker gate dielectric layers. If the region of the gate electrode near the gate dielectric layer has few electric current carriers, the effective capacitance of the gate dielectric layer combined with the gate electrode is lower. The depletion of electric current carriers in the gate electrode near the gate dielectric layer is known as "poly depletion" or "carrier depletion" or "polysilicon-gate depletion." This depletion of electric current carriers in the gate electrode near the gate dielectric layer is discussed in the book entitled Fundamentals of Modern VLSI Devices by Yuan Taur and Tak H. Ning, Cambridge University Press, 1998, ISBN 0-521-55959-6, specifically discussed in Section 2.3.4.2. [0004] International patent application number PCT/US00/31676 discloses the fabrication of a gate electrode of a transistor, wherein the gate electrode includes silicon germanium. Silicon germanium is desirable because it has a material characteristic, which increases the number of electric current carriers in the material. The material characteristic is known as the "Band Gap," which is smaller for silicon germanium than it is for polysilicon.

[0005] Silicon germanium may not be deposited uniformly on an insulation or a dielectric layer (e.g., a silicon dioxide layer) typically formed on a silicon substrate. Silicon germanium layer deposited directly on an insulation layer tends to have an undesirable segregation. As such, a seed layer is often desired. Current technology enables formation of a polysilicon seed layer (e.g., PCT/US00/31676) on a silicon dioxide layer. The polysilicon seed layer tends to be thicker than necessary and thus increases the thickness of the gate electrode more than desirable. The polysilicon seed layer also increases the effective width of the gate dielectric layer. As semiconductor devices are getting smaller, active layers in these devices need to be thin; a thin polysilicon seed layer may not completely and continually cover the surface of the structures beneath the thin polysilicon seed layer.

SUMMARY OF THE INVENTION

[0006] According to an aspect of the invention, a silicon germanium layer is deposited directly on an ultra-thin amoφhous seed layer, which is deposited directly on an insulation layer formed over a semiconductor substrate. The ultra-thin amoφhous seed layer is an amoφhous silicon layer having a thickness less than 10 A.

[0007] In one embodiment, a semiconductor substrate is provided. An insulation layer such as a gate dielectric layer is formed on the substrate. An amoφhous silicon layer having a thickness less than lOA is formed directly on the insulation layer. A silicon- containing gas Si_xH_2x+2 wherein x is at least 2 is used to form the amoφhous silicon layer. The amoφhous silicon layer is formed at a temperature between 560°C and 590°C and a pressure between 100 Torr and 400 Torr. A silicon germanium layer is formed directly on the amoφhous silicon layer using the silicon-containing gas and a germanium containing gas. The silicon germanium layer is formed at the same temperature and pressure as those used to form the amoφhous silicon layer (560°C to 590°C and 100 Torr to 400 Torr, respectively). Optionally, an amoφhous silicon cap layer is formed on the silicon germanium layer. The amoφhous silicon cap layer is formed using the silicon-containing gas and the same temperature and pressure ranges as those used to form the amoφhous silicon layer and the silicon germanium layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The invention is further described by way of examples with reference to the accompanying drawings, wherein:

[0009] Figure 1 illustrates an exemplary method of fabricating an electronic device having the amoφhous silicon seed layer, the silicon germanium layer, and the amoφhous cap layer on a semiconductor substrate;

[0010] Figure 2 illustrates a cross-sectional side view of an exemplary semiconductor processing system that is used for carrying out the process according to the invention;

[0011] Figure 3 illustrates an enlarged view of an exemplary chamber and internal components of the chamber;

[0012] Figures 4A to 4H illustrate cross-sectional side views an exemplary process of forming an electronic device that includes a gate electrode having a silicon germanium layer formed on an ultra-thin amoφhous silicon seed layer;

[0013] Figure 5 illustrates a temperature range within which an amoφhous silicon layer can be formed and within which a polycrystalline silicon germanium layer can be formed; and

[0014] Figure 6 illustrates cluster tool that can be used for some of the embodiments of the present invention.

DF.T An F.D DESCRIPTION OF THE INVENTION

[0015] The present invention relates to a film stack that includes a silicon germanium layer, an ultra-thin amoφhous seed layer, and a dielectric layer, which is formed over a semiconductor substrate. In the following description, for puφoses of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, specific apparatus structures and methods have not been described so as not to obscure the present invention. The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention.

[0016] Figure 1 illustrates one exemplary method 300 of forming a film stack that includes a dielectric layer, an amoφhous silicon layer, a silicon germanium layer and an amoφhous silicon cap layer. The amoφhous silicon layer acts as a seed layer for the silicon germanium layer. First, at operation 302, a substrate is provided. In one embodiment, the substrate is made out of monocrystalline silicon. The substrate may be made out of other silicon-containing substrate such as a silicon-on-insulator (SOI) substrate. The substrate may also have a different form of crystalline structure such as an amoφhous and a polycrystalline structure. In one embodiment, an insulation (or dielectric) layer such as a gate dielectric is formed on the substrate using conventional method. Next, at operation 304, an amoφhous silicon layer is formed on the substrate. In an embodiment where an insulation layer is formed on the substrate, the amoφhous silicon layer is formed directly on the insulation layer. Next, at operation 306, a silicon germanium layer is formed on the amoφhous silicon layer. In one embodiment, an amoφhous silicon cap layer is formed on the silicon germanium layer as illustrated at operation 308.

[0017] In one embodiment, the method 300 is carried out in a semiconductor processing system 10 that is illustrated in Figure 2. The system 10 includes a low-pressure chemical vapor deposition chamber 12, a gas supply apparatus 14, a susceptor 16, and a susceptor elevating apparatus 18.

[0018] In one embodiment, the chamber 12 is a single-wafer deposition chamber. The chamber 12 is also a resistively heated single wafer deposition chamber. In another embodiment, a current is provided to a resistive heater 76 located within the susceptor 16. The susceptor 16 can be made out of ceramic, graphite, aluminum, or other suitable material, preferably, ceramic. The current heats the resistive heater 76, and the heat conducts from the resistive heater 76 through the susceptor 16 to heat a substrate 79 supported by the susceptor 16. In one exemplary embodiment, a thermocouple 78 is located within the susceptor 16, and provides temperature feedback for puφoses of controlling the temperature of the susceptor 16 and, indirectly, the temperature of the substrate 79. The temperature of the substrate 79 is approximately 20°C lower than the temperature measured at the susceptor 16. [0019] In another embodiment, the chamber 12 can also be a cold-wall chamber in which a coolant fluid is supplied to a container (not shown) surrounding the wall of the chamber 12 to prevent the chamber 12 from getting too hot. With the reactant gases and the high temperature process occurring in the chamber 12, the chamber 12 may be easily corroded unless made out of a corrosion resistant material, which is often expensive. With the cold- wall feature, the chamber 12 does not need to be made out of such an expensive material that is corrosion resistant. The chamber 12 can be made out of an aluminum alloy or other suitable metal.

[0020] The chamber 12 includes a lower body 20 and a lid 22. The lid 22 seals peripherally with an upper extremity of the body 20. The body 20 and the lid 22 jointly define an inner volume 24 of approximately five to seven liters. In one embodiment, the chamber 12 includes a reacting space 47. The reacting space 47 is the area between the dispersion plate 38 and the susceptor 16. In one embodiment, the reacting space 47 is the area where process gases react together and form a particular film (e.g., an amoφhous silicon layer, a silicon germanium layer, and an amoφhous silicon cap layer). In one embodiment, the reacting space 47 has a volume of about 750 cm³, which is the dispersion plate area times the distance between the dispersion plate 38 and the susceptor 16. [0021] In one embodiment, a first gas inlet port 26 is formed through a center of the lid 22. A second gas inlet port 28 is formed into a base of the susceptor elevating apparatus 18 and leading directly into the bottom side of the chamber 12. A gas outlet port 30 is formed in a side of the body 20. The body 20 also has a slit valve opening 32 in one side thereof, and a susceptor elevating apparatus opening 34 in a base thereof. [0022] In one embodiment, a gas dispersion plate 38 or "shower head" is mounted below the lid 22. Surfaces of the lid 22 and the gas dispersion plate 38 jointly define a thin horizontal cavity 40. The gas dispersion plate 38 has a multitude of openings (not shown) formed therethrough that place the cavity 40 in communication with the inner volume 24. [0023] In one embodiment, a gas accumulation ring (or "pumping plate") 42 is mounted within the chamber 12. The gas accumulation ring 42 and the surfaces of the chamber 12, define a ring volume 44. Gas outlet openings 46 are formed as an open gate between the pumping plate 42 and the dispersion plate 38. The ring volume 44 is in communication with the gas outlet port 30. [0024] A process gas or gases can flow through the first gas inlet port 26 into the cavity 40. In one embodiment, the process gas or gases flow radially within the cavity 40. The process gas or gases can flow through the openings in the gas dispersion plate 38 into the inner volume 24. More gas or gases can enter through the second gas inlet port 28 into the inner volume 24. Typically, only a purging gas or an inert gas such as nitrogen (N₂) gas is introduced to the inlet port 28. The process gases that are used to form films on a substrate are introduced through the inlet port 26. Introducing the inert gas through the inlet port 28 during a film deposition process prevents undesirable deposition on the bottom side of the chamber 12. In one embodiment, the gas or gases can exit the inner volume 24 through the gas outlet openings 46, be accumulated in the ring volume 44, and subsequently be pumped out through the gas outlet port 30.

[0025] Referring to Figure 2, the gas supply apparatus 14 of the system 10 includes a gas bank 60 and a gas-mixing manifold 62. The gas-mixing manifold 62 is connected to the first gas inlet port 26. In one embodiment, the gas bank 60 includes a number of different gas sources. In one embodiment, the gas sources includes a nitrogen (N₂) gas, a silicon-containing gas Si_xH_2x+2 where x is at least 2 (e.g., disilane (Si₂H₆))- and a germanium-containing gas (e.g., germaine (GetL ). In another embodiment, the gas sources include an oxidation source gas, (e.g., nitrous oxide (NO₂)), a carrier/dilution gas (e.g., helium (He), hydrogen (H₂), and argon (Ar)).

[0026] In one embodiment, each of the gas sources is connected to the gas-mixing manifold 62 through a respective valve (not shown). In one embodiment, the N₂ source gas is also connected to the second gas inlet port 28 through a valve (not shown). [0027] In one embodiment, the gas supply apparatus 14 couples to a processor/controller 64, which is further coupled to a memory 66. The memory 66 includes a program or a set of instructions that is read by the processor/controller 64. When the processor/controller 64 executes the program, the processor/controller 64 can operate and control each of the gas sources independently. In one embodiment, the processor/controller 64 can control and operate the gas-mixing manifold 62.

[0028] In another embodiment, the processor/controller 64 controls all activity of the system 10, for example, the processes for forming or depositing various layers (e.g., an amoφhous silicon layer, a silicon germanium layer, and an amoφhous silicon cap layer) in accordance with the present invention. [0029] In another embodiment, the program further includes sets of instructions that dictate the timing, the mixture of gases, the chamber pressure, the heater temperature, the power supply, the susceptor position, and other parameters of the deposition processes in accordance with the present invention. The program may also include instructions for controlling process parameters such as process gas flow rates, process gas, compositions, temperatures, and pressures that are used to form various layers according to the present invention.

[0030] In one embodiment, the instructions provide for obtaining a process temperature from 560°C to 590°C, for obtaining a process pressure from 100 Torr to 400 Torr, and for controlling flow rates of the process gas mixtures. In one embodiment, the instructions provide for controlling the gas supply apparatus 14 to introduce a process gas mixtures comprising a silicon-containing gas and a germanium-containing gas. In another embodiment, the instructions provide for introducing the silicon containing gas to form an amoφhous silicon layer, introducing the silicon-containing gas simultaneously with the germanium-containing gas to form a silicon germanium layer, and cutting off the germanium-containing gas while continuing introducing the silicon-containing gas to form an amoφhous silicon cap layer.

[0031] In one embodiment, the processor/controller 64 includes a single board (SBC) analog and digital input/output boards, interface boards and stepper motor controller board. The memory 66 can be stored in a hard disk, a floppy disk, a compact disc ROM (CD-ROM), a digital video disc (DVD-ROM), a magnetic optical disk, or any other types of media suitable for storing electronic instructions. The computer program code for the computer program can be written in any conventional computer readable programming language such as 68000 assembly language, C, C++, Pascal, Fortran, or others [0032] Referring to Figure 3, the elevating apparatus 18 includes a set of elevating pins 48, a pin elevator 50, and a susceptor elevator 52. The pin elevator 50 and the susceptor elevator 52 are tubular members that extend through the apparatus opening 34 into the inner volume 24. The susceptor elevator 52 is, for the most part, located within the pin elevator 50. A portion of the susceptor elevator 52 extends out of an upper end of the pin elevator 50. A susceptor 16 is mounted to an upper end of the susceptor elevator 52. Vertical movement of the susceptor elevator 52 causes vertical movement of the susceptor 16. [0033] The pins 48 extend through openings (not shown) in the susceptor 16. Each pin 48 has a head 56 at an upper end thereof. The pin elevator 50 engages with lower ends of the pins 48. Vertical movement of the pin elevator 50 causes vertical movement of the pins 48 relative to the chamber 12. The pins 48 also move relative to the susceptor 16, assuming that the susceptor 16 is stationary.

[0034] In one embodiment, a transfer blade 70 is used to transport a substrate (or a wafer) 79 into the chamber 12 as illustrated in Figure 3. The transfer blade 70 transports the substrate 79 through the slit valve opening 32 and into the inner volume 24 of the chamber 12. In another embodiment, the transfer blade 70 is coupled to a robot assembly (not shown) that facilitates the transport of the substrate 79.

[0035] In one embodiment, to load the substrate 79, the transfer blade 70 inserts the substrate 79 through the slit valve opening 32. The pin elevator 50 is raised so that the heads 56 make contact with a lower surface of the substrate 79, and lifts the substrate 79 off the transfer blade 70. The transfer blade 70 is then removed through the slit valve opening 32.

[0036] In one embodiment, the pin elevator 50 remains stationary while the susceptor elevator 52 is raised which causes movement of the susceptor 16 in a vertically upward direction, while the pins 48 slide along the openings in the susceptor 16. The susceptor 16 is raised until an upper surface 72 of the susceptor 16 makes contact with a lower surface of the substrate 79. The susceptor 16 is then further elevated until an upper surface of the substrate 79 is at a required distance from the gas dispersion plate 38. In one exemplary embodiment, the upper surface of the substrate is at a distance of approximately 14 mm from the gas dispersion plate 38.

[0037] Figures 4A-4H illustrate an exemplary process of forming a film stack that can be used to form a semiconductor device. First, a substrate 102 is provide as illustrated in Figure 4A. In one embodiment, the substrate 102 is made of monocrystalline silicon. The substrate 102 can be other type of silicon substrate that are typically used for making semiconductor devices. In another embodiment, the substrate 102 is a silicon-containing substrate such as a silicon on insulator (SOI) substrate.

[0038] In one embodiment, a thin layer of epitaxial silicon (not shown) is formed on the substrate 102. Next, an insulation (or dielectric) layer 104 such as a gate dielectric layer is formed on the epitaxial silicon layer as shown in Figure 4B. In an embodiment where the substrate 102 does not have the epitaxial silicon layer formed thereon, the insulation layer 104 is formed directly on the substrate 102. The insulation layer 104 is typically comprised of silicon dioxide. In one embodiment, the insulation layer 104 is typically less than 25 A thick. In another embodiment, the insulation layer 104 is sufficiently thick to act as an insulation layer as is well known in the art. In one embodiment, the insulation layer 104 is made of silicon dioxide, nitrided silicon dioxide, or another dielectric material such as a high-k material. In one embodiment, the insulation layer 104 is thermally grown from the surface of the underlying silicon substrate (e.g., the epitaxial silicon layer or the substrate 102). Many conventional processes are known for forming the insulation layer 104. For instance, a conventional method such as chemical vapor deposition can be used to form the insulation layer 104 on the substrate 102.

[0039] Next, an amoφhous silicon layer 106 is formed on the insulation layer 104 as shown in Figure 4C. In one embodiment, the system 10 discussed in Figures 2 and 3 is used to form the amoφhous silicon layer 106. In one embodiment, the substrate 102 is inserted into the chamber 12. In one embodiment, the substrate 102 is positioned at approximately 14 mm from the gas dispersion plate 38. An upper surface of the insulation layer 104 is exposed when the substrate 102 is inserted into the chamber 12. In one embodiment, after the substrate 102 is loaded, the chamber 12 is set to a desired process temperature and a desired process pressure. The pressure is reduced to a range of 100 Torr- 400 Torr and ideally, to around 275 Torr. The substrate 102 is heated to a temperature approximately between 530°C and 590°C, and ideally, between 550°C and 570°C. In one embodiment, to heat the substrate 102, the susceptor 16 is heated to a temperature approximately between 560°C and 620°C ideally, between 580°C and 610°C. [0040] In one embodiment, the chamber 12 is stabilized for a brief amount of time. An inert gas such as a nitrogen (N₂) gas is introduced through the inlet ports 26 and 28. In one embodiment, the N₂ gas flow into the top of the chamber 12 is approximately 6000 standard cubic centimeters per minute (seem). The N₂ gas flow into the bottom of the chamber 12 is approximately 2000 seem. The flows of the N₂ gas are continued for approximately five seconds; more or less time may be necessary depending on the need for stabilizing the chamber 12. The flow rates of the N₂ gas can be varied from about 2000 seem to about 10,000 seem.

[0041] In one embodiment, a silicon-containing gas Si_xH_2x+2 where x is at least 2 (e.g., a disilane (Si_∑H ) gas) is introduced into the chamber 12. In one embodiment, the silicon- containing gas is not diluted (undiluted silicon-containing gas). The undiluted silicon- containing gas is introduced at a flow rate between 5 seem and 50 seem. Alternatively, the undiluted silicon-containing gas has a flow rate that will allow deposition of the amoφhous silicon film 106 having a thickness less than lOA. In another embodiment, the silicon-containing gas is diluted with a carrier or dilution gas such as an N₂ gas creating a diluted silicon-containing gas. Inert gases such as Ar, Xe, and He, may be used to dilute the silicon-containing gas.

[0042] In one embodiment, the flow rate of the diluted silicon-containing gas can be varied according to the dilution. In one embodiment, the amount of the silicon introduced into the chamber 12 from the diluted silicon-containing gas is equivalent to the amount of silicon introduced from the undiluted silicon-containing gas with a flow rate of about 10- 60 seem.

[0043] In one embodiment, the silicon-containing gas is thermally decomposed in the chamber 12 to form the amoφhous silicon layer 106 upon the insulation layer 104. The deposition of the amoφhous silicon layer 106 is continued for a predetermined amount of time, (e.g., approximately 3-5 seconds). The predetermined amount of time is chosen so that the layer 106 has a thickness less than lOA. The time for deposition may be varied according to the desired thickness for the amoφhous silicon layer 106. [0044] The amoφhous silicon layer 106 enables uniform and homogenous formation of another film on the amoφhous silicon layer 106, e.g., a silicon germanium layer 108. In one embodiment, the amoφhous silicon layer 106 is also uniform and is substantially free of surface roughness. The amoφhous silicon layer 106 is smooth and continuous. The - amoφhous characteristic of the amoφhous silicon layer 106 provides a uniform seed layer upon which the silicon germanium layer is to be formed. The amoφhous silicon layer 106 further continuously and uniformly covers the insulation layer 104. The amoφhous silicon layer 106 continuously and uniformly covers surfaces of all of the structures that may be present on the substrate 102 and beneath the amoφhous silicon layer 106. [0045] Furthermore, the amoφhous silicon layer 106 ensures that the poly depletion is minimized. The amoφhous characteristic of the layer 106 enables this layer to be ultra thin which further minimizes the poly-depletion typically seen in an electronic device with a silicon germanium layer. [0046] After the deposition of the amoφhous silicon layer 106 is completed, a silicon germanium layer 108 is formed on the amoφhous silicon layer 106 as illustrated in Figure 4D. To form the silicon germanium layer 108, with a silicon-containing gas and a germanium-containing gas are introduced into the chamber 12. In one embodiment, the silicon germanium layer 108 is formed immediately following the deposition of the amoφhous silicon layer 106. In this embodiment, the germanium-containing gas is introduced into the chamber 12 while the silicon-containing gas is continued to be fed into the chamber 12. Thus, after the deposition of the amoφhous silicon layer 106, the silicon- containing gas is not shut off and the germanium-containing gas is immediately introduced into the chamber 12.

[0047] In one embodiment, the silicon-containing gas is the same silicon-containing gas that is used to form the amoφhous silicon layer 106, e.g., a disilane gas. The silicon- containing gas can be the undiluted silicon-containing gas that is used to form the amoφhous silicon layer 106. In one embodiment, the germanium-containing gas is not diluted (undiluted germanium-containing gas). In another embodiment, the germanium- containing gas is diluted with a carrier or a dilution gas such as an H₂ gas, an Ar gas, or an N₂ gas forming a diluted germanium-containing gas. In one embodiment, the diluted germanium-containing gas contains approximately 10% germaine gas and approximately 90% H₂ gas. In another embodiment, the diluted germanium-containing gas contains about 0.5% to 50% germaine and 95% to 50% H₂ gas.

[0048] In one embodiment, the germanium-containing gas is the undiluted germanium- containing gas, which has a flow rate of about 5-50 seem. In another embodiment, the germanium-containing gas is the diluted germanium-containing gas. The flow rate of the diluted germanium-containing gas is varied depending on the dilution to introduce an equivalent amount of the germaine into the chamber 12 as when the undiluted germanium- containing gas is used.

[0049] In one embodiment, the relative flow rates of the undiluted silicon-containing gas and the undiluted germanium-containing gas are approximately 1.5. In another embodiment, the undiluted silicon-containing gas and the undiluted germanium-containing gas have a flow ratio between 0.5 and 5.0.

[0050] In one embodiment, the process temperature and the process pressure for the deposition of the silicon germanium layer 108 is within the same range as the process temperature and the process pressure that are used for the deposition of the amoφhous silicon layer 106, for example, a temperature between 560-590°C and a pressure between 100-400 Torr. In one embodiment, the process temperatures for the formation of the amoφhous silicon layer 106 and the formation of the silicon germanium layer 108 overlap by being within a particular temperature range, between 560-590°C. In this particular temperature range, the amoφhous silicon layer 106 that is formed is amoφhous and that the silicon germanium layer 108 that is formed is either amoφhous silicon germanium or polycrystalline silicon germanium. In one embodiment, the silicon germanium layer 108 is a polycrystalline silicon germanium layer.

[0051] An advantage of using a silicon source gas Si_xH_2x+2 (e.g., disilane (Si₂H_ό)) gas as opposed to a monosilane gas (SiFL_t) is that the Si_xH_2x+2 gas has a similar thermal reactivity to a germaine (GeH gas. The molecules in the Si_xH_2x+2 and the germaine gases break down at a more similar rate at a particular temperature than the molecules from the monosilane and the germaine gases. The similarity in reactivity between the Si_xH_2x+2 and the germaine gases results in a higher film quality for the silicon germanium layer 108. Additionally, the Si_xH_2X+2 also results in a more silicon-rich film in the amoφhous silicon layer 106 and with better uniformity. Although not specifically tested, it is also believed that higher-order silane gases, such as Si₃H₈, may provide benefits over silane gas, although not as good as disilane gas.

[0052] In one embod..:.ent, the deposition of the silicon germanium layer 108 is continued for approximately 25 seconds, so that the silicon germanium layer 108 is approximately 500 A thick. The time of deposition may be varied depending on the desired film thickness. In one embodiment, the deposition for the silicon germanium layer 108 is continued for an amount of time sufficient to form a 500-100θA thick silicon germanium layer 108.

[0053] In one embodiment, the germanium has an atomic count of 30% in the silicon germanium layer 108. In another embodiment, the atomic count may be between 5% and 50%, or more typically, between 15% and 40%.

[0054] In one embodiment, an amoφhous silicon cap layer 110 is formed on the silicon germanium layer 108 as illustrated in Figure 4E. To form the amoφhous silicon cap layer 110, a silicon-containing gas is used. In one embodiment, the amoφhous silicon cap layer 110 is formed immediately after the silicon germanium layer 108 is formed. In this embodiment, the flow of the undiluted or the diluted germanium-containing gas that is introduced into the chamber 12 to form the silicon germanium layer 108 is shut off; and, the flow of the diluted or undiluted silicon-containing gas that is introduced into the chamber 12 to form the silicon germanium layer 108 is maintained. In one embodiment, the flow of the diluted or undiluted silicon-containing gas is increased to form a thick amoφhous silicon cap layer 110 (typically, thicker than the amoφhous silicon layer 106 or the silicon germanium layer 108). In one embodiment, the amoφhous silicon cap layer 110 is approximately 700 A thick. In another embodiment, the amoφhous silicon cap layer 110 is between 100 and 1000 A thick. In one embodiment, the amoφhous silicon cap layer 110 is formed under the same conditions, e.g., temperature and pressure, as for the amoφhous silicon layer 106 described above.

[0055] In one embodiment, the amoφhous silicon layer 106, the silicon germanium layer 108, and the amoφhous silicon cap layer 110 are formed at a temperature between 560°C and 590°C as illustrated in Figure 5. This particular temperature range is indicated as a range "A" in Figure 5. In one embodiment, the depositions of these layers, 106, 108, and 110, occurs in one deposition chamber (e.g., the chamber 12). The x-axis of Figure 5 indicates the process time. The y-axis of Figure 5 indicates the process temperature. At the process time Tl, the amoφhous silicon layer 106 is formed. Next, at a later process time T2, the silicon germanium layer 18 is formed. Next, at a yet later process time T3, the amoφhous silicon cap layer 110 is formed.

[0056] In one embodiment, Figure 5 further illustrates that at a process pressure, e.g., 275 Torr, amoφhous silicon is formed when the process temperature is below 625°C and polysilicon is formed when the temperature is above 625°C at the process time Tl using the silicon-containing gas. As the process time moves into the time T2 and as the germanium-containing gas is introduced, amoφhous silicon germanium is formed when the temperature is below 550°C and polycrystalline silicon germanium is formed when the temperature is above 550°C. As the process time moves to the time T3 and as the germanium-containing gas is cut off, amoφhous silicon is again formed when the process temperature is below 625°C and polysilicon is formed when the temperature is above 625°C.

[0057] In one embodiment, the process temperature (560-590°C) is thus chosen such that the amoφhous silicon layer 106 is amoφhous, the silicon germanium layer 108 is polycrystalline, and the amoφhous silicon cap layer 110 is amoφhous. Depositing the layers 106, 108, and 110 under the same temperature alleviates the need and/or the difficulty of adjusting the temperature between the fabrication of the different layers. Alleviating the need to adjust the temperature between different layer formations is especially useful when a resistively heated single-wafer deposition chamber such as the chamber 12 is used for forming the layers 106, 108, and 110. The deposition an additional layer can take place immediately following the deposition of a previous layer since there is no need to change the temperature setting of the deposition chamber. [0058] Next, the insulation layer 104, the amoφhous silicon layer 106, the silicon germanium layer 108, and the amoφhous silicon cap layer 110 are masked and etched as illustrated in Figure 4F. In one embodiment, the insulation layer 104, the amoφhous silicon layer 106, the silicon germanium layer 108, and the amoφhous silicon cap layer

110 are patterned to a desired gate length and gate width of a transistor. In one embodiment, conventional methods such as photolithography and reactive ion etching process are used to pattern the structure shown in Figure 4F.

[0059] In one embodiment, the amoφhous silicon layer 106, the silicon germanium layer 108, and the amoφhous silicon cap layer 110 jointly form a gate electrode 111 of a transistor. In one embodiment, the transistor is a PMOS (Positive Channel Metal Oxide Semiconductor) device; and substrate 102 is n-doped. In one embodiment, boron is implanted into the gate electrode 111 so that the gate electrode 111 is p-doped. Optionally, boron is also implanted into surfaces of the substrate 102 on opposing sides of the gate electrode 111 to form source and drain regions 114 as shown in Figure 4F. [0060] In another embodiment, the transistor is an NMOS (Negative Channel Metal Oxide Semiconductor) device; and the substrate 102 is p-doped. In one embodiment, phosphorous or arsenic is implanted into the gate electrode 111 so that the gate electrode

111 is n-doped. Optionally, phosphorous or arsenic is also implanted into surfaces of the substrate 102 on opposing sides of the gate electrode 111 to form source and drain regions 114 as shown in Figure 4F.

[0061] In one embodiment, a dielectric film 112 (e.g., silicon dioxide, silicon nitride, or nitride oxide) is blanketly deposited over the gate electrode 111 and the gate dielectric 104 as shown in Figure 4G. Conventional methods such as anisotropic reactive ion etching can be used to etch the dielectric film 112 to form spacers 112A and 112B next to side surfaces of the gate electrode 111 and the gate dielectric 104, (see Figure 4H), and more boron can be doped into the gate electrode 111 and the substrate 102 using conventional methods. .

[0062] In one embodiment, the substrate 102 is heated to activate the boron and make the electrode conductive. The boron diffuses throughout the gate electrode 111. The silicon germanium layer 108, however, prevents boron diffusion through the insulation layer 104 and into the substrate 102. Boron is prevented from entering the substrate 102 and impairing the switching characteristics in a channel between the source and drain regions 114. Boron is also prevented from depleting out of a lower region of the silicon germanium layers 108, referred to as "poly depletion problems," which increases the effective gate dielectric thickness.

[0063] An advantage of having the amoφhous silicon layer 106 between the gate dielectric layer 102 and the silicon germanium layer 108 is that the amoφhous silicon layer 106 ensures that the silicon germanium is uniformly deposited on the gate dielectric layer 102 without segregation. The ultra-thin characteristic of the amoφhous silicon layer 106 minimizes the poly-depletion in the electronic device. The amoφhous characteristic of the amoφhous silicon layer 106 ensures that the surfaces of the structure beneath the amoφhous silicon layer 106 are uniformly and continuously covered. [0064] In one embodiment, the various layers discussed above are formed in situ, in one deposition chamber. With the process temperature carefully chosen as discussed above (Figure 5), there is no need to change temperature for the formation of the different layers. For example, the amoφhous silicon layer 104 is formed using the temperature range as that for the germanium silicon 108 and the amoφhous silicon cap layer 110. [0065] In another embodiment, the various films described above can be formed in different chambers that are arranged into a cluster tool. Figure 6 illustrates an exemplary cluster tool 1100 that includes several processing chambers. For example, the cluster tool 1100 includes a silicon oxide deposition chamber 1102, an annealing chamber 1104, a silicon film deposition chamber 1105, and a silicon oxynitride deposition chamber 1106. Each of the silicon oxide deposition chamber 1102, the silicon deposition chamber 1105, and the silicon oxynitride deposition chamber 1106 can be a reaction chamber like the chamber 12 described above. [0066] The cluster tool 1100 also includes a transfer chamber 1108 having a wafer handler 1109 (e.g., a robot), which includes a wafer clip 1112 for handling a wafer that is to be deposited into one of the chambers mentioned above. The wafer clip 1112 can be the transfer blade 70 described above in Figure 2. The transfer chamber 1108 is further coupled to a load lock system 1110, which stores the substrates to be processed. In one embodiment, the wafer handler 1109 removes a substrate (e.g., a wafer) from the load lock system 1110 and places the substrate into an appropriate chamber depending on a process protocol. The wafer handler 1109 also removes the substrate from the chamber once the processing is complete and moves the substrate to the next processing chamber or into the load lock system 1110. [0067] The transfer chamber 1108 is typically set at a reduced pressure as compared to the atmospheric condition. The transfer chamber 1108 can also be set at a pressure close to the process pressure that the chambers will be operating at. The cluster tool 1100 is also set at a pressure that once the wafers are in the load lock system 1110, the loading of other substrates into other chambers does not impact the operating conditions inside each chamber. When multiple processes are involved, the wafer handler 1109 is used to move the substrate from one chamber to the next chamber for each process.

[0068] In one embodiment, the cluster tool 1100 also includes a processor/controller and a memory similar to the processor/controller 64 and the memory 66 included in the system 10 described above. A program or a set of instructions is stored the memory that enables the processor/controller to operate the cluster tool 1100. The program provides for the operation of moving the substrate(s) in and out of any particular chamber in the cluster tool 1100 for processing. Additionally, the program may also provide for the operations of the system 10 similar to the processor/controller 64 described above. [0069] While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described since modifications may occur to those ordinarily skilled in the art.

Claims

CLAIMSWhat is claimed:

1. A method of forming a semiconductor device comprising: depositing an amoφhous silicon layer having a first thickness less than 10 A directly on a an insulation layer, the insulation layer being formed over a semiconductor substrate; and depositing a silicon germanium layer directly on the amoφhous silicon layer.

2. The method as in claim 1 wherein the insulation layer has a second thickness less than 25 A.

3. The method as in claim 1 wherein the insulation layer is a gate dielectric layer.

4. The method as in claim 1 wherein the semiconductor substrate is silicon and the insulation layer comprises one of silicon dioxide, nitrided silicon dioxide, and a high-k material.

5. The method as in claim 1 wherein a silicon-containing gas is used to deposit the amoφhous silicon layer wherein the silicon-containing gas is Si_xH_2X+2 wherein x is at least 2.

6. The method as in claim 5 wherein the silicon-containing gas is diluted.

7. The method as in claim 5 wherein a germanium-containing gas is used to deposit the silicon germanium layer wherein the germanium-containing gas is GeH

8. The method as in claim 7 wherein the germanium-containing gas is diluted.

9. The method as in claim 8 wherein a ratio between the silicon-containing gas and the germanium-containing gas is between 0.5 and 5.0.

10. The method as in claim 8 wherein the germanium-containing gas is diluted to a concentration between 0.5% to 50%.

11. The method as in claim 1 wherein an atomic count of germanium in the silicon germanium layer is between 5% and 50%.

12. The method as in claim 1 further comprising: heating the semiconductor substrate to a temperature between 560°C and 590°C when the amoφhous silicon layer and the silicon germanium layer are being deposited.

13. The method as in claim 1 wherein the depositing of the amoφhous silicon layer and the depositing the silicon germanium layer occur in a single wafer deposition chamber.

14. The method as in claim 13 wherein the single-wafer deposition chamber is maintained at a pressure between 100 Torr and 400 Torr during the depositing of the amoφhous silicon and the silicon germanium layers.

15. The method as in claim 1 further comprising depositing an amoφhous silicon cap layer over the silicon germanium layer.

16. The method as in claim 15 wherein the depositing of the amoφhous silicon layer, the depositing the silicon germanium layer, and the depositing of the amoφhous silicon cap layer occur in a single wafer deposition chamber.

17. The method as in claim 16 wherein the single-wafer deposition chamber is maintained at a pressure between 100 Torr and 400 Torr during the depositing of the amoφhous silicon layer, the depositing the silicon germanium layer, and the depositing of the amoφhous silicon cap layer.

18. The method as in claim 17 further comprising: heating the semiconductor substrate to a temperature between 560°C and 590°C when the amoφhous silicon layer, the silicon germanium layer and the amoφhous cap layer are being deposited.

19. The method as in claim 15 wherein the amoφhous silicon layer, the silicon germanium layer, and the amoφhous silicon cap layer jointly form a gate electrode of a transistor.

20. The method as in claim 19 further comprises doping said gate electrode.

21. A method of forming a semiconductor device comprising: placing a semiconductor substrate in a single-wafer deposition chamber, the semiconductor substrate having an insulation layer formed thereon; heating the semiconductor substrate to a temperature between 560°C and 590° C; forming an amoφhous silicon layer that is less than 10 A thick on the gate dielectric layer by introducing a silicon-containing gas into the single-wafer deposition chamber, the silicon-containing gas being Si_xH_2x+2 wherein x is at least 2 and thermally decomposing the silicon-containing gas while continuing heating the semiconductor substrate; and forming a silicon germanium layer on the amoφhous silicon layer by introducing a germanium-containing gas into the single-wafer deposition chamber together with the silicon-containing gas and thermally decomposing the germanium- containing gas and the silicon-containing gas while continuing heating the semiconductor substrate; wherein the single-wafer deposition chamber has a pressure between 100 Torr and 400 Torr when the amoφhous silicon layer and the silicon germanium layer are being formed.

22. The method as in claim 21 further comprising: forming an amoφhous silicon cap layer on the silicon germanium layer by cutting off the germanium-containing gas into the single-wafer chamber and thermally decomposing the silicon-containing gas while continuing heating the semiconductor substrate.

23. The method as in claim 21 wherein the semiconductor substrate is silicon and the insulation layer comprises one of silicon dioxide, nitrided silicon dioxide, and a high-k material.

24. The method as in claim 21 wherein the germanium-containing gas is GetL_t.

25. The method as in claim 21 wherein an atomic count of germanium in the silicon germanium layer is between 5% and 50%.

26. The method as in claim 21 wherein the single-wafer deposition chamber is a resistively heated chamber.

27. The method as in claim 22 wherein the amoφhous silicon layer together with the silicon germanium layer and together with the amoφhous cap layer jointly form at least a part of a gate electrode of a transistor.

28. The method as in claim 27 further comprises doping said gate electrode.

29. A semiconductor device comprising: a semiconductor substrate having a first conducting type; a gate dielectric layer formed over the semiconductor substrate; and a gate electrode formed directly on the gate dielectric; the gate electrode including an amoφhous silicon layer, a silicon germanium layer, and an amoφhous silicon cap layer, wherein the amoφhous silicon layer is less than 10 A thick and is deposited directly over the gate dielectric, wherein the silicon-germanium layer is deposited directly over the amoφhous silicon layer.

30. The semiconductor device as in claim 29 wherein the amoφhous silicon layer, the silicon germanium layer, and the amoφhous silicon cap layer of the gate electrode are formed in a single-wafer deposition chamber using a process temperature range between 560°C and 590°C

31 The semiconductor device as in claim 29 further composing source/drain regions formed on opposite sides of the gate electrode, the source/drain regions having a second conductivity type opposite to the first conductivity type of the semiconductor substrate.

32. The semiconductor device as in claim 29 wherein the silicon germanium layer is a polycrystalline layer.

33. The semiconductor device as in claim 29 wherein the silicon germanium layer is an amoφhous layer.

34. The semiconductor device as in claim 29 wherein the silicon germanium layer includes an atomic count of 5% to 50% of germanium.

35. A substrate processing system including: a susceptor, located within a deposition chamber, the susceptor to hold a substrate duπng a substrate processing; a gas supply apparatus to introduce process gas mixtures into the deposition chamber to form a gate electrode composing an amoφhous silicon layer having a thickness less than 10 A, a silicon germanium layer formed on the amoφhous silicon layer, and an amoφhous silicon cap layer formed on the silicon germanium layer; a controller for controlling the gas delivery system; and a memory device coupled to the controller, the memory device composes a computer-readable medium having a computer readable program embodied therein for directing operation of the substrate processing system, the computer-readable program including instructions for controlling the gas supply apparatus to introduce the process gas mixtures, for obtaining a process temperature from 560°C to 590°C, for obtaining a process pressure from 100 Torr to 400 Torr, and for controlling flow rates for the process gas mixtures.

36. A substrate processing system processing system as in claim 35 wherein the instructions are further for introducing the process gas mixtures comprising a silicon- containing gas and a germanium-containing gas, wherein the silicon-containing gas being Si_xH_2x+2 wherein x is at least 2.

37. A substrate processing system as in claim 35 wherein said germanium-containing gas is germaine (GeHj).

38. A substrate processing system processing system as in claim 35 wherein the instructions are further for introducing the silicon containing gas to form the amoφhous silicon layer, introducing the silicon-containing gas simultaneously with the germanium-containing gas to form the silicon germanium layer, and cutting off the germanium-containing gas while continuing introducing the silicon-containing gas to form the amoφhous silicon cap layer.