WO2004013949A2 - Convertisseur tension/tension pour circuits integres. - Google Patents
Convertisseur tension/tension pour circuits integres. Download PDFInfo
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- WO2004013949A2 WO2004013949A2 PCT/FR2003/002351 FR0302351W WO2004013949A2 WO 2004013949 A2 WO2004013949 A2 WO 2004013949A2 FR 0302351 W FR0302351 W FR 0302351W WO 2004013949 A2 WO2004013949 A2 WO 2004013949A2
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
Definitions
- the invention relates to a voltage / voltage converter for integrated circuits, which has particular applications in the production of EEPROM memories and low voltage integrated circuits.
- CMOS voltage / voltage converters are used in particular in two main areas, namely: “EEPROM” memories also called “FLASHROM”, and low voltage integrated circuits in order to supply certain parts of these circuits with higher voltages.
- EEPROM electrically erasable read-only memory
- FLASHROM low voltage integrated circuits
- Low-voltage integrated circuits are also in full expansion and in particular used in consumer products such as cell phones and portable devices mentioned above.
- the main technical problem to be solved is to increase the output voltage of the converter as much as possible for a given number of stages.
- a programming voltage of nine volts is required in order to be able to store information in a memory of the "FLASHROM" type.
- the invention aims to design a new voltage / voltage converter structure which is able to meet several goals, in particular:
- the invention provides a voltage / voltage converter for integrated circuits, having a symmetrical structure with several stages and comprising at least one input stage constituted by a clock booster circuit with symmetrical structure which delivers two voltages of output, a voltage multiplier stage with symmetrical structure comprising two voltage multiplier circuits respectively mounted in two branches of the converter and to which the two output voltages of the input stage are respectively applied, and an output stage constituted by a circuit multiplexer to which the two output voltages of the voltage multiplier stage are applied, which is characterized in that each voltage multiplier circuit is controlled by a control circuit, and in that each voltage multiplier circuit supplies the voltages necessary for operation of its control circuit on the one hand and at the fo operation of the control circuit of the other voltage multiplier circuit of the same stage on the other hand.
- the function of the clock booster circuit is to add a DC component to a clock signal, and it comprises two similar circuits which respectively receive two clock signals having opposite phases,
- each voltage multiplier circuit includes a capacitor and a switch for controlling the charge of the capacitor and the transfer of its charge to the voltage multiplier circuit of the next stage, and
- each voltage multiplier circuit is controlled by a control circuit and supplies the voltages necessary for the operation of its control circuit on the one hand and for the operation of the control circuit of the other voltage multiplier circuit of the same stage of somewhere else.
- the converter according to the invention can have a positive output and, in this case, the multiplexer circuit recovers the highest voltages from the voltage multiplier circuits and, by switching, extracts the highest direct voltage which forms the output voltage. of the converter. Conversely, the converter can be at negative output and, in this case, the multiplexer circuit recovers the lowest voltages from the voltage multiplier circuits and, by switching from it extracts the lowest direct voltage which forms the output voltage of the converter.
- the structure of the voltage / voltage converter according to the invention allows the advantages of a symmetrical structure to be preserved.
- the Applicants have carried out tests and have been able to demonstrate that a voltage / voltage converter with symmetrical structure is more efficient in particular for applications on resistive load than a converter with non-symmetrical structure.
- a converter with a symmetrical structure exhibits better load carrying capacity and the result is that the smoothing capacity to be added at the output may have a lower value, which makes it possible to reduce the total surface area of the converter.
- the output voltage rises faster than in the case of a non-symmetrical structure.
- the structure of the voltage / voltage converter according to the invention also makes it possible to reduce the effect of stray capacitances to obtain better efficiency and a higher output voltage. This result is obtained by using voltage multiplier circuits based on the structure of the DICKSON circuit, while the Applicants had made first tests on a voltage / voltage converter which used a capacity stacking technique.
- FIG. 1 shows in the form of a block diagram the general structure of a voltage / voltage converter according to the invention
- FIG. 2 illustrates a first embodiment of a voltage / voltage converter according to the invention and with positive output
- Figures 3 and 4 respectively illustrate two multiplexer circuits which can each constitute the output stage of the voltage / voltage converter with positive output of Figure 2;
- FIG. 5 illustrates a second embodiment of a voltage / voltage converter according to the invention and with positive output
- - Figure 6 illustrates a first embodiment of a voltage / voltage converter according to the invention and with negative output
- - Figures 7 and 8 respectively illustrate two multiplexer circuits which can each constitute the output stage of the voltage / voltage converter with negative output of Figure 6;
- FIG. 9 illustrates a second embodiment of a voltage / voltage converter according to the invention and with negative output; and - Figures 10 and 11a to 11d are views which will be used to explain the operation of the first embodiment of the converter illustrated in Figure 2.
- FIG. 1 The general structure of a voltage / voltage converter according to the invention is illustrated in FIG. 1, knowing that this converter 10 has a symmetrical structure, with several stages and with positive or negative output voltage. More specifically, the converter comprises at least N stages connected in cascade, the first stage being constituted by a clock booster circuit CB with symmetrical structure.
- the following (N-1) intermediate stages each consist of two voltage multiplier circuits CMj and CMjp (i varying from 2 to N) which form a symmetrical structure. These two voltage multiplier circuits are respectively controlled by two circuits of CCj and CCj P which deliver control voltages V C i and V (i varying from 2 to N).
- Each voltage multiplier circuit uses the charge transfer technique of the DICKSON circuit mentioned in the preamble, and supplies part of the voltages necessary for the operation of its control circuit on the one hand, and part of the voltages necessary for the operation of the other multiplier circuit on the other hand.
- the voltage / voltage converter has an output stage S which is constituted by a multiplexer circuit MX receiving the output voltages VN and VN P from the two multiplier circuits CMN and CMN P of the last intermediate stage to reconstruct a continuous output voltage V s . All these stages will be described in detail below with reference to Figures 2 to 9 which illustrate several embodiments.
- the voltage / voltage converter 10 has a positive output, has a symmetrical structure with two branches Bi and B 2 , and comprises several stages.
- the first stage or input stage is a clock booster circuit CB with symmetrical structure and with positive output, comprising a transistor Mi of NMOS type and a capacitor Ci for the branch B ⁇ of the converter 10, and a transistor M ⁇ p of NMOS type and a capacitor C ⁇ p for branch B 2 of the converter 10.
- the transistors Mi and M ⁇ p have their drains connected to a supply voltage V d , and their sources respectively connected to the positive electrodes of the capacitors Ci and C ⁇ p .
- the gate of transistor M is connected to the source of transistor M ⁇ p and vice versa.
- the negative electrodes of the capacitors Ci and C ⁇ p are respectively connected to two clock signals ⁇ i and ⁇ 2 which are in phase opposition.
- the (N-1) stages which follow are cascaded each comprise two voltage multiplier circuits CM, and CMj P (i varying from 2 to N) respectively mounted in the two branches Bi and B 2 of the converter 10 to form a structure symmetrical, each multiplier circuit taking up the basic structure of the DICKSON circuit.
- Each voltage multiplier circuit CMj of the branch Bi comprises a capacitor Ci whose positive electrode is connected to the output terminal of a switch Kj by a node Vj, and whose electrode negative is connected to a clock signal ⁇ n .
- each voltage multiplier circuit CMj P of branch B 2 comprises a capacitor Cj P whose positive electrode is connected to the output terminal of a switch Kj P by a node Vj P and whose negative electrode is connected to a clock signal ⁇ np (i varying from 2 to N).
- the clock signal ⁇ n corresponds to the clock signal ⁇ -i of the clock boost circuit CB if i is odd and to the signal ⁇ 2 of the clock boost circuit CB if i is even, and vice versa for the signal d 'clock ⁇ np , these two clock signals ⁇ i and ⁇ 2 corresponding to those received by the clock booster circuit CB.
- the input terminal of the switch Kj of the branch Bi of the converter 10 is connected to the node Vj_ ⁇ of the previous stage, while the input terminal of the switch Kj P of the branch B 2 of the converter 10 is connected to node V ( n ) P of the previous stage.
- Each control circuit C of a voltage multiplier CMj of the branch Bi of the converter 10 comprises an inverter circuit lj whose output voltage provides the control voltage V C j applied to the control input of the switch Kj of the CMJ voltage multiplier circuit (i varying from 2 to N).
- Each inverter circuit lj is supplied between the output voltage V ⁇ i of the multiplier circuit CMj. ⁇ of the previous stage of the branch Bi of the converter 10 on the one hand and the output voltage Vj P of the voltage multiplier circuit CMj P of l 'corresponding stage of the branch B 2 of the converter 10 on the other hand.
- the voltage Vj P is supplied by the voltage multiplier circuit CMj P of the same stage but from the branch B 2 of the converter 10.
- the inverter lj is controlled by a input signal which is constituted by the output signal V c (i-1) of the previous stage (i varying from 3 to N) to obtain an output signal V ci , knowing that the inverter l 2 is controlled by the output signal V ⁇ p from branch B 2 of the clock boost circuit CB of the first stage of the converter 10.
- each control circuit CCj P of a voltage multiplier CMj P of branch B 2 of the converter 10 comprises an inverter circuit lj P , the output voltage of which supplies the control voltage V C j P applied to the control input of the switch Kj P of the voltage multiplier circuit CM ip (i varying from 2 to N).
- Each inverter circuit lj P is supplied between the output voltage V ( M) P of the voltage multiplier circuit CM () P of the previous stage of branch B 2 of the converter 10 on the one hand and the output voltage Vj of the voltage multiplier circuit CMj of the corresponding stage of the branch Bi of the converter 10 on the other hand.
- the output voltage V ( H) P is supplied by the voltage multiplier circuit CM ( H ) P of the branch B 2 of the converter 10, apart from the voltage V ⁇ p , the voltage V-, is supplied by the voltage multiplier circuit CMj of the same stage but from the branch Bi of the converter 10.
- the inverter l ip is controlled by an input signal which is constituted by the output signal V C (ji ) P of the previous stage (i varying from 3 to N) to obtain an output signal V C j P , knowing that the inverter l 2p is controlled by the output signal Vi of the branch Bi of the booster circuit d ' CB clock of the first stage of the converter 10.
- the multiplexer circuit MX which constitutes the output stage S of the voltage / voltage converter 10 of FIG. 2 is the subject of two embodiments which are illustrated in FIGS. 3 and 4.
- the function of the multiplexer circuit MX is to recover the highest voltages of the voltage multiplier circuits and, by switching, extracts the highest direct voltage which forms the output voltage of the converter. According to the first embodiment of FIG.
- the multiplexer circuit MX is based on the use of two switches K s ⁇ and K s2 which, on the output side, share the same output node corresponding to the output voltage V s of the converter 10 and which, on the input side, are respectively connected to the two output voltages VN P and VN of the two voltage multiplier circuits CM Np and CMN of the stage N of the converter 10.
- the multiplexer circuit MX also includes an auxiliary circuit for producing the control signals of the two switches K s ⁇ and K s2 , this circuit auxiliary consisting of two inverter circuits i (N + i) p and IN + L of two switches K s3 and K s4 , and two capacitors C ( N + I) P and CN + I.
- the switch K s3 shares the same control and input signals as those of the switch K s ⁇ , while the switch K s4 shares the same control and input signals as those of the switch K s2 .
- the switch K s3 is connected between the output voltage VN P of the multiplier circuit CMN P of the branch B 2 of stage N of the converter 10 and the positive electrode of the capacitor C (N + i) P of which the negative electrode is boosted by the clock signal ⁇ ( n + i) - Symmetrically
- the switch K s4 is connected between the output voltage V of the multiplier circuit CMN of the branch B ⁇ of the stage N of the converter 10 and the positive electrode of the capacitor CN + I, the negative electrode of which is boosted by the clock signal ⁇ n + ⁇ .
- the inverter circuit IN + I has as an input signal the control signal V C N of the multiplier circuit CMN of stage N of the branch Bi of the converter 10, and it is supplied between the voltage of output V N as low supply and voltage V ( N + I> P as high supply.
- the multiplexer circuit MX generally takes up the structure of that illustrated in FIG. 3. The only difference resides in the fact that the input signal of the inverter circuit I ⁇ N + I) P is the signal V ( N + I) instead of the signal V C N P , and the input signal of the inverter circuit l N + ⁇ is the signal VN + I instead of the signal V C N.
- the voltage / voltage converter 10 is also with positive output and differs only in terms of the control circuits CCj and CC ip of the multiplier circuits voltage CMj and CM ip (i varying from 2 to N). More precisely, the inverter circuit lj of each control circuit CCj is supplied between the output voltages Vj_ ⁇ and Vj P , knowing that the output voltage Vu is that produced by the voltage multiplier circuit CMj- ⁇ of the previous stage of the branch Bi of the converter 10, and the output voltage Vj P is that produced by the voltage multiplier circuit CMi P of the corresponding stage of branch B 2 of the converter 10.
- each inverter circuit lj is controlled by the output signal Vj from the voltage multiplier circuit CM, to produce the output signal V cj .
- the inverter circuit lj P of each control circuit CCj P is supplied between the output voltages V ( MP and Vj, knowing that the output voltage V ( ji ) P is produced by the voltage multiplier circuit CM ( ji ) P of the previous stage of branch B 2 of converter 10, and the output voltage Vj is that produced by the voltage multiplier circuit CMj of the corresponding stage of branch Bi of converter 10.
- each inverter circuit ip is controlled by the output signal Vj P of the voltage multiplier circuit CM ⁇ p to produce the output signal V cip .
- the multiplexer circuit MX which forms the output stage of the converter 10 can be produced according to one of the two examples illustrated in FIGS. 3 and 4.
- FIG. 6 illustrates a first embodiment of a voltage / voltage converter according to the invention but with negative output, knowing that it also has several stages and a symmetrical structure with two branches Bi and B 2 .
- the first stage or input stage is a clock booster circuit with symmetrical structure and with negative output, comprising a transistor PM of the PMOS type and a capacitor Ci for the branch B ⁇ of the converter 10, and a transistor M- ⁇ p PMOS type and a capacitor C ⁇ p for branch B 2 of the converter 10.
- the transistors M ⁇ and M ⁇ p have their drains connected to a zero volt ground, and their sources respectively connected to the negative electrodes of the capacitors Ci and C ⁇ p .
- the gate of transistor Mi is connected to the source of transistor M- ⁇ p and vice versa.
- the positive electrodes of the capacitors Ci and C ⁇ p are respectively connected to two clock signals ⁇ 1 and ⁇ 2 which are in phase opposition.
- the (N-1) stages which follow and are connected in cascade each comprise two voltage multiplier circuits CMj and CMj P (i varying from 2 to N) respectively mounted in the two branches Bi and B 2 of the converter 10 to form a symmetrical structure, each voltage multiplier circuit taking up the basic structure of the DICKSON circuit.
- Each voltage multiplier circuit CMj of the branch B ⁇ comprises a capacitor Cj whose negative electrode is connected to the output terminal of a switch Kj by a node Vj, and whose positive electrode is connected to a signal d ' clock ⁇ n .
- each voltage multiplier circuit CMj P of branch B 2 comprises a capacitor Cj P whose negative electrode is connected to the output terminal of a switch Kj P by a node Vj P and whose positive electrode is connected to a clock signal ⁇ np (i varying from 2 to N).
- the clock signal ⁇ n corresponds to the clock signal ⁇ i of the clock boost circuit CB if i is odd and to the signal ⁇ 2 of the clock boost circuit CB if i is even, and vice versa for the clock signal ⁇ np , these two clock signals ⁇ -i and ⁇ 2 corresponding to those received by the clock booster circuit CB.
- the entrance terminal of .
- Each control circuit CCj of a voltage multiplier CMj of the branch Bi of the converter 10 comprises an inverter circuit lj, the output voltage of which supplies the control voltage V C j applied to the control input of the switch Kj of the voltage multiplier circuit CMj (i varying from 2 to N).
- Each inverter circuit lj is supplied between the output voltage V ip of the voltage multiplier circuit CMj P of the corresponding stage of branch B 2 of the converter 10 and the output voltage Vj.-i of the multiplier circuit CMj.i of l 'previous stage of the branch Bi of the converter 10. It is important to note that if the output voltage Vj_ ⁇ is supplied by the voltage multiplier circuit CMj_ ⁇ of the branch Bi of the converter 10, apart from the voltage V 1 t the voltage V ip is supplied by the CM ip voltage multiplier circuit of the same stage but of branch B 2 of the converter 10.
- the inverter lj is controlled by an input signal which is constituted by the output signal V C (ji ) of the previous stage (i varying from 3 to N) to obtain an output signal V C j, knowing that the inverter l 2 is controlled by the output signal V ⁇ p from branch B 2 of the clock boost circuit CB of the first stage of the converter 10.
- each control circuit CC ip of a voltage multiplier CMj P of branch B 2 of the converter 10 comprises an inverter circuit lj P , the output voltage of which supplies the control voltage V C j P applied to the control input of the switch Kj P of the voltage multiplier circuit CMj P (i varying from 2 to N).
- Each inverter circuit lj P is supplied between the output voltage Vj of the voltage multiplier circuit CMj of the corresponding stage of the branch Bi of the converter 10 and the output voltage V ( j_i ) P of the voltage multiplier circuit CM ( j. 1) p from the previous stage of branch B 2 of the converter 10.
- the multiplexer circuit MX which constitutes the output stage S of the voltage / voltage converter 10 with negative output of FIG. 6 is the subject of two exemplary embodiments which are illustrated in FIGS. 7 and 8.
- the function of the multiplexer circuit MX is recover the lowest voltages of the voltage multiplier circuits and, by switching, extract the lowest direct voltage which forms the output voltage of the converter. According to the first exemplary embodiment of FIG.
- the multiplexer circuit MX is based on the use of two switches K s ⁇ and K s2 with reverse control which, on the output side, share the same output node corresponding to the output voltage V s of the converter 10 and which, on the input side, are respectively connected to the two output voltages V P and V of the two voltage multiplier circuits CMN P and CMN of stage N of the converter 10.
- the circuit multiplexer MX also includes an auxiliary circuit for producing the control signals of the two switches K s1 and K s2 , this auxiliary circuit consisting of two inverter circuits I ( + I) P and IN + I, of two switches K s3 and K s , and two capacitors C (N + i) P and
- the switch K s3 shares the same control and input signals as those of the switch K s ⁇ , while the switch K s4 shares the same control and input signals as those of the switch K s2 .
- the switch K s3 is connected between the output voltage V P of the multiplier circuit CMN P of the branch B 2 of stage N of the converter 10 and the negative electrode of the capacitor C (N + i) P of which the positive electrode is boosted by the clock signal ⁇ (n + i) P.
- the switch K s is connected between the output voltage VN of the multiplier circuit CMN of the branch Bi of stage N of the converter 10 and the negative electrode of the capacitor C + I including the positive electrode is boosted by the clock signal ⁇ n + ⁇ .
- the inverter circuit l (+ i) has as an input signal the control signal V C N P of the voltage multiplier circuit CMN of stage N of branch B 2 of converter 10, and it is supplied between the voltage of output V Np as high supply and voltage VN + I as low supply.
- the inverter circuit IN + I has as an input signal the control signal V cN of the multiplier circuit CMN of stage N of the branch Bi of the converter 10, and it is supplied between the output voltage VN as high supply and voltage V (N + i) P as low supply.
- the multiplexer circuit MX generally takes up the structure of that illustrated in FIG. 7.
- the input signal of the inverter circuit l (N + i) p is the signal V ( N + I ) P instead of the signal V C N P
- the input signal of the inverter circuit l N + ⁇ is the signal VN + I instead of the signal V cN .
- the voltage / voltage converter 10 is also at negative output and differs only in terms of the control circuits CCj and CCj P of the circuits voltage multipliers CMj and CMj P (i varying from 2 to N).
- each inverter circuit lj of each control circuit CCj is supplied between the output voltages V ip and Vu, knowing that the output voltage Vj.-) is that produced by the multiplier circuit of the previous stage of the branch Bi of the converter 10, and the output voltage Vj P is that produced by the multiplier circuit CMj P of the corresponding stage of the branch B 2 of the converter 10.
- each inverter circuit lj is controlled by the output signal Vj of the voltage multiplier circuit CMj to produce the output signal V C j.
- the inverter circuit lj P of each control circuit CC ip is supplied between the output voltages Vj and V ( j_i ) P , knowing that the output voltage V ( ji ) P is produced by the multiplier circuit C (H) P of the previous stage of branch B 2 of converter 10, and the output voltage Vj is that produced by the voltage multiplier circuit CMj of the corresponding stage of branch Bi of converter 10.
- each inverter circuit l ip is controlled by the output signal Vj P from the voltage multiplier circuit CMj P to produce the output signal V ⁇ .
- the multiplexer circuit MX which forms the output stage of the converter 10 can be produced according to one of the two examples illustrated in FIGS. 7 and 8.
- This operation can be divided into two phases, namely: a first phase corresponding to the charge of the capacitor from the first stage, and a second phase corresponding to the transfer of the charges stored on the capacitor during the first phase to the next stage.
- stage i of the branch B- ⁇ comprising the voltage multiplier circuit CMj and its control circuit CCj is in the first operating phase
- stage i of the branch B 2 comprising the voltage multiplier circuit CMj P and its control circuit CCj P is then in the second operating phase
- the phase switching is controlled by the clock signals ⁇ i and ⁇ 2 on the one hand, and the phase of a stage is changed with each new clock half-cycle on the other hand, that is that is to say that if the stage i of the branch B 2 is in the first operating phase, it will pass in the second operating phase to the next half clock cycle, as illustrated in the timing diagrams of FIGS. 11a to 11d, in particular those of FIGS. 11 a and 11 b.
- the first operating phase corresponds to the charge of the capacitor Cj or C ip of the stage i of each branch Bi and B 2 , with i varying from 2 to N.
- the voltage on the positive electrode of the capacitor Cj (branch Bi) or Cj P (branch B 2 ) is charged, through the switch Kj (branch Bi) or Kj p (branch B 2 ) which is in the on state, at the voltage Vj_ ⁇ (capacitor Cj) or at the voltage V (n) P (capacitor Cj P ), these voltages being equal to iV dd -
- the state of the switch Kj (branch Bi ) and K ip (branch B 2 ) is controlled by a voltage V C j (branch Bi) and V ⁇ (branch B 2 ), these voltages equal to (i + 1) V dd being supplied by the inverter lj (branch B ⁇ or lj P (branch B 2 ) which is supplied between the voltages V ip (equal to (i + 1) V dd ) and Vu (equal to iVdd) for the branch Bi, and Vj (equal to
- the second operating phase corresponds to the stacking on the supply voltage Vdd of the capacitor Cj or Cj P of the stage i of each branch B ⁇ and B 2 with i varying from 2 to N.
- Vdd the voltage on the positive electrode Vj (Vj P ) of the capacitor Cj (Cj P ) is boosted by Vdd thus raising this voltage to (i + 1) Vdd.
- the switch Kj (Kj P ) is blocked during the second phase and controlled by a voltage V C j (V ⁇ ) equal to (i-1) Vdd and supplied by the inverter lj (lj P ), as illustrated in Figures 11e and 11d respectively associated with Figures 11a and 11b.
- the inverter lj is supplied between Vj P of value iVdd and Vj. ⁇ of value (i-1) Vdd, while the inverter lj P is supplied between Vj of value iVdd and V (H) P of value (i- 1) Vdd.
- the two operating phases also concern the clock booster CB.
- the elements of the branch Bi comprising the capacitor Ci associated with the transistor Mi are in the first phase then the elements of the branch B 2 comprising the capacitor C 1p associated with the transistor M ⁇ p are in the second phase and then alternately.
- the second phase corresponds to the stacking of the capacitor Ci or C- ⁇ p on the clock signal ⁇ j at the high level (Vdd), which produces on V- t or V ⁇ p a voltage of 2Vdd as illustrated by the Figures 11a and 11b.
- a voltage / voltage converter according to the invention with only two voltage multiplier stages is sufficient to produce the programming voltage.
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Abstract
Description
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/522,738 US7266002B2 (en) | 2002-07-30 | 2003-07-25 | Voltage-voltage converter for integrated circuits |
AU2003269059A AU2003269059A1 (en) | 2002-07-30 | 2003-07-25 | Voltage-voltage converter for integrated circuits |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0209653A FR2843207B1 (fr) | 2002-07-30 | 2002-07-30 | Convertisseur tension/tension a circuits integres. |
FR02/09653 | 2002-07-30 |
Publications (2)
Publication Number | Publication Date |
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WO2004013949A2 true WO2004013949A2 (fr) | 2004-02-12 |
WO2004013949A3 WO2004013949A3 (fr) | 2004-04-08 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/FR2003/002351 WO2004013949A2 (fr) | 2002-07-30 | 2003-07-25 | Convertisseur tension/tension pour circuits integres. |
Country Status (4)
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US (1) | US7266002B2 (fr) |
AU (1) | AU2003269059A1 (fr) |
FR (1) | FR2843207B1 (fr) |
WO (1) | WO2004013949A2 (fr) |
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KR20100138146A (ko) * | 2009-06-24 | 2010-12-31 | 삼성전자주식회사 | 고효율의 차지 펌프 |
EP2378648A1 (fr) * | 2010-04-19 | 2011-10-19 | Nxp B.V. | Circuit de pompe de charge avec réduction du bruit des pics de courant |
US10008817B2 (en) * | 2011-03-24 | 2018-06-26 | Correlated Magnetics Research, Llc | Electrical adapter system |
US8702437B2 (en) * | 2011-03-24 | 2014-04-22 | Correlated Magnetics Research, Llc | Electrical adapter system |
JP2013114711A (ja) * | 2011-11-28 | 2013-06-10 | Toshiba Corp | 電圧生成回路 |
US8975942B2 (en) | 2012-03-01 | 2015-03-10 | Analog Devices, Inc. | System for a clock shifter circuit |
US9225253B2 (en) * | 2012-10-23 | 2015-12-29 | Microchip Technology Inc. | High voltage switching linear amplifier and method therefor |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2002043232A2 (fr) * | 2000-11-21 | 2002-05-30 | Mosaid Technologies Incorporated | Alimentation a pompe de charge |
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FR2762457B1 (fr) * | 1997-04-16 | 1999-05-28 | Sgs Thomson Microelectronics | Circuit generateur de tension du type pompe de charge |
KR20040047173A (ko) * | 2002-11-29 | 2004-06-05 | 주식회사 하이닉스반도체 | 노이즈를 감소시킨 전압 발생장치 |
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2002
- 2002-07-30 FR FR0209653A patent/FR2843207B1/fr not_active Expired - Fee Related
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2003
- 2003-07-25 WO PCT/FR2003/002351 patent/WO2004013949A2/fr not_active Application Discontinuation
- 2003-07-25 US US10/522,738 patent/US7266002B2/en not_active Expired - Fee Related
- 2003-07-25 AU AU2003269059A patent/AU2003269059A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002043232A2 (fr) * | 2000-11-21 | 2002-05-30 | Mosaid Technologies Incorporated | Alimentation a pompe de charge |
Non-Patent Citations (1)
Title |
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NAKAGOME ET AL: "An experimental 1.5 V 64-Mb DRAM" IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 26, no. 4, avril 1991 (1991-04), pages 465-472, XP002241539 cité dans la demande * |
Also Published As
Publication number | Publication date |
---|---|
US20060105586A1 (en) | 2006-05-18 |
FR2843207A1 (fr) | 2004-02-06 |
US7266002B2 (en) | 2007-09-04 |
WO2004013949A3 (fr) | 2004-04-08 |
FR2843207B1 (fr) | 2005-03-04 |
AU2003269059A8 (en) | 2004-02-23 |
AU2003269059A1 (en) | 2004-02-23 |
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