WO2004010488A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2004010488A1 WO2004010488A1 PCT/JP2003/008982 JP0308982W WO2004010488A1 WO 2004010488 A1 WO2004010488 A1 WO 2004010488A1 JP 0308982 W JP0308982 W JP 0308982W WO 2004010488 A1 WO2004010488 A1 WO 2004010488A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 230000004888 barrier function Effects 0.000 claims abstract description 221
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 26
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
- H01L29/7785—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer
Definitions
- the present invention relates to a semiconductor device applied to a power amplifier and the like.
- Recent requirements for transmitting power amplifiers for mobile communication mobile terminals include low distortion and high efficiency operation and single positive power supply operation.
- high-efficiency operation is the output power P.
- ut the input power P in the difference between the DC input power P de ratio in definition is the power added efficiency of the (Power Added E f ⁇ ci ency ;. It had been less PAE) means the operation of enhanced.
- ⁇ is an important performance index because the larger the PAE, the lower the power consumption of the mobile terminal.
- CDMA code division multiple access
- WCDMA code division multiple access
- the single positive power supply operation uses the conventional depletion type.
- HBT Heterojunction Bipolar Transistor
- HEMT High Electron Mobility Transistor
- HIG FET Heterostructure Insulated-Gate FET
- HFET also enables the realization of high-performance switches, and has the advantage of integrating power amplifiers and switches. -By the way, in order to realize single positive power supply operation with HFET and eliminate the need for negative power supply generation circuit and drain switch, complete enhancement type
- the complete enhancement means that the drain leakage at the time of OFF is sufficiently small, that is, when a voltage is applied between the source and the drain while the voltage between the gate and the source is kept at 0, the source and the drain are not changed. Since the current flowing between them is sufficiently small, this means an enhancement-type operation in which the drain switch can be made unnecessary, and a high threshold voltage Vth of about 0.5 V or more is generally required.
- the first problem is that the source resistance and on-resistance R are affected by the surface depletion.
- Rukoto to increase n is a result of V lh is higher in the second, the difference between the forward current elevation rising voltage Vf and V th of the gate 'source is that shrink, eventually, a low distortion and high efficiency characteristics It is very difficult to obtain.
- An example of the HFET that can easily realize the full enhancement type operation is a J PHEMT (Junction Pseudomorphic HEMT) structure as disclosed in Japanese Patent Application No. 10-258989.
- Fig. 7 shows an example of the configuration of such a conventional J PHEMT.
- this semiconductor device for example, on one surface of a substrate 1 made of a semi-insulating single crystal GaAs, for example, u—Ga As (u— A second barrier layer 3 composed of A 1 GaAs having an A 1 composition ratio of about 20%, and an In composition ratio of 20 through a buffer layer 2 composed of A channel layer 4 made of about 1% InGaAs and a first barrier layer 5 made of about 1% A1GaAs having a composition ratio of about 20% are sequentially laminated.
- u—Ga As u—
- a second barrier layer 3 composed of A 1 GaAs having an A 1 composition ratio of about 20%, and an In composition ratio of 20 through a buffer layer 2 composed of A channel layer 4 made of about 1% InGaAs and a first barrier layer 5 made of about 1% A1GaAs having a composition ratio of about 20% are sequentially laminated.
- the first barrier layer 5 includes a region 5 a in which n-type impurities are added at a high concentration, a region 5 b in which impurities are not intentionally added, and a gate electrode 9 containing a high concentration of p-type impurities.
- the second barrier layer 3 has a region 3 a to which n-type impurities are added at a high concentration and an impurity The region 3b has no added region.
- the p-type conductive region 5c is generally formed by diffusion of Zn.
- An insulating film 6 is formed on the surface of the first barrier layer 5 opposite to the substrate 1.
- the insulating film 6 is provided with a plurality of openings, and the first barrier layer 5 in these openings is formed.
- a source electrode 7, a drain electrode 8, and a gate electrode 9 are formed thereon.
- the gate electrode 9 forms a p-type ohmic contact with the first barrier layer 5.
- the channel layer 4 serves as a current path between the source electrode 7 and the drain electrode 8. It is shown in Fig. 7. However, a cap layer doped with n-type impurity at a low concentration may be interposed between the source electrode 7 and the drain electrode 8 and the first barrier layer 5 in some cases.
- a pn junction gate is used, so a built-in voltage can be obtained, and a higher voltage is applied to the gate compared to a normal Schottky gate type HFET. can do. That is, the forward rising voltage Vf between the gate and the source can be increased.
- Vi is defined as a voltage at which the forward current between the gate and the source shows a predetermined value.
- the p-type conductive region 5c containing a high concentration of p-type impurities is embedded in the first barrier layer 5, so that the surface depletion occurs even in the enhancement type in which Vth is positive. It is convenient that the source resistance does not increase due to the formation.
- J PHEMT shown in FIG. 7 has a very advantageous structure for performing the enhancement-type operation, but is not yet sufficient for realizing the above-mentioned complete enhancement-type operation. There is not enough.
- J PHEMT in Fig. 7 has a Vf of about 1.2 V, which is larger than that of a normal Schottky-type HFET or J-FET, and there is no problem if only enhancement-type operation is performed.
- a V th of about 0.5 V or more is required, and in consideration of manufacturing variations, satisfactory characteristics must be obtained even at a higher V th .
- V th increases, the difference between V lh and Vf decreases even in the case of a pn junction gate, so that the PAE characteristics under low distortion conditions deteriorate.
- the present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor device which is capable of performing a full enhancement type operation as a power transistor and has excellent low distortion and high efficiency characteristics. Disclosure of the invention
- the present invention (1) provides a source electrode, a drain electrode, a gate electrode provided between the source electrode and the drain electrode, and a channel made of a semiconductor serving as a current path between the source electrode and the drain electrode.
- a first barrier layer made of a semiconductor having a P-type conductive region doped with a high concentration of p-type impurities corresponding to a gate electrode, and a first barrier layer sandwiching a channel layer.
- a second barrier layer which is provided on the opposite side of the barrier layer and has a smaller electron affinity than the channel layer and is provided between the first barrier layer and the channel layer, and has a lower electron affinity than the channel layer;
- a third barrier layer composed of a semiconductor, wherein the electron affinity of the first barrier layer is ⁇ , the band gap is E gl , the electron affinity of the third barrier layer is ⁇ 3 , and the band gap is Eg 3 Then, the following equation
- the gate forward direction
- the barrier height ⁇ for the hole related to the current rise voltage Vf increases, and Vf can be increased.
- the semiconductor material of the first barrier layer 11 and the third barrier layer 12 is, for example, a group III element of Ga, Al, or In.
- III-V group compound semiconductors containing at least one of them and containing at least one of As and P as V group elements can be used.
- GaAs or InGaP or InGaP having an A1 composition ratio of 50% or less can be used for the first barrier layer 11.
- the third barrier layer 12 includes InGaP and A1GaAs with an A1 composition ratio of 50% or more, and AlInGaP and GalnAsP. The original compound can also be used.
- InGaAs or GaAs is used for the channel layer.
- the thickness of the third barrier layer is preferably equal to or less than 20 nm in order to obtain a desired threshold voltage Vth corresponding to the enhancement type operation.
- the p-type conductive region in the first barrier layer is formed by diffusion of a p-type impurity, it is desirable that p-type impurities do not enter the third barrier layer as much as possible from the viewpoint of controllability of diffusion.
- a semiconductor layer containing only one-tenth or less of the maximum impurity concentration in the p-type conductive region in the portion near the third barrier layer in the first barrier layer Is preferably present in a thickness of, for example, 5 nm or more.
- the present invention (2) is the semiconductor device according to the present invention (1), further comprising a fourth barrier layer made of a semiconductor having a smaller electron affinity than the channel layer between the third barrier layer and the channel layer. It is characterized by the following.
- the fourth barrier layer has a good connection with the channel layer. This problem can be avoided by using a semiconductor material capable of forming a simple interface.
- a 1 GaAs or GaAs can be used as a semiconductor material of the fourth barrier layer. Further, from the relation of V th , it is preferable that the fourth barrier layer is formed so that the sum of the thicknesses of the fourth barrier layer and the third barrier layer is 20 nm or less.
- the present invention (3) is the semiconductor device according to the present invention (1), wherein a high-concentration P-type impurity having a smaller band gap than the first barrier layer is added between the first barrier layer and the gate electrode.
- a fifth barrier layer made of a semiconductor having a formed P-type conductive region.
- the height of the Schottky barrier between the semiconductor in contact with the gate metal and the gate metal is reduced, and the ohmic contact resistance can be reduced.
- GaAs can be used as the semiconductor material of the fifth barrier layer.
- the present invention (4) provides the semiconductor device according to the present invention (1), wherein the diffusion speed of Zn is lower than that of the first barrier layer between the first barrier layer and the third barrier layer.
- a sixth barrier layer is provided.
- the present invention (4) when the p-type conductive region of the first barrier layer is formed by diffusion of Zn, the diffusion of Zn added to the first barrier layer is stopped by the sixth barrier layer. And control of Zn diffusion becomes easy.
- GaAs or A1 GaAs can be used as the semiconductor material of the sixth barrier layer.
- the sixth barrier layer is preferably formed so that the sum of the thicknesses of the sixth barrier layer and the third barrier layer is 25 nm or less.
- FIG. 1 is a sectional view showing a first embodiment of a semiconductor device of the present invention.
- FIG. 2 is a band diagram along the V-axis in FIG.
- FIG. 3 is a sectional view showing a second embodiment of the semiconductor device of the present invention.
- FIG. 4 is a sectional view showing a third embodiment of the semiconductor device of the present invention.
- FIG. 5 is a cross-sectional view showing a fourth embodiment of the semiconductor device of the present invention.
- FIG. 6 is a sectional view showing a fifth embodiment of the semiconductor device of the present invention.
- FIG. 7 is a cross-sectional view showing a conventional J PHEMT which is a conventional semiconductor device.
- Fig. 8 is the? It is a band diagram along 7 axes.
- FIG. 7 is a band diagram along seven axes, showing a state where no voltage is applied to the gate.
- Ec is the energy at the bottom of the conduction band
- Ev is the energy at the top of the valence band
- Ef is the Fermi level
- ⁇ is the barrier height for holes.
- Fig. 8 is based on the calculation results for a particular parameter, and a different band diagram is obtained for different parameters, but it is enough to grasp the following qualitative trends.
- One way to increase ⁇ is to increase the band gap by increasing the A 1 composition ratio of the first barrier layer.
- the A1 composition ratio is increased from about 20% to about 30 to 40%, the source contact resistance generally increases because the electron affinity decreases.
- the composition of A 1 is increased, the diffusion rate of Zn increases, which causes a problem in the controllability of diffusion.
- a first embodiment shown in FIG. 1 can be considered as a structure that can increase ⁇ without causing the above-described problem.
- Fig. 2 shows the band diagram along the? 7 axis in Fig. 1.
- the difference from FIGS. 7 and 8 is that a third barrier layer 12 made of a semiconductor is located between the first barrier layer 11 made of a semiconductor including the ⁇ -type conductive region 11 c and the channel layer 4.
- the third barrier layer 12 has a larger band gap than the first barrier layer 11, and the first barrier layer 11 and the third barrier layer 11 have a larger band gap.
- the valence band edge energy difference ⁇ 13 is larger than the conduction band edge energy difference A Ec 13 of layer 12 .
- Vf can be increased, but the electron affinity of the third barrier layer 12 does not decrease so much, and the conduction band edge energy difference AEc 13 of the first and third barrier layers also does not so much. Since it does not increase, it is possible to prevent the ohmic contact resistance of the source from increasing. Further, in this structure, the Zn diffusion layer of the p-type conductive region 11 c is formed up to the third barrier layer 12. The diffusion speed of Zn does not become a problem because the structure can not be achieved by the above method.
- the relationship between the first barrier layer 11 and the third barrier layer 12 is such that the band gap is increased by increasing the electron affinity of the first barrier layer 11 1 and the electron affinity of the third barrier layer 12 ⁇ 3 .
- the band gap is Eg 3 , it is expressed by the following equation.
- one side of a substrate 1 made of a semi-insulating single crystal GaAs is not intentionally doped with impurities, for example, u—GaAs, u—AlGaA. or a second barrier layer 3 of A 1 G a As with a composition ratio of A 1 of about 20%, and an I n G a of about 20% of a composition ratio of In through a buffer layer 2 composed of a multilayer film thereof.
- a channel layer 4 composed of As, a third barrier layer 12 composed of InGaP, and a first barrier layer 11 composed of A1GaAs having a composition ratio of A1 of about 20% are sequentially laminated. Have been.
- the first barrier layer 11 and the third barrier layer 12 include at least one of Group III elements Ga, A1, and In.
- group IV compound semiconductors that include at least one of As and P as group V elements are conceivable.
- the first barrier layer 11 can be made of GaAs or InGaP with a composition ratio of GaAs or A1 of 50% or less.
- the third barrier layer 12 includes quaternary elements such as InGaP and A1GaAs with an A1 composition ratio of 50% or more, AlInGaP and GalInAsP.
- Compounds can also be used Wear.
- A1GaAs having an A1 composition ratio of 50% or more the electron affinity of the conduction band with respect to the X band increases, so that the relationship of the formula (1) is satisfied.
- GaAs is used for the channel layer in addition to InGaAs.
- the first barrier layer 11 includes a P-type conductive region 11 c containing a high-concentration P-type impurity and provided corresponding to the gate electrode 9, and the other region includes a low-impurity-concentration region 1. 1 b.
- Zn is used as the p-type impurity
- the p-type conductive region 11c is formed by diffusion of Zn.
- the thickness of the first barrier layer 11 is 100 nm. It may be thicker or thinner, but if it is too thick, it will be difficult to reduce the source contact resistance, and if it is too thin, it will be difficult to control Zn diffusion, so it is preferably about 70 to 100 nm.
- the thickness of the ⁇ -type conductive region 11 c is difficult to define accurately when the P-type impurity is added by Zn diffusion, but the impurity concentration of the low impurity concentration region 11 b is difficult. If the value is set to one-tenth or less of the maximum concentration of the p-type impurity contained in the p-type conductive region 11c, it is about 90 nm here. In this case, a low-impurity-concentration region 11b exists about 10 nm between the third barrier layer 12 and the p-type conductive region 11c.
- the thickness of the p-type conductive region 11 c must be appropriately adjusted according to the desired V th. It is preferable that the thickness of 1 lb of the impurity concentration region be 5 nm or more.
- the third barrier layer 12 includes, for example, an n-type impurity high-concentration addition region 12 a in which an n-type impurity made of Si is added at a high concentration, and a low impurity concentration in which no impurity is intentionally added. It consists of area 1 2b.
- the thickness of the n-type impurity-doped region 12a is 4 nm
- the low-impurity-concentration region 12b between the n-type impurity-doped region 12a and the first barrier layer 11 is 4 nm.
- the thickness of 3 nm, the thickness of the low impurity concentration region 12 b between the n-type heavily doped region 12 a and the channel layer 4 is 3 nm, and the total thickness of the third barrier layer 12 is 3 nm. And 1 O nm.
- the third barrier layer 12 can be made slightly thicker or thinner, but if it is too thick, the p-type conductive region is obtained in order to obtain the desired Vth corresponding to the enhancement type operation. In the third barrier layer 12, there is a possibility that diffusion may be difficult to control. Therefore, the thickness is preferably about 20 nm or less.
- the thickness of the n-type impurity-doped region 12a be as small as possible within a range where a desired value is obtained as the sheet concentration of the n-type impurity and there is no difficulty in manufacturing such as reproducibility. . Therefore, the thickness is preferably several nm or less, and may be one atomic layer. This is because, in the channel layer between the source and the gate, the product of the mobility and the carrier concentration can be maximized, so that the source resistance can be reduced. In the gate region, the barrier layer can be formed without deteriorating the mobility. This is because the parallel conduction through which the carrier flows can be suppressed.
- the thickness of the low impurity concentration region 12b on the channel layer 4 side is desirably 2 nm or more. This is to suppress the deterioration of the electron mobility of the channel layer 4.
- the sheet impurity concentration of the n-type impurity high-concentration addition region 12a was set to 2 ⁇ 10 12 / cm ⁇ 2 . If the amount is too small, the source resistance becomes high. Therefore, 1 ⁇ 10 12 pieces / cm— 2 units are desirable.
- the second barrier layer 3 also includes, for example, an n-type impurity high-concentration addition region 3a in which an n-type impurity made of Si is added at a high concentration and a low impurity concentration region 3b in which no impurity is intentionally added. Consists of Here, the sheet impurity concentration of the n-type impurity-doped region 3.a was set to 1 ⁇ 10 12 cm ⁇ 2 .
- the thickness of the channel layer 4 was set to about 15 nm for InGaAs with an In composition ratio of about 20%.
- the film thickness can be freely changed.
- the insulating film 6, the source electrode 7, the drain electrode 8, and the gate electrode 9 are formed in the same manner as the structure shown in FIG.
- Si 3 N 4 can be used for the insulating film 6.
- Ti / PtZAu can be used for the source electrode 7, the drain electrode 8, and the gate electrode 9, for example.
- V f can be further increased, so that the complete enhancement operation is facilitated and the power amplifier is configured.
- a negative power supply generating circuit and a drain switch are not required, and the power amplifier can be reduced in size and cost.
- V f it is possible to increase the power added efficiency under a constant low distortion condition.
- the first embodiment is a basic form according to the present invention, and is provided between the third barrier layer and the channel layer, between the first barrier layer and the gate electrode 9, between the first barrier layer and the third barrier layer. In between, another layer can be inserted, thereby adding a new effect.
- the third barrier layer 12 has an n-type impurity high-concentration addition region 12 a in which an n-type impurity is added at a high concentration, but the third barrier layer 12
- the third barrier layer 12 Depending on the type of material used for the semiconductor device, there may be a case where n-type impurities cannot be added at a high concentration, or a case where a good interface between the third barrier layer 12 and the channel layer 4 is not easily formed. In such a case, it is convenient to insert a fourth barrier layer between the third barrier layer and the channel layer 4.
- FIG. 3 shows a case where n-type impurities are added at a high concentration to the third barrier layer (second embodiment), and FIG.
- FIG. 4 shows a case where n-type impurities are added at a high concentration to the fourth barrier layer. This is the case (third embodiment). If it is difficult to add an n-type impurity to the third barrier layer at a high concentration, it is necessary to make it as shown in FIG. 4.If only the interface between the third barrier layer and the channel layer 4 becomes a problem, Either of the configurations shown in FIGS. 3 and 4 may be used. (Second embodiment)
- a second embodiment of the semiconductor device of the present invention will be described with reference to FIG.
- a fourth barrier layer 14 to which an impurity is not intentionally added is provided between the third barrier layer 13 and the channel layer 4. Is provided.
- the third barrier layer 13 is made of a material that satisfies the relationship expressed by the following expression (1) with the first barrier layer 11, similarly to the third barrier layer 12 of the first embodiment.
- the fourth barrier layer 14 is made of a material that can form a good interface with the channel layer 4 and is not intentionally added with impurities.
- the A 1 composition ratio is about 20% or less.
- A1GaAs or GaAs can be used.
- the thickness of the fourth barrier layer 14 is desirably about 5 nm or less.
- the sum of the thicknesses of the third barrier layer 13 and the fourth barrier layer 14 is desirably about 20 nm or less.
- the other parts are formed in the same manner as in the first embodiment.
- the third barrier layer 15 has no region to which an n-type impurity is added at a high concentration, and the third barrier layer 15 and the channel A fourth barrier layer 16 having an n-type impurity-doped region 16 a is provided between the fourth barrier layer 16 and the layer 4.
- the third barrier layer 15 is made of a material that satisfies the relationship of the formula (1) with the first barrier layer 11 similarly to the third barrier layer 12 of the first embodiment. Does not intentionally add n-type impurities.
- the fourth barrier layer 16 is made of a material capable of forming a good interface with the channel layer 4 as in the case of the second embodiment.
- A1 GaAs or GaAs of about 20% or less can be used, but an n-type impurity, for example, an n-type impurity high-concentration addition region 16 in which Si is added at a high concentration can be used. a, and a low impurity concentration region 16 b to which no impurity is intentionally added.
- the thickness of the n-type impurity high concentration added region 16a, the sheet concentration of the n-type impurity, and the thickness of the low impurity concentration region 16b on the channel layer 4 side are the same as those in the first embodiment.
- the description similar to that of the third barrier layer 12 applies, but the sum of the third barrier layer 15 and the fourth barrier layer 16 is preferably about 20 nm or less. The other parts are formed in the same manner as in the first embodiment.
- the third barrier layer 15 satisfies the relationship of the first barrier layer 11 and the equation (1).
- a semiconductor material it is possible to apply a material that does not easily form a good interface with the channel layer 4 or a material that is difficult to add a high concentration of n-type impurities.
- the first barrier layer 11 is changed to a two-layer structure of a first barrier layer 17 and a fifth barrier layer 18.
- a fifth barrier layer 18 made of a semiconductor having a smaller sum of electron affinity and band gap than the first barrier layer 17 is provided between the first barrier layer 17 and the gate electrode 9.
- the fifth barrier layer 18 for example, GaAs can be used.
- a p-type impurity here, Zn
- the thickness of the fifth barrier layer 18 can be, for example, about 50 nm.
- the other parts are the same as in the first embodiment.
- the fifth barrier layer having a smaller sum of the electron affinity and the band gap than the first barrier layer is provided between the gate electrode and the first barrier layer.
- a fifth embodiment of the semiconductor device of the present invention will be described with reference to FIG.
- the first barrier layer 11 and the sixth barrier layer 19 are different from each other in order to enhance the controllability of Zn diffusion.
- the structure is changed to a two-layer structure of the barrier layer 20, and between the first barrier layer 20 and the third barrier layer 12, the diffusion speed of Zn is lower than that of the first barrier layer 20.
- a sixth barrier layer 19 is provided.
- a 1 GaAs or InGaP is used for the first barrier layer 20, and GaAs or A 1 GaAs is used for the sixth barrier layer 19. be able to.
- the sum of the thicknesses of the sixth barrier layer 19 and the third barrier layer 12 is desirably about 25 nm or less. It is also desirable that the sixth barrier layer has a thickness of about 5 nm or more so that 11 does not penetrate the sixth barrier layer 19. The other parts are the same as in the first embodiment.
- the p-type conductive region 20 c of the first barrier layer 20 provided corresponding to the gate electrode 9 is formed by diffusion of Zn.
- the diffusion of Zn added to the first barrier layer 20 can be stopped by the sixth barrier layer 19, and the thickness of the Zn diffusion layer can be easily controlled.
- the semiconductor device of the present invention is not limited to the above embodiment, and various configurations in which the above embodiment is mixed can be considered.
- the fourth to sixth barrier layers only one of them may exist, two of them may exist, or all may exist.
- the third barrier layer having the relationship of the formula (1) between the first barrier layer and the channel layer by providing the third barrier layer having the relationship of the formula (1) between the first barrier layer and the channel layer, the rise of the gate in the forward direction is achieved.
- the voltage V f can be effectively increased, a perfect enhancement type operation can be performed, and a power transistor excellent in low distortion and high efficiency can be realized.
- a power amplifier constructed using this transistor can be used as a negative power supply circuit or drain switch. Since it does not require a small size, it is small in size, low in price, and has excellent low distortion and high efficiency characteristics.
- the material of the third barrier layer can be selected without considering the interface with the channel layer. be able to.
- the ohmic contact resistance is reduced by providing the fifth barrier layer having a smaller band gap than the first barrier layer between the first barrier layer and the gate electrode. Can be achieved.
- the present invention by providing a sixth barrier layer having a lower Zn diffusion rate than the first barrier layer between the first barrier layer and the third barrier layer, The controllability of Zn diffusion forming the conductive region can be improved.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/519,877 US20060220165A1 (en) | 2002-07-19 | 2003-07-15 | Semiconductor device |
GB0501132A GB2406970B (en) | 2002-07-19 | 2003-07-15 | Semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002-210597 | 2002-07-19 | ||
JP2002210597A JP2004055788A (ja) | 2002-07-19 | 2002-07-19 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
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WO2004010488A1 true WO2004010488A1 (ja) | 2004-01-29 |
Family
ID=30767739
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/008982 WO2004010488A1 (ja) | 2002-07-19 | 2003-07-15 | 半導体装置 |
Country Status (6)
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US (1) | US20060220165A1 (ja) |
JP (1) | JP2004055788A (ja) |
CN (1) | CN1669131A (ja) |
GB (1) | GB2406970B (ja) |
TW (1) | TWI261322B (ja) |
WO (1) | WO2004010488A1 (ja) |
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JP4867137B2 (ja) * | 2004-05-31 | 2012-02-01 | 住友化学株式会社 | 化合物半導体エピタキシャル基板 |
EP1938385B1 (en) | 2005-09-07 | 2014-12-03 | Cree, Inc. | Transistors with fluorine treatment |
JP2007194588A (ja) | 2005-12-20 | 2007-08-02 | Sony Corp | 電界効果トランジスタ及びこの電界効果トランジスタを備えた半導体装置並びに半導体装置の製造方法 |
JP2007335586A (ja) * | 2006-06-14 | 2007-12-27 | Sony Corp | 半導体集積回路装置および半導体集積回路装置の製造方法 |
PL2080228T3 (pl) * | 2006-10-04 | 2021-04-19 | Leonardo S.P.A. | Urządzenie mocy pseudomorficznego tranzystora o wysokiej ruchliwości elektronów (phemt) z zasilaniem jednonapięciowym i sposób jego wytwarzania |
US8203376B2 (en) * | 2006-11-20 | 2012-06-19 | Panasonic Corporation | Semiconductor device and method for driving the same |
US7573080B1 (en) * | 2008-06-20 | 2009-08-11 | Visual Photonics Epitaxy Co., Ltd. | Transient suppression semiconductor device |
JP2010056250A (ja) * | 2008-08-27 | 2010-03-11 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
TWI514567B (zh) * | 2009-04-08 | 2015-12-21 | Efficient Power Conversion Corp | 逆擴散抑制結構 |
KR102065115B1 (ko) * | 2010-11-05 | 2020-01-13 | 삼성전자주식회사 | E-모드를 갖는 고 전자 이동도 트랜지스터 및 그 제조방법 |
JP5810518B2 (ja) | 2010-12-03 | 2015-11-11 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
JP2013048212A (ja) * | 2011-07-28 | 2013-03-07 | Sony Corp | 半導体装置および半導体装置の製造方法 |
JP2013074179A (ja) * | 2011-09-28 | 2013-04-22 | Fujitsu Ltd | 化合物半導体装置及びその製造方法 |
JP5900315B2 (ja) | 2012-02-16 | 2016-04-06 | ソニー株式会社 | 半導体装置および半導体装置の製造方法 |
US9608085B2 (en) * | 2012-10-01 | 2017-03-28 | Cree, Inc. | Predisposed high electron mobility transistor |
US9425276B2 (en) * | 2013-01-21 | 2016-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | High electron mobility transistors |
US9231094B2 (en) | 2013-05-21 | 2016-01-05 | Globalfoundries Inc. | Elemental semiconductor material contact for high electron mobility transistor |
US9276077B2 (en) * | 2013-05-21 | 2016-03-01 | Globalfoundries Inc. | Contact metallurgy for self-aligned high electron mobility transistor |
TWI643337B (zh) * | 2017-10-17 | 2018-12-01 | 全新光電科技股份有限公司 | 具有能隙漸變的電洞阻隔層之異質接面雙極性電晶體結構 |
CN111276538B (zh) * | 2018-12-04 | 2023-03-14 | 世界先进积体电路股份有限公司 | 半导体装置及其制造方法 |
US10644128B1 (en) * | 2019-01-07 | 2020-05-05 | Vanguard International Semiconductor Corporation | Semiconductor devices with reduced channel resistance and methods for fabricating the same |
WO2022109974A1 (en) * | 2020-11-27 | 2022-06-02 | Innoscience (suzhou) Semiconductor Co., Ltd. | Semiconductor device and manufacturing method thereof |
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- 2003-07-15 GB GB0501132A patent/GB2406970B/en not_active Expired - Fee Related
- 2003-07-15 CN CN03817224.0A patent/CN1669131A/zh active Pending
- 2003-07-15 WO PCT/JP2003/008982 patent/WO2004010488A1/ja active Application Filing
- 2003-07-15 US US10/519,877 patent/US20060220165A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
GB2406970B (en) | 2005-12-07 |
TWI261322B (en) | 2006-09-01 |
US20060220165A1 (en) | 2006-10-05 |
TW200410342A (en) | 2004-06-16 |
GB2406970A (en) | 2005-04-13 |
JP2004055788A (ja) | 2004-02-19 |
GB0501132D0 (en) | 2005-02-23 |
CN1669131A (zh) | 2005-09-14 |
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