WO2004001848A1 - Fabrication de circuits electroniques - Google Patents

Fabrication de circuits electroniques Download PDF

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Publication number
WO2004001848A1
WO2004001848A1 PCT/IE2003/000094 IE0300094W WO2004001848A1 WO 2004001848 A1 WO2004001848 A1 WO 2004001848A1 IE 0300094 W IE0300094 W IE 0300094W WO 2004001848 A1 WO2004001848 A1 WO 2004001848A1
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WO
WIPO (PCT)
Prior art keywords
layer
component
components
internal material
internal
Prior art date
Application number
PCT/IE2003/000094
Other languages
English (en)
Inventor
Sten Bjorsell
Original Assignee
Sten Bjorsell
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sten Bjorsell filed Critical Sten Bjorsell
Priority to EP03760849A priority Critical patent/EP1514307A1/fr
Priority to AU2003253227A priority patent/AU2003253227A1/en
Priority claimed from IE2003/0455A external-priority patent/IE83585B1/en
Publication of WO2004001848A1 publication Critical patent/WO2004001848A1/fr
Priority to US11/012,196 priority patent/US7485489B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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Definitions

  • the invention relates to manufacture of circuits having passive components such as resistors and capacitors and/or active components such as transistors and integrated circuits either packaged or unpackaged (die form).
  • US Pat. No. 6,400,573 Bl (Texas Instruments Inc.) pertains to packaging of semiconductor components and more particularly to packaging of multiple semiconductor die in a laminated substrate with an interconnect layer formed in a* deposited overlay structure. Cavities of specific depths are made in the upper surface of a polymer substrate to accommodate integrated circuit chips such that the to ' surface of the chip and the top surface of the substrate are copla ⁇ ar.
  • a layer of laminate film is then disposed on top of the die and substrate surfaces with yia openings. The via openings are disposed such that they expose bonding pads on the die surface.
  • a conductor pattern is disposed on the laminate film so as to extend between at least some of the via openings and provide electrical connections to the bonding pads.
  • HDI high density interconnect
  • US Pat. No. 6,403,881 Bl (Elliot Industries Ltd) relates to an electronic component package assembly and method of manufacturing the same.
  • An electronic component package assembly is produced in the form of a panel.
  • a planar base substrate, a frame layer made from laminate material with a number of cavities is attached to the planar base substrate.
  • a component is attached to the planar base substrate in each of the cavities and a lid fits over the cavity.
  • the component in the cavity may or may not be enclosed in a protective material.
  • US Pat. No. 6,344,688 Bl (Singapore Institute of Microelectronics) relates to a multi- chip package for active and/or passive devices.
  • the devices are joined to a flexible tape which is then joined to a substrate having a cavity such that the devices are within the cavity.
  • the flexible tape has a number of interconnect pads and test pads. These are connected to the chips by electrodes or within the flexible tape.
  • US Pat. No. 5,564,181 (Draper Laboratory Inc.) relates to a laminated substrate assembly chips-first ultichip module and a method of making it.
  • Electronic components are thinned to a predetermined thickness and are mounted on a flat internal layer in precise positions.
  • a mechanical spacer layer having precisely- located apertures corresponding to the component locations is applied. Spaces between the mechanical spacer layer and components may be filled during laminations by adhesive for securing the mechanical spacer layer to the bottom and top layers.
  • a cover layer is bonded over the mechanical layer and the tops of the components. Disadvantages of this method are that the chips must be accurately thinned and the apertures made to precisely fit the chips. Also, it appears that voids may remain around components if there is insufficient excess adhesive.
  • EP 0611,129 Bl also describes a process in which components of differing shapes and thicknesses are placed on a substrate. A mould form is placed around the components and the mould is filled over the components and the moulding material is cured at 300°C. This approach appears to allow versatility in component height difference. However, it also appears that there is little versatility m component or conductor arrangements above the components, where the moulding material has been cured.
  • JP06247726 describes a method for mounting semiconductor chips in which a chip die bonded to a board is coated on the periphery with an insulating material. Holes for wiring are then made in the insulation layer by means of a laser beam. The hole is filled with a conductor and a wiring pattern is formed on the surface of the insulation layer.
  • the invention is therefore directed towards achieving a process for embedding a component or components with:
  • a method of manufacturing a circuit comprising the steps of embedding a component between external layers and making at least one electrical connection to the component through an external layer, wherein the component is encapsulated by:
  • the component is completely encapsulated without voids and without need to provide components of a particular height.
  • Another major advantage that because the component is embedded in internal material between external layers, conventional multilayer board production equipment and techniques can be used for some of the operations.
  • the internal material is caused to flow by application of heat and external pressure on both sides.
  • the internal material comprises a resin of the type which flows under application of heat and pressure . In one embodiment, the internal material comprises reinforcing fibres.
  • the internal material is applied as one or more solid sheet having an aperture for the component.
  • the depth of the sheet or sheets is such as to leave a cavity over the component.
  • the layer includes a dummy aperture to provide a space for excess internal material when it flows.
  • application of the internal material and pressing takes place in a vacuum.
  • the internal material is applied as a plurality of solid sheets, one above the other.
  • the sheets have apertures to accommodate heights of all of the components.
  • a conducting layer is applied externally before or after internal material flow.
  • pressure and/ or resin depth are dynamically monitored to ensure that the internal material does not become thinner than a target minimum thickness, being greater than the depth of the deepest component.
  • the internal material is prepreg.
  • an electrical connection is made to a component terminal and a conductor land on a layer by drilling a via through said layer and an insulation layer and plating the via so that the plating inter-connects the conductor land and the component terminal.
  • a component is connected to an internal conducting layer, and the method comprises the further steps of:
  • an electrical connection is made to a component lateral lead.
  • a via is drilled through the lead.
  • the via is laser drilled.
  • the via is mechanically drilled.
  • the via is drilled by acid exposure for selective removal of insulation layer material.
  • an outer conductive laminated layer is selectively etched where vias are required and subsequent acid exposure is performed to remove underlying insulation material, remaining conductive layer acting as etch resist.
  • the method comprises the further step of back-etching the outer conductive layer.
  • the via is drilled by plasma etching.
  • the via is drilled by high pressure liquid jet machining , with or without abrasives.
  • a plurality of components are embedded in the internal material one above the other and are interconnected by a multi-layer vertical bus
  • bus interconnections are made at vias formed through the components.
  • interconnections are made at vias formed through component terminals or bonding pads to stack at least two components with total inter- component interconnection length being only the thickness of the components and intervening layers.
  • a via is drilled in a layer and a waveguide is mounted in the via to provide an optical connection to a component.
  • a layer comprises a transparent portion for emission or absorption of light or other electromagnetic radiation for signal or power exchange by a component.
  • said layer is formed to provide at least one lens.
  • the method comprises the further step of providing a heat- transfer layer thermally connected to any external or internal part of a component.
  • the layer is thermally connected by vias and/or by electrical connections.
  • the heat-transfer layer is a substrate onto which the component is placed.
  • said heat transfer layer also acts as a power plane.
  • the method comprises the further step of applying an external electromagnetic shielding layer.
  • an external layer comprises a board etched and/ or plated for interconnection of components.
  • the internal material is powder-form epoxy, and it is flowed and attached by initially applying heat and subsequently flowed by heat and pressure.
  • the invention also provides a circuit whenever produced by a method as defined above.
  • Fig 1 is a cross-sectional diagram showing part of a circuit of the invention, in which components are embedded within a multi-layer board type structure;
  • Fig. 2 is a flow diagram illustrating the production process
  • Figs. 3 to 6 are cross-sectional diagrams of different circuits produced according to the process
  • a circuit 1 has an SMT component 2 embedded within a multilayer circuit having a top foil 3 and a bottom foil 4.
  • the component 2 is connected to the remainder of the circuit by laser-drilled vias 5 and 6 which extend from the top surface, through the foil 3 and terminate at terminals at the top of the component 2.
  • a through via 7 extends fully through the circuit 1. All of the vias are laser-drilled and electro-plated using a conventional electro-plating technique.
  • the multi-layer board comprises FR4 layers 9, 11, and 12 and circuit conductors 8 and 10 on the FR4 layers 9 and 11.
  • the board is manufactured in the conventional manner for multi-layer circuit boards using FR4 prepreg and FR4 material. However, the manufacturing process also embeds the component 2 into the top layer 12.
  • a component semiconductor die
  • the process steps are described for a simple situation in which the substrate is a single layer, and only one component is illustrated.
  • a prepared copper-clad FR4 sheet 14 is provided and a die 13 is placed on it with an underfill of compatible adhesive.
  • the underfill is of the type typically used when dies are bonded to a lead frame before injection moulding to produce packaged ICs, to absorb CTE differences with low loss of thermal conductivity. Since such dies have a body of, usually, silicon, and circuitry on only one side (opposite the underfill side), electrical isolation to copper and die circuitry and hence between multiple dies can be achieved through such die bodies. However, such die bodies have a relatively high thermal conductivity, allowing excellent heat dissipation. Thinning of die bodies can also be made to further enhance thermal conductivity.
  • the sheet 14 may be selectively etched and suitably pretreated for lamination.
  • the sheets 15 have apertures through which the component 13 and other components fit freely in the X, Y, and Z directions.
  • the sheets 15 are in this embodiment Liquid Crystal Polymer (LCP) bondsheets (prepreg) available for multilayer board production.
  • LCP Liquid Crystal Polymer
  • prepreg Liquid Crystal Polymer
  • the sheets 15 are pre-machined according to a design so that the components fit through them and the depth of the aperture is greater than the thickness of the component. Components of different thicknesses can be accommodated by pre-machining the prepreg sheets according to the design. For example, at another XY location there may be apertures in only the two lowermost or uppermost sheets 15.
  • Some prepreg layers include dummy apertures to accommodate excess prepreg resin, as described below.
  • the final thickness of the compressed prepreg with all apertures exclusive of component volumes completely filled with resin is calculated at preparation stage.
  • consideration is made for its height so that a thicker (in Z) component usually is provided with a larger aperture to be filled with resin than a thinner component, providing similar overall thinning of the prepreg through resin flow into these cavities.
  • Extra apertures in the prepreg sheets are then added at suitable locations at this calculation stage to balance the average pressed thickness across the board .
  • Consideration here is given to maximum resin travel distance. Press parameters such as pressure and 'temperature increase rate' are modified to adjust optimum resin travel distance. Consideration is given to ensure that the total of resin is sufficient to fill all of the cavities without allowing its thickness to reach its minimum possible, i.e.
  • a sheet comprising a prepreg (a LCP bondsheet is one suitable prepreg material for dies, combining absence of halogens and hermetic properties) layer 16(a) and copper foil 16(b) is placed over the prepreg layers 15. This is done leaving an empty (with negligible air) cavity over each component 13.
  • the top-most sheet may, for example, alternatively be an RCC foil. Again this is widely used in the multilayer circuit industry.
  • the internal pressure is dynamically maintained so that the resin of the prepreg flows sufficiently to completely encapsulate the components irrespective of spaces around components and differing component heights.
  • the prepreg sheet dimensions and internal "dummy" apertures are such as to avoid excessive flow of excess resin outside of the external side edges and to maintain uniform layer height and component encapsulation.
  • the cured depth, d2 is greater than the maximum component thickness, dl, with a margin.
  • This is achieved, as described above, by design of the prepreg sheets and by choice of press pressure, and temperature rise and liquid resin viscosity.
  • parameters typically range from 12 to 18 bar and 2 to 4 degree/minute.
  • a lower "kiss pressure" of some 20% of full pressure before resin melt starts is usually employed during air evacuation time(15-60 minutes) as well, especially if a large percentage of area is occupied by dies to avoid mechanical deformation of remaining prepreg and following potential damage to dies.
  • Other materials have 'standard' times that usually needs to be adjusted accordingly from a standard multilayer press cycle with only prepreg and inner layers to bond.
  • Fig. 2(e) The top foil 16(b) and cured resin 16a is after lamination selectively removed (laser usually) down to points on die for connection, and these openings are electroplated to make connections to the components.
  • a via 18 is shown in Fig. 2(e).
  • More complex interconnectivity may be achieved by subsequently applying more prepreg layers and foil, pressing, and making external via connections to the (now internal) foil 16(b), equivalent to standard forming of buried micro vias.
  • the layouts for connecting tracks can be near identical for a buried die inside a pcb and the same die in a 'CSP' package attached with solder balls, without consideration for minimum solder ball pad size.
  • one or more double-sided selectively etched boards may be used to provide connecting track layers. This is particularly advantageous if the components have many connection points, potentially reducing number of lamination cycles to one. For example, there may be a number of components each having 20 x 20 bond pads, and the tracks on the external sheets connect the pads to a bus.
  • a shielding layer for example of Cu followed by Ni, may be laminated with prepreg again on the outside(s) through further press lamination above or below all components and interconnections as required.
  • This provides shielding and electromagnetic interference noise protection.
  • the hence reduced noise sensitivity may also allow lower operating voltages and higher clock speeds or reduced power consumption and generated EMI noise.
  • a thermally conductive substrate such as a sheet of thick copper may be used. This provides good heat dissipation from the components, increasing circuit life and improving reliability for most circuit designs, especially when the whole circuit side then can be directly attached to external cooling
  • a via may be drilled to act as a socket for a waveguide interconnection.
  • some layers may be transparent at some or all wavelengths to allow emission or absorption of light or other electromagnetic waves for signal or power exchange of light by components, possibly with focusing.
  • An embedding plane may be curved to provide a focusing lens.
  • An alternative to laser drilling is to use acid etching to simultaneously form vias.
  • An outer foil is etched to a via pattern, and upon acid dipping the underlying prepreg is dissolved to the desired depth.
  • the extent of dissolving of the prepreg may be greater than that of the foil etch, and so back-etching of the foil may be required to enlarge the foil via diameter to match that of the internal prepreg.
  • the acid dip technique allows all vias to be simultaneously "drilled", as opposed to the sequential laser drilling method. This leads to significantly higher efficiencies and much less use of - In ⁇
  • the components are embedded using only a variation of standard manufacturing techniques used in the multi-layer circuit industry. Also, there is no need for soldered connections to the flip chip, this being achieved by use of the platings on the layers and the vias, although the embedding as per the invention of panels with components soldered to circuitry can sometimes be a feasible option. Another advantage is that there are no need for exposed components on the outside of the multilayer board, and so the circuit may be used for harsh physical and/or electrical environments and they do not need to be physically protected by a housing.
  • the invention avoids the problems arising in standard environments of dust particles reducing electrical isolation between conductors, particularly for high-density and/ or high voltage circuits, and reduces possible terminal spacing in all cases when air is replaced by insulators of much greater strength. Furthermore, it is possible to place components on the outside surfaces of the board in the conventional manner, and/ or on additional internal layers thus achieving a desired circuit density in a versatile manner.
  • a circuit 20 has a flip chip 21 embedded in a multi-layer board having top and bottom foil layers 22 and 23 respectively and six additional conductor layers in-between.
  • Vias 24 interconnect the top surface to the flip chip 21.
  • Vias 25 interconnect the top surface to conductors on an internal foil, so that connections to the flip chip 21 are completed by a second set of vias 26.
  • a via 27 extends between the inner foil layers on both sides. The vias 26 and 27 are "buried" vias formed after a first pressing.
  • a circuit 40 has a component 41 embedded in a board having only one substrate FR4 layer 45.
  • Six layers of prepreg 46 are used to build up to the height of the component 41, and a seventh layer is placed over the top of the component 41 and the other layers.
  • a through via 44 interconnects foil layers 42 and 43.
  • the vias 44 are electrically connected to lateral leads 47 of the component 41 instead of the top surfaces of the component. This is achieved by drilling through the lead 47 and subsequently electroplating.
  • the block 41 may alternatively be a number of at least two components.
  • a through-via may be used to interconnect multiple components in the Z dimensions. This may be in a bus arrangement, allowing very high frequency connectivity.
  • the processing for connecting vias to component leads may involve back etching of epoxy to obtain clean connections, just like in standard multilayer pcb fabrication.
  • a circuit 60 has an embedded component 61 over a set of cooling vias 64 extending through an FR4 layer 63.
  • Layers of prepreg 65 are placed over the layer 63 in which all but the topmost prepreg sheet 66 has an aperture for accommodating the components 61.
  • Such cooling vias can also be drilled, usually with a drill bit with a flat tip with a drill machine equipped with depth control, into the packaged chip to the copper plate the die is attached to, from the non-die side, to provide cooling path(s) through subsequent copper plating.
  • a circuit 80 is produced in a symmetrical manner about an XY plane through its centre.
  • the circuit is achieved in two placement cycles followed by a pressing cycle and a drilling and plating cycle on both external sides.
  • a second press and drilling and plating cycle is required for a buried micro via 85.
  • the items of Fig. 6 are:
  • 83 FR4 layers on to which 81 were placed with suitable adhesive before pressing, the prepreg layers 82 being placed around and above the components 81,
  • 86 'double-layer' micro via connecting outer foil with component terminal
  • 87 copper foil added together with 83 at first press cycle
  • 88 external components soldered post board manufacture in normal fashion
  • 89 through via, added after second lamination at same cycle as 86 and 96
  • 95 internal component connected at same cycle as 89 formed
  • the prepreg layer number and thickness is chosen so that the thickness does not reach a minimum possible pressed thickness, namely that of the non-flowable fibres impregnated in the resin, and does never reach to the height of any component.
  • Dummy apertures may be included in some prepreg layers to control flows and thickness. Determination of number, size, and locations of component and dummy apertures is according to average resin flow distance linked to its viscosity in the build-up , press cycle pressure and duration, and mechanical CAD data for the components.
  • the components embedded according to the invention may be of any electronic or opto-electronic type such as:
  • BGAs Ball grid arrays
  • CSPs without solder balls, and dies. There may be via connections to lateral terminals.
  • prepreg be used. Any material having electrical insulation properties and being capable of reflowing (preferably but not necessarily during lamination pressing) without excessive pressure being applied to components may be used. Examples are:
  • a powder epoxy which melts when the circuit/panel and/ or the epoxy itself is heated and dipped into it.
  • the coating thickness will depend on the circuit/panel temperature. Such temperature must not allow resin to more then partly cure to provide good resin flow during final pressure lamination step in which the epoxy is re-flowed under pressure.
  • Fibres may be mixed with the epoxy for purposes of thermal conductivity and/ or for strength. Thick coatings can be applied as there are no solvents in such powder.
  • acid exposure may be used for simultaneous formation of a large number of vias.
  • plasma etching may be used.
  • the internal material may be pre-processed to remove glass from the via locations, thus avoiding any potential barriers to the acid dipping via formation.
  • the process of the invention uses a variant of a standard process for manufacturing multilayer circuit boards, and so may be easily implemented. It allows a very high component density to be achieved with excellent versatility. It also provides excellent protection for the embedded components. Another advantage is that there is no need for soldering, thus avoiding the quality problems associated with solder joints.
  • the process may be used to completely encapsulate a circuit for use in a harsh environment, with for example external condensation.
  • the apparent disadvantage of poor thermal dissipation can be avoided by providing thermal conduction planes and/ or vias as described above.
  • a metal layer may double as both a power plane and a heat dissipater.
  • the invention is not limited to the embodiments described but may be varied in construction and detail.
  • copper when used in this specification it shall be noted that although copper is the most common conductive material used, other suitable conductive materials are not excluded.
  • FR4 When used herein it shall be noted that other resin systems are suitable, as set out above.
  • 'via' should be interpreted to include blind 'micro vias' and blind drilled or etched holes and through holes of any suitable size.
  • plated via should be interpreted accordingly, although sometimes just "via” has been used for this, although the meaning is clear from the context.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un procédé permettant de fabriquer un circuit dans lequel sont incrustés des composants (13); lequel procédé consiste à placer les composants (13) sur un substrat (14) et à appliquer des feuilles préimprégnées (15). Ces feuilles préimprégnées (15) présentent des ouvertures permettant l'adaptation aux composants; le nombre de feuilles et la disposition des ouvertures sont choisis de manière à pouvoir s'adapter à une variété de dimensions X, Y et Z des composants. Une couche supérieure comprenant une feuille de Cu (16(b)) est appliquée. L'ensemble est pressé lors d'une opération semblable à celle du pressage de lamination de cartes multicouches, ce qui a pour effet de provoquer l'écoulement de la résine préimprégnée qui enrobe les composants sans dégâts. Des raccordements électriques sont réalisés par perçage puis placage de trous de raccordement.
PCT/IE2003/000094 2002-06-19 2003-06-19 Fabrication de circuits electroniques WO2004001848A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP03760849A EP1514307A1 (fr) 2002-06-19 2003-06-19 Fabrication de circuits electroniques
AU2003253227A AU2003253227A1 (en) 2002-06-19 2003-06-19 Electronics circuit manufacture
US11/012,196 US7485489B2 (en) 2002-06-19 2004-12-16 Electronics circuit manufacture

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IE020503 2002-06-19
IE20020503 2002-07-22
IE020609 2002-07-22
IE2003/0455A IE83585B1 (en) 2003-06-19 Electronics circuit manufacture

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