WO2004001810A2 - Integration coplanaire d'un semiconducteur a desaccord de reseau dans du silicium via des substrats virtuels de liaison de plaquette - Google Patents

Integration coplanaire d'un semiconducteur a desaccord de reseau dans du silicium via des substrats virtuels de liaison de plaquette Download PDF

Info

Publication number
WO2004001810A2
WO2004001810A2 PCT/US2003/020054 US0320054W WO2004001810A2 WO 2004001810 A2 WO2004001810 A2 WO 2004001810A2 US 0320054 W US0320054 W US 0320054W WO 2004001810 A2 WO2004001810 A2 WO 2004001810A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
virtual substrate
virtual
etch
planarized
Prior art date
Application number
PCT/US2003/020054
Other languages
English (en)
Other versions
WO2004001810A3 (fr
Inventor
Arthur J. Pitera
Eugene A. Fitzgerald
Original Assignee
Massachusetts Institute Of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Massachusetts Institute Of Technology filed Critical Massachusetts Institute Of Technology
Priority to AU2003253705A priority Critical patent/AU2003253705A1/en
Publication of WO2004001810A2 publication Critical patent/WO2004001810A2/fr
Publication of WO2004001810A3 publication Critical patent/WO2004001810A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/25—Web or sheet containing structurally defined element or component and including a second component containing structurally defined particles

Definitions

  • the invention relates to the field of virtual substrates, and in particular to coplanar integration of lattice-mismatched semiconductors with silicon via wafer bonding virtual substrates.
  • the large lattice constant mismatch between Si and GaAs/Ge precludes direct growth of the mismatched material directly on Si without nucleation of a high density of defects.
  • One solution to this limitation is growth of compositionally graded layers where a large lattice constant mismatch is spread across several low-mismatch interfaces, thereby minimizing nucleation of threading dislocations.
  • Compositional grading of relaxed Si 1-x Ge x layers of increasing Ge fraction can be used to create an arbitrary lattice constant ranging from that of Si to Ge on a bulk Si substrate. Such a structure is termed a virtual substrate.
  • FIG. 1 is a schematic block diagram demonstrating the issue of non-coplanarity arising when SiGe virtual substrates are used to integrate Ge or GaAs with Si;
  • CMP of the Ge virtual substrate is facilitated with a planarization layer consisting of an epitaxial Si 1-x Ge x layer or deposited oxide. This layer not only aids surface planarization, but also serves to protect the Ge surface from subsequent post-CMP and pre-bonding cleaning steps.
  • the wafers 40, 42 may be given a plasma treatment, typically in an O 2 plasma, as an additional surface activation step to improve the bond strength obtained during annealing temperatures below 800°C.
  • the wafers 40, 42 are direct bonded and annealed at a nominal temperature of 250°C for a nominal time of 12hours to strengthen the bond.
  • Layer exfoliation is carried out at a temperature ranging between 300 and 650°C with a nominal temperature of 450°C, transferring the CMP layer 34 Ge 46, 50 , passivation layer 44 and etch-stop 36 layers to the Si handle wafer 42, as shown in FIG. 9D.
  • the transferred film structure 52 is etched in H 2 O 2 to selectively remove the damaged Ge surface 50, as shown in FIG. 4E.
  • a selective CMP step could be applied to remove the remaining etch stop layer 36, as shown in FIG. 9F.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Paints Or Removers (AREA)

Abstract

La présente invention concerne un procédé de liaison de semiconducteurs à désaccord de réseau. Selon le procédé de l'invention, on forme un substrat virtuel à base de Ge et on dépose sur ce dernier une couche soumise à un polissage chimico-mécanique (CMP) qui forme un substrat virtuel planarisé. Ensuite on lie un substrat Si au substrat virtuel planarisé et on effectue une exfoliation de couche sur des couches sélectives du substrat virtuel planarisé afin de produire une couche de Ge endommagée. Enfin, on enlève la couche de Ge endommagée.
PCT/US2003/020054 2002-06-25 2003-06-25 Integration coplanaire d'un semiconducteur a desaccord de reseau dans du silicium via des substrats virtuels de liaison de plaquette WO2004001810A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003253705A AU2003253705A1 (en) 2002-06-25 2003-06-25 Coplanar integration of lattice-mismatched semiconductor with silicon via wafer boning virtual substrates

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39155502P 2002-06-25 2002-06-25
US60/391,555 2002-06-25

Publications (2)

Publication Number Publication Date
WO2004001810A2 true WO2004001810A2 (fr) 2003-12-31
WO2004001810A3 WO2004001810A3 (fr) 2004-04-08

Family

ID=30000719

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/020054 WO2004001810A2 (fr) 2002-06-25 2003-06-25 Integration coplanaire d'un semiconducteur a desaccord de reseau dans du silicium via des substrats virtuels de liaison de plaquette

Country Status (3)

Country Link
US (3) US7157119B2 (fr)
AU (1) AU2003253705A1 (fr)
WO (1) WO2004001810A2 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2886763A1 (fr) * 2005-06-06 2006-12-08 Commissariat Energie Atomique Procede de realisation d'un composant comportant au moins un element a base de germanium et composant ainsi obtenu
WO2007020351A1 (fr) * 2005-08-16 2007-02-22 Commissariat A L'energie Atomique Procédé de report d'une couche mince sur un support
US8252663B2 (en) 2009-06-18 2012-08-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer
US8609514B2 (en) 1997-12-10 2013-12-17 Commissariat A L'energie Atomique Process for the transfer of a thin film comprising an inclusion creation step
US8778775B2 (en) 2006-12-19 2014-07-15 Commissariat A L'energie Atomique Method for preparing thin GaN layers by implantation and recycling of a starting substrate

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7157119B2 (en) * 2002-06-25 2007-01-02 Ppg Industries Ohio, Inc. Method and compositions for applying multiple overlying organic pigmented decorations on ceramic substrates
US7453129B2 (en) 2002-12-18 2008-11-18 Noble Peak Vision Corp. Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US20050069714A1 (en) * 2003-09-30 2005-03-31 Hart Terence J. Method and compositions for improving durability of coated or decorated ceramic substrates
US20070087118A1 (en) * 2003-06-19 2007-04-19 Tang Robert H Method and compositions with nonexpandable or expanded beads for coating ceramic substrates
RU2378230C2 (ru) * 2003-07-25 2010-01-10 Ппг Индастриз Огайо, Инк. Способ и композиции для нанесения на стеклянные и керамические подложки
US7279369B2 (en) * 2003-08-21 2007-10-09 Intel Corporation Germanium on insulator fabrication via epitaxial germanium bonding
US20050067377A1 (en) * 2003-09-25 2005-03-31 Ryan Lei Germanium-on-insulator fabrication utilizing wafer bonding
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
WO2005104192A2 (fr) * 2004-04-21 2005-11-03 California Institute Of Technology Procede de fabrication de substrats virtuels lies a une plaquette de gaas/si et de substrats virtuels associes
US7247545B2 (en) * 2004-11-10 2007-07-24 Sharp Laboratories Of America, Inc. Fabrication of a low defect germanium film by direct wafer bonding
US20060270778A1 (en) * 2005-05-26 2006-11-30 Dow Global Technologies Inc. Sealer compositions
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
US7202140B1 (en) 2005-12-07 2007-04-10 Chartered Semiconductor Manufacturing, Ltd Method to fabricate Ge and Si devices together for performance enhancement
US7700395B2 (en) * 2006-01-11 2010-04-20 Stc.Unm Hybrid integration based on wafer-bonding of devices to AlSb monolithically grown on Si
RU2457188C2 (ru) * 2006-03-13 2012-07-27 Агк Гласс Юроп Стеклянный лист с покрытием
JP2008004821A (ja) * 2006-06-23 2008-01-10 Sumco Corp 貼り合わせウェーハの製造方法
US7442599B2 (en) * 2006-09-15 2008-10-28 Sharp Laboratories Of America, Inc. Silicon/germanium superlattice thermal sensor
JP2008072049A (ja) * 2006-09-15 2008-03-27 Sumco Corp 貼り合わせウェーハの製造方法
KR100864932B1 (ko) * 2007-07-23 2008-10-22 주식회사 동부하이텍 반도체 기판의 세정방법
DE102007040661A1 (de) * 2007-08-27 2009-03-05 Behr Gmbh & Co. Kg Saugrohr für einen Verbrennungsmotor
US8115195B2 (en) * 2008-03-20 2012-02-14 Siltronic Ag Semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer
DE102008059044B4 (de) * 2008-11-26 2013-08-22 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe mit einer verspannt-relaxierten Si1-xGex-Schicht
EP2251897B1 (fr) * 2009-05-13 2016-01-06 Siltronic AG Procédé de production d'une plaque comportant un substrat de silicium monocristallin doté d'un côté avant et arrière et d'une couche de SiGe déposée à l'avant
AU2011239491B2 (en) 2010-04-16 2016-02-25 Swimc Llc Coating compositions for packaging articles and methods of coating
WO2012109278A2 (fr) 2011-02-07 2012-08-16 Valspar Sourcing, Inc. Compositions de revêtement pour contenants et autres articles, et procédés de revêtement
EP3831900A1 (fr) 2012-08-09 2021-06-09 Swimc Llc Compositions pour récipients et autres articles et leurs procédés d'utilisation
KR102093405B1 (ko) 2012-08-09 2020-03-25 에스더블유아이엠씨 엘엘씨 용기 코팅 시스템
US9064789B2 (en) * 2013-08-12 2015-06-23 International Business Machines Corporation Bonded epitaxial oxide structures for compound semiconductor on silicon substrates
US9331227B2 (en) * 2014-01-10 2016-05-03 The Boeing Company Directly bonded, lattice-mismatched semiconductor device
CN110790914A (zh) 2014-04-14 2020-02-14 宣伟投资管理有限公司 制备用于容器和其它制品的组合物的方法以及使用所述组合物的方法
WO2016123602A1 (fr) * 2015-01-31 2016-08-04 Leica Biosystems Richmond, Inc. Compositions de revêtement et procédés de préparation et d'utilisation correspondants
US9871176B2 (en) 2015-02-02 2018-01-16 Ferro Corporation Glass compositions and glass frit composites for use in optical applications
US10418273B2 (en) * 2015-10-13 2019-09-17 Nanyang Technological University Method of manufacturing a germanium-on-insulator substrate
TWI614275B (zh) 2015-11-03 2018-02-11 Valspar Sourcing Inc 用於製備聚合物的液體環氧樹脂組合物

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5462883A (en) * 1991-06-28 1995-10-31 International Business Machines Corporation Method of fabricating defect-free silicon on an insulating substrate
FR2777116A1 (fr) * 1998-04-03 1999-10-01 Picogiga Sa Structure a semiconducteurs de composant photovoltaique
US6059895A (en) * 1997-04-30 2000-05-09 International Business Machines Corporation Strained Si/SiGe layers on insulator
DE10100194A1 (de) * 2000-01-07 2001-07-19 Samsung Electronics Co Ltd Integrierte CMOS-Schaltungsvorrichtungen und Substrate mit eingegrabenen Silizium-Germanium-Schichten und Verfahren zur Herstellung derselben
WO2002013342A2 (fr) * 2000-08-04 2002-02-14 Amberwave Systems Corporation Plaquette de silicium avec materiau optoelectronique integre pour circuit electronique optoelectronique integre monolithique
WO2002015244A2 (fr) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle
WO2002033746A1 (fr) * 2000-10-19 2002-04-25 International Business Machines Corporation Transfert de couches de sige a faible defaut utilisant un procede de retrogravure

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3607349A (en) 1969-05-07 1971-09-21 Neville Chemical Co Printing on substrates such as glass using epoxy resin ink compositions
US3854267A (en) * 1971-03-15 1974-12-17 Tile Council Of America Grout compositions
US4171228A (en) 1976-05-19 1979-10-16 Lowrey Hugh W Pigment composition for high build protective coating
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5478885A (en) * 1994-04-15 1995-12-26 Shell Oil Company Composition of epoxy resin, epoxidized block polydiene and curing agent
US5770647A (en) * 1994-12-27 1998-06-23 Nissan Motor Co., Ltd. Friction sound-preventing surface-treating agent
US5736602A (en) 1996-04-09 1998-04-07 Crocker; George L. Retroreflective coating composition for coil coating application, method for application, and articles produced therefrom
DE69721532T2 (de) 1996-06-19 2003-12-18 Matsumoto Yushi Seiyaku Co Steinschlagresistentes anstrichmittel
US6288170B1 (en) * 1997-05-05 2001-09-11 3M Innovative Properties Company Removable adhesive of polyepoxide, curing agent and microspheres
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
ATE283549T1 (de) * 1997-06-24 2004-12-15 Massachusetts Inst Technology Kontrolle der verspannungsdichte durch verwendung von gradientenschichten und durch planarisierung
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US6207077B1 (en) * 2000-02-18 2001-03-27 Orion 21 A.D. Pty Ltd Luminescent gel coats and moldable resins
US6403222B1 (en) * 2000-09-22 2002-06-11 Henkel Corporation Wax-modified thermosettable compositions
US6475072B1 (en) * 2000-09-29 2002-11-05 International Business Machines Corporation Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP)
US6451876B1 (en) * 2000-10-10 2002-09-17 Henkel Corporation Two component thermosettable compositions useful for producing structural reinforcing adhesives
US20050026432A1 (en) * 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
US7019339B2 (en) * 2001-04-17 2006-03-28 California Institute Of Technology Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby
US7238622B2 (en) * 2001-04-17 2007-07-03 California Institute Of Technology Wafer bonded virtual substrate and method for forming the same
US6709756B2 (en) * 2001-05-21 2004-03-23 Shin-Etsu Chemical Co., Ltd. Optical device-related adhesive and optical device
JP2003031495A (ja) * 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法
US6746902B2 (en) * 2002-01-31 2004-06-08 Sharp Laboratories Of America, Inc. Method to form relaxed sige layer with high ge content
US6723622B2 (en) * 2002-02-21 2004-04-20 Intel Corporation Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer
US7157119B2 (en) * 2002-06-25 2007-01-02 Ppg Industries Ohio, Inc. Method and compositions for applying multiple overlying organic pigmented decorations on ceramic substrates
AU2003261300A1 (en) * 2002-07-29 2004-02-16 Amberwave Systems Selective placement of dislocation arrays

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5462883A (en) * 1991-06-28 1995-10-31 International Business Machines Corporation Method of fabricating defect-free silicon on an insulating substrate
US6059895A (en) * 1997-04-30 2000-05-09 International Business Machines Corporation Strained Si/SiGe layers on insulator
FR2777116A1 (fr) * 1998-04-03 1999-10-01 Picogiga Sa Structure a semiconducteurs de composant photovoltaique
DE10100194A1 (de) * 2000-01-07 2001-07-19 Samsung Electronics Co Ltd Integrierte CMOS-Schaltungsvorrichtungen und Substrate mit eingegrabenen Silizium-Germanium-Schichten und Verfahren zur Herstellung derselben
WO2002013342A2 (fr) * 2000-08-04 2002-02-14 Amberwave Systems Corporation Plaquette de silicium avec materiau optoelectronique integre pour circuit electronique optoelectronique integre monolithique
WO2002015244A2 (fr) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle
WO2002033746A1 (fr) * 2000-10-19 2002-04-25 International Business Machines Corporation Transfert de couches de sige a faible defaut utilisant un procede de retrogravure

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8609514B2 (en) 1997-12-10 2013-12-17 Commissariat A L'energie Atomique Process for the transfer of a thin film comprising an inclusion creation step
FR2886763A1 (fr) * 2005-06-06 2006-12-08 Commissariat Energie Atomique Procede de realisation d'un composant comportant au moins un element a base de germanium et composant ainsi obtenu
EP1732122A2 (fr) * 2005-06-06 2006-12-13 Commissariat A L'Energie Atomique Procédé de réalisation d'un composant comportant au moins un élément à base de germanium et composant ainsi obtenu
US7361592B2 (en) 2005-06-06 2008-04-22 Commissariat A L'energie Atomique Method for producing a component comprising at least one germanium-based element and component obtained by such a method
EP1732122A3 (fr) * 2005-06-06 2009-11-11 Commissariat A L'Energie Atomique Procédé de réalisation d'un composant comportant au moins un élément à base de germanium et composant ainsi obtenu
WO2007020351A1 (fr) * 2005-08-16 2007-02-22 Commissariat A L'energie Atomique Procédé de report d'une couche mince sur un support
FR2889887A1 (fr) * 2005-08-16 2007-02-23 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
US8142593B2 (en) 2005-08-16 2012-03-27 Commissariat A L'energie Atomique Method of transferring a thin film onto a support
US8778775B2 (en) 2006-12-19 2014-07-15 Commissariat A L'energie Atomique Method for preparing thin GaN layers by implantation and recycling of a starting substrate
US8252663B2 (en) 2009-06-18 2012-08-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer

Also Published As

Publication number Publication date
US20040058144A1 (en) 2004-03-25
AU2003253705A8 (en) 2004-01-06
AU2003253705A1 (en) 2004-01-06
US20060235111A1 (en) 2006-10-19
US20040072409A1 (en) 2004-04-15
US6927147B2 (en) 2005-08-09
WO2004001810A3 (fr) 2004-04-08
US7157119B2 (en) 2007-01-02

Similar Documents

Publication Publication Date Title
US6927147B2 (en) Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates
EP1309989B1 (fr) Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle
US6054363A (en) Method of manufacturing semiconductor article
JP5107911B2 (ja) 転位の無い歪んだ結晶を作成するための方法
US11699615B2 (en) High resistivity semiconductor-on-insulator wafer and a method of manufacture
EP1482549B1 (fr) Procédé pour la fabrication d'une microstructure heteroepitaxiale
JP4919316B2 (ja) 層の移転を介してシリコン・オン・グラスを製造する方法
EP1763069A1 (fr) Hétérostructure semiconductrice et méthode de fabrication de cette structure
JP7470233B2 (ja) 優れた性能、安定性および製造性を有する無線周波数シリコン・オン・インシュレータ・ウエハ・プラットフォーム
CA2220600C (fr) Methode de fabrication d'articles a semi-conducteur
JP2008512868A (ja) ウェハ接合技術を用いて欠陥のない高Ｇｅ含有量のＳｉＧｅオン・インシュレータ（ＳＧＯＩ）基板を製造する方法
TWI698960B (zh) 製造絕緣體上半導體之方法
CN1774798B (zh) 从不具有缓冲层的晶片形成松弛的有用层
TWI699832B (zh) 製造絕緣體覆矽鍺之方法
KR101142138B1 (ko) 적층기판의 세척방법, 기판의 접합방법 및 접합 웨이퍼의제조방법
US7572331B2 (en) Method of manufacturing a wafer
JPWO2020014007A5 (fr)

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP