WO2003096158A2

WO2003096158A2 - Method and apparatus for assembling printed circuit boards

Info

Publication number: WO2003096158A2
Application number: PCT/US2003/014714
Authority: WO
Inventors: Eldad Giberman; Steven R. Rogers
Original assignee: Return On Investment Ltd.
Priority date: 2002-05-10
Filing date: 2003-05-09
Publication date: 2003-11-20
Also published as: WO2003096158A3

Abstract

Improved methods and apparatus for the programming and testing of programmable electronic devices such as integrated circuits, and to the automated assembly, programming, testing and verification of assembled printed circuit boards in a single unified apparatus (1-4).

Description

Method and Apparatus for Assembling Printed Circuit Boards Technical Field

The present invention is directed generally to the testing and programming of programmable electronic devices, and to the automated assembly, testing and verification of assembled printed circuit boards.

Background of the Invention

High volume manufacturing of printed circuit boards (PCBs) is generally carried out by means of Pick-and-Place (P&P) machines, which rapidly pick electrical components from a feeder device and place them onto a PCB with high placement accuracy. State-of-the art machines can perform placement at speeds of 0.1 seconds per electrical component, and can complete an entire PCB in 20 seconds or less.

Programmable electronic devices such as programmable integrated circuits (PICs), including flash memories, EEPROMs, FPGAs, microcontrollers, and the like, require electrical testing and/or programming prior to being placed on the PCB. The term "testing" will be used in a broad sense to include both electrical testing and programming, unless the context indicates otherwise. Typical testing times for a PIC can be 100 seconds or more.

In the past, off-line testing of PICs was performed prior to assembly. However, this created major logistics problems because programs stored in PICs were under constant development, and the entire inventory of tested PICs would often have to be discarded because of a program change. Known circuit board test connectors, fixtures, and protocols can be divided into two basic classes. The first class includes parallel testers, i.e. test apparatus having an adapter in which all circuit board test points are contacted simultaneously by means of an adapter using 'Bed-Of- Nails' technology. The second class is composed of apparatus that sequentially scan the individual circuit board test points by two or more test contacts known as 'Flying Probes.' The current dominant solution for testing an assembled PCB is the In-Circuit-Test (ICT) approach, using Bed-Of-Nails or Flying Probes that make contact with appropriate points on the electronic devices or on the board, and transmit electrical signals between the test system and the device under test. Because of their relatively low cost, high throughput, and diagnostic accuracy, ICT is used universally in virtually all electronic product assembly lines. ICT products support a broad range of PCB test applications, including prototype and ramp-up, high- volume production, selective or sample test, and final subsystem or system test. ICT systems examine the assembled PCB for proper construction, proper components, and can execute some combination of the following protocols: determine presence or absence of components, identify faulty components, program and verify ICs that are programmable, and test the overall functionality of the PCB.

Assembled PCBs comprise nearly all of electronic products. The density on such PCBs is constantly increasing commensurate with the miniaturization of components such as integrated circuits, resistors, capacitors, and similar devices. Such increasing density also increases the complexity and difficulty of adequately testing such boards. The assembled PCB test industry has attempted to evolve in parallel with the ever more difficult requirement.

However, each of the current designs involves considerable compromise, resulting in higher cost of ownership, higher cost of operation, and a reduction in product yield.

Integral to designs for such assembly and testing systems are IC sockets, which have been in use for years, either to permanently house the device in operation as a component of a product, or to temporarily house it during testing and programming. In current test systems, a broad variety of socket designs exist, intended to hold, and provide an electrical connection to, packaged integrated circuits ("chips") of various configurations. Such chips can be produced in several formats, and many different test/programming sockets have been configured to accommodate them, each with various advantages and disadvantages. Elastic and spring-loaded connectors called "Pogo Pins" have been in use for years as an established means of connecting integrated circuits to test assemblies.

The primary problem with current assembled PCB test/programming/validation technology is that the test functions generally cannot be performed in serial with the production process, but must be performed offline. After components have been assembled onto the printed circuit board, the result is moved to a separate offline tester. When faults are identified the board must be reworked and retested before it can be returned to the online assembly process.

Another problem with current technology is that both flying probes and bed of nails circuit access techniques require specific conductive pads on the circuit board with which they must make contact, thus increasing the size of the circuit board consistent with the area dedicated to such pads. Yet another problem with current technology is that even when space is allocated for contact pads, the typical system cannot program in parallel and must rely upon serial programming using protocols such as JTAG and boundary scan, etc. Obviously, serial requires more time than parallel. A further problem with current technology is that ICT can handle only one panel of assembled PCBs at a time, and therefore parallel programming/testing is conceptually impossible. Since ICT becomes an added stage, it increases production time per unit.

A still further problem with current technology is that assembly is a faster sub-process than is ICT programming and testing, thus the overall production time is increased by the requirement for the offline processes, increasing a critical economic factor: Time To Market (TTM).

Yet another problem with current technology is that the requirement for an offline, additional, machine increases the space required for the assembly/test/programming functions. Another problem with current technology is that with ICT a separate bed of nails design and production cycle must be developed for each type of PCB, increasing inventory and cost of ownership, as well as a pro-rated cost of operation.

Another problem with current technology is degradation of signal quality by bed of nails or flying probe contacts, and the cabling required to transfer signals from the test point to the analytical system. Another problem with current technology is that yield of the processes is significantly reduced not by failure of components or assembly, but by failure of the test apparatus. Current first-pass yield is typically about 85%. The result is unnecessary rework or additional evaluation, increasing cost of production.

A further problem with current technology is that failure analysis is done at the board level rather than at the component level, thus increasing time required and cost of the process.

A still further problem with current technology is that conversion from any one operating modality or configuration to another generally involves extensive system analysis, software writing, debugging, validation, and other functions that add significantly to the cost, time, and risk of conversion. Another problem with current technology is that manual processes are required for second-level analyses, system modifications, rework, transport, and other steps in the production cycle, and manual processes are generally more costly than automated ones. The main problem with conventional IC sockets is the relative inflexibility of socket configurations, resulting in a need for a different socket design for each type of integrated circuit.

Another problem with conventional sockets is that any change in any of the parameters (IC size, number of pins, type of pin, pitch between pins) dictates a new socket, so the ability to handle a variety of integrated circuit types and formats depends upon an inventory of components that greatly elevates the cost of ownership of the system.

Yet another problem with conventional sockets is that the need to change sockets to accommodate various ICs increases the cost of production due to required, set-up time (down time, labor), and required accessories such as arms to open/close the socket, a mechanical precision system to accurately position the IC, and some sort of pressure or vacuum device to ensure good electrical contact.

A further problem with current sockets is that they cannot readily be used in P&P machines without delaying the revolver head, because the economical cycle time for placing one IC is less than 100 milliseconds, and by using current technology without delaying the process the IC can bounce from the socket and lose its accurate placement and electrical contact.

Therefore programming and testing functions are generally performed offline, creating a variety of production management complexities.

A still further problem with current sockets is a lack of durability due to moving parts, which produce friction and wear, with a resulting insidious failure of the socket that increases operating cost substantially due to replacement rate, while increasing the percentage of improperly processed ICs.

Another problem with current socket designs is that failures and inadequacies of the sockets appear to be failures of the device under test (DUT), and therefore conventional socket designs reduce the yield of the test/programming processes. PCT application WO0045323, entitled "In-line Programming System and Method", published on August 3, 2000, describes a system in which the testing process is carried out directly on the P&P machine. An essential part of the disclosed system is a device consisting of a number (N) of sockets, which enables the testing of N PICs in parallel. The average testing time per PIC is thereby reduced approximately by a factor of 1/N, assuming negligible time is spent in the mechanical transfer of PICs to and from the device. For a large enough value of N, say N=5 or more, the average testing time can be reduced to a level where in-line testing on the P&P machine becomes feasible. However, the need for a large number of sockets in the test device creates a reliability problem. If any of the N sockets fail, the average testing time per PIC will increase, and the P&P machine either will have to be operated at a slower speed, or it will have to be stopped entirely until the faulty test device is replaced. Both of these options are economically unacceptable. What is needed, therefore, is a means for improving the reliability of test devices used in in-line assembly systems.

While prior art devices may be suitable for the particular purposes that they address, they are not optimum, and certainly cannot support testing and programming integrated circuits as part of the surface mount technology (SMT) assembly line, online rather than offline, with the improved output yield percentage, lower cost of ownership, and lower operating cost attainable by the present invention.

Disclosure of the Invention

The present invention provides improved methods and apparatus for the assembly, programming and testing of programmable electronic devices, and to the automated assembly, programming, testing and verification of assembled printed circuit boards. In one aspect, the present invention provides a method for assembling an assembled printed circuit board (APCB) in an integrated assembly apparatus. The method comprises the steps of receiving, in the assembly apparatus, a programmable electronic device (PED) to be programmed and a printed circuit board (PCB); automatically programming the PED in the assembly apparatus; automatically testing the programmed PED in the assembly apparatus; and assembling the APCB in the assembly apparatus by assembling the programmed and tested PED and the PCB so as to form the APCB.

A further aspect of the present invention provides an assembly apparatus capable of assembling an APCB. The apparatus comprises means for receiving a PED to be programmed; means for automatically programming the PED; means for automatically testing the PED; means for receiving a PCB; and means for automatically assembling the programmed PED and the PCB so as to form the APCB.

Other aspects of the invention include improved sockets for testing PEDs, methods and apparatus wherein the process of assembling, programming and testing the PED and APCB are fully automated, as well as a PED Test Tray integrated into the assembly apparatus which provides means for detecting and preventing interference between the testing means and the assembly means during the testing of the PED.

A primary object of the present invention is to provide an improved method for testing/programming integrated circuits and APCBs that can be integrated into the online assembly of SMT products, rather than taken offline as is required by prior art devices. Another object of the present invention is to provide an improved system with an improved output yield percentage and lower operating cost.

Another object is to provide an improved socket that reduces the cost of ownership by minimizing the number and variety of parts required to accommodate a wide variety of DUT configurations. Another object is to provide an improved system that reduces the cost of conversion from predecessor systems to the invention by application of algorithms to convert layout and test patterns as required. Another object is to exploit and integrate an improved socket technology for testing/programming integrated circuits, with such sockets using the same accessories for many different types of ICs, as described in the precedent invention submitted by the same inventors. Another object is to integrate the universal socket design as part of the Test Tray unit within the pick and place function.

Another object is to provide a Test Tray that quickly and automatically executes device- level validation, testing, and programming, identifying and removing the faulty devices prior to their entry into the automated production stream.

Another object is to provide an APCB tester that quickly and automatically executes board-level validation and testing, with a far higher PASS percentage partly due to the pretesting of components accomplished in the Test Tray.

Other objects and advantages of the present invention will become obvious to the reader and it is intended that these objects and advantages be within the scope of the present invention. In these respects, the improved socket for testing/programming integrated circuits according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of enabling the testing and programming of integrated circuits as part of the surface mount technology (SMT) assembly line, online rather than offline, and particularly suited for rapid placement systems such as SMT P&P machines, with an improved output yield percentage and lower operating cost. To the accomplishment of the above and related objects, this invention may be embodied in the form illustrated in the accompanying drawings, attention being called to the fact, however, that the drawings are illustrative only, and that changes may be made in the specific construction illustrated.

Brief Description of the Drawings

Figure 1 depicts an embodiment of the overall socket and precision placement assembly of the present invention, showing the operational sequence of the Preciser; Figure 2 depicts a socket and precision placement assembly of the invention, together with the mechanism that operates it;

Figure 3 depicts a typical unit using a one-armed version of the Preciser of the invention, with seven stations each in a different phase of operation;

Figure 4 depicts a cross-section of an assembly of the present invention, with the Pogo Pin bed of nails establishing contact between the integrated circuit and the base of the socket;

Figure 5 portrays an exploded view of an assembly of the invention in which a single arm pressure device is used to apply pressure to the device;

Figure 6 shows a top view of one Test Tray embodiment of the present invention;

Figure 7 shows a side view of the Test Tray embodiment of Figure 6; Figure 8 shows the use of redundant probes to enhance socket reliability in a Test Tray of the present invention;

Figure 9 graphically depicts calculated values of the socket reliability, R(N,K) of the invention compared with the single socket reliability Rs;

Figure 10 illustrates a feedback mechanism for increasing the lifetime of the probes inside the individual sockets in the present Test Tray;

Figure 11 is a block diagram depicting the current technology of SMT assembly line flow with conventional ICT;

Figure 12 is a block depicting the replacement of conventional ICT with device level tests and board level tests according to the invention; Figure 13 is a block diagram depicting an Online-PCB-Testing-System (OPTC) of the present invention;

Figure 14 is a schematic depiction of a Test-Tray according to the present invention;

Figure 15 is a schematic depiction of the Test-Tray of Figure 14 illustrating a socket with a gripper, for holding the device and establishing electrical conductivity; Figure 16 is a schematic depiction of a cycle of placing one device on the socket, in which (1) the socket is empty and the gripper is open, a free socket is awaiting a fresh PED, (2) the Pick and Place head places the device on the top of the socket, (3) the first motor bring the griper's arm to the exact location above the device, and (4) the second motor moves the gripper' s arm and controls the pressure on the device;

Figure 17 is a schematic depiction of two configurations, one where the socket is disassembled, exposing the socket's internal structure , and one where the socket is assembled and connected to the PCB;

Figure 18 is a schematic depiction of the control of the system by connecting the two testers (pre-assembly and post-assembly) to a local network, in order to control and monitor the system from one place;

Figure 19 depicts connecting the internal test pads on the board using BS technology Figure 20 depicts the assembled and soldered board being pushed into the cartridge;

Figure 21 depicts top views of two different cartridge widths, which differ only in the connector;

Figure 22 is a schematic depiction of a mixed signal Testing Data Collector; Figure 23 is a flow chart depiction of a mixed signal Testing Data Collector; Figure 24 is a schematic depiction of a post-assembly tester generating the test pattern that is applied to the printed circuit board;

Figure 25 depicts the gripper in which panel A is a side view, and panel B depicts the Pick and Place revolver head;

Figure 26 depicts a Test-Feeder as an alternative tester to the pre-assembly Test-Tray, wherein the Test-Feeder is externally attached to the Pick and Place machine; Figure 27 depicts a test-feeder cycle of the embodiment of Figure 21 ; Figure 28 depicts a testing and programming cycle of the embodiment of Figure 21 ; Figure 29 depicts the repetition of the cycles of Figures 22 and 23 and the completion of the assembly cycle; and Figure 30 depicts the test-feeder alternative of Figure 21 in schematic form.

Detailed Description of the Invention

In the description of the present invention, the following terms shall have the defined meanings:

As used herein, the term "programmable electronic device" or "PED" refers to any electronic devices such as programmable integrated circuits (PICs), including, for example, flash memories, EEPROMs, PLDs, PALs, FPGAs, microcontrollers, and the like, now known or developed in the future, which require electrical testing and/or programming prior to being placed on the PCB.

As used herein, the term "printed circuit board" or "PCB" refers to any substrate, now known or developed in the future, upon which programmable electronic devices are assemble to form a functional assembled printed circuit board. In view of the disadvantages inherent in the types of PED and PCB testing and programming currently available, the present invention provides a new improved method and apparatus to test and program PEDs as an integral part of the APCB assembly line, i.e. online rather than offline, with improved output yield percentage, lower ownership cost, and lower operating cost.

A primary object of the present invention is to enable production processes to perform component and APCB testing/programming at realtime speed online, with algorithms to support automatic and low-cost conversion from predecessor test apparatus to the new technology. The present invention includes a complete and comprehensive testing apparatus for testing APCB without a need for Bed of Nails or Flying Probes, a means for testing the APCB online as an integrated, serial, subprocess of the overall SMT assembly line, and a means by which ICT testing apparatus can be rapidly and easily replaced by an online tester defined by this invention

The present invention divides the APCB testing process into two stages; pre-assembly PED testing and programming, and post-assembly board testing. Together, these two stages provide complete, fast, and economical testing and programming of the end product.

The pre-assembly PED tester device ("Test Tray") is capable of executing all tests and programming related to the device-level tests, sorting the faulty devices prior to the P&P operation. The device-level tests are those that can be independently performed on the PED device (passive or active) itself, independent of interaction with the PCB. The Test Tray is comprised of an IC tester that can drive test patterns and compare them to standards, a multipurpose test socket to establish electrical conductivity, a gripper to hold the device under test (DUT), and a mechanical chassis to hold the tester and socket in accurate locations.

The post-assembly APCB tester tests the finished PCB product, which will have a higher effective yield because components thereon will have been tested pre-assembly by the Test Tray device just described. It includes a cartridge to hold the APCB in place, electrical connectors, and a board tester that can drive and compare test patterns.

The attached figures illustrate an improved system for testing/programming APCBs. This invention is a system comprising individual subsystems and components, which are all susceptible to considerable variation without negatively affecting the performance of the result. A preferred embodiment of the invention is therefore comprised of such subsystems and components, each of which represents generally known techniques and components executable by those skilled in the various arts involved. Existing patents applicable to, or suitable as background of, the invention include 6,353,329, 6,340,896, 6,283,780, 6,299,320, 6,204,680, 6,152,744, 6,124,720, 6,118,291 and 5,208,976, as well as PCT Publication WO00/45323. Pogo pins are well described in 6,288,555 and 6,261,130. The overall system is divided into two subsystems: pre-assembly testing is performed at the component level before those components are added to the automated production stream, and post-assembly testing is then performed on the complete assembled APCB.

Pre-Assembly Testing and Test Tray The Test Tray pre-testing executes all tests and programming related to the devices to be used in assembly, and removes faulty components. This testing phase checks for component functionality, value, tolerance, alignment, orientation, and the component identity against the bill of materials (BOM). It will also program and verify any nonvolatile memory (NVM). The attached Figures 1 through 5 illustrate an improved socket for testing and programming PED devices, which comprises a mechanical subassembly ("Preciser") for accurately holding the DUT and a gripper to apply downward pressure to the PED, a bed of nails array of telescoping pins ("Pogo Pins") as electrical paths, a housing with holes through which th Pogo Pins pass, and associated electrical connections to pass signals between the socket and the test system. In a preferred implementation, the gripper assembly consists of one (Figures 3-5) or two

(Figures 1-2) gripper arms driven by a mechanical geared mechanism that is synchronous with the other mechanical components of the system. The arms are driven by a programmable mechanical geared system. The ability to control the rotation of the arms horizontally permits use of the system with DUTs of different dimensions and characteristics. Each arm is so configured that it will both rotate about a vertical axis, and move axially, all under control of the present system.

Good conductivity in a Pogo Pin system requires accurate management of downward pressure, which is established by the present system as that required for each pin (an established number) times the number of pins in use by the particular DUT. Therefore, the control system will control the pressure applied by the arms to permit good electronic contact regardless of the number of pins, or the type of contacts, of the DUT. There is a multiplicity of spring-loaded Pogo Pins, of a number far greater than the pins of a PED device, with each pin consisting of an outer housing, an inner spring, and a sliding contact at each end. The contacts are restrained from moving outside the housing by a partial ^' crimp, and the spring and materials are selected to ensure low resistance to electrical signals. This housing is a block with holes larger than the outer diameter of a Pogo Pin, thus permitting airflow and allowing the Pogo Pin to operate axially while being fixed in its location. The assembly is connected to the overall Test Tray, and then to the system, by conventional electrical connections and cables, with impedances and loading selected in accordance with the intended frequency range of the system. As shown in Figure 1, the gripper is an assembly adjacent to the test socket; a vertical shaft operates either one or a pair of geared arms capable of both rotation (synchronously geared together) to position the arms over the device when it is tested, and vertical movement to apply downward pressure upon the device to ensure electrical connection. The gripper' s arm or arms then move(s) laterally to make space for the revolver to replace the DUT for the next test cycle. The socket can also be at the "bottom" of a depression with angled sides that lead the device to its required location, with a partial vacuum applied to hold the DUT in place while being tested.

In Figure 1 , panels A-D, is shown a typical assembly operation using a mechanical Preciser and two gripping arms, in which (Panel A ) the arms open, and the socket is empty and awaiting delivery of PED by the revolver; (Panel B) the PED is placed on the socket by the revolver head, into the Preciser at the top of the socket. The Preciser prevents the PED from moving after the revolver head completes placement. When the revolver leaves the PED atop the socket, the PED remains in place; (Panel C) the arms close as appropriate to the DUT's dimensions, but do not yet touch the top of the PED; and (Panel D) the arms apply controlled pressure to the PED, as determined by the number and type of contacts, to establish electrical connection and prevent unwanted movement.

There is a multiplicity of spring-loaded pins comprising a Bed of Nails, of a number far greater than the pins of an integrated circuit, with spacing such that contact will always be made between the desired points. Each Pogo Pin in the Bed of Nails consists of an outer tube, two telescoping electrical contacts within that tube, plus an inner spring that tends to force the two contacts out. They are, however, held within the tube by any sort of crimp or other device that impedes their movement beyond the ends of the outer tube. The number of pins is sufficiently greater than the number of pins on potential PED devices to be tested and programmed so that any contact on the device will find an electrical path to the system, yet the pins are sufficiently proximate one to another, yet insulated one from another, such that no Pogo Pin can make contact with more than one pin of the DUT. At least one Pogo Pin will make a reliable electrical connection with both a pin of the DUT and a contact point beginning a conductive path from the socket to the system. The pattern of pins can be established to encompass all possible configurations and pin counts of potential PEDs to be tested. A Pogo Pin can consist of an outer housing which is itself one contact, with an internal pin applying outward pressure to the second contact, and a crimp preventing the second contact from being expelled from the outer housing. This housing is a block with holes larger than the outer diameter of a Pogo Pin, thus permitting airflow for cooling and/or for suction to hold the DUT in place if that modality is selected, and allowing the Pogo Pin to operate axially while fixed in its location.

The assembly is connected to the overall Test Tray, and then to the system. This is accomplished by conventional electrical connections and cables, with impedances and loading selected in accordance with the intended frequency range of the system. The mechanical interconnection between the revolver assembly and the Preciser can be a simple gear and shaft drive that ensures synchrony between them, with the Preciser arms opening, the DUT being placed, the arms closing and then moving down to apply pressure. The downward pressure depresses the DUT into the array of Pogo Pins, and therefore pressure upon the other end of the Pogo Pins proximate to electrical points that are fixed within the assembly and leading to the system, thus achieving electrical connection between the DUT and the system. The Preciser can be either a mechanical device as described above, or a pneumatic (e.g. vacuum) device that pulls the DUT into the Pogo Pins. The Pogo Pin array includes a housing with a hole for each pin, and each hole is sufficiently larger than the Pogo Pin to provide airflow for pulling the PED down, and/or for cooling. Multiple sockets as described herein are in an array, or Test Tray, beneath the "Place" component of a P&P production assembly system. The Place component is typically a Revolver, which picks a device from a ribbon or other source, and then carries it to the Test Tray. As the Revolver approaches the test socket, synchronous mechanical connections ensures that the arms of the Preciser are moved out, making room for the placement of the DUT. Those arms then move inward to the top of the DUT, and the same mechanical linkage lowers the arms, thus applying downward pressure upon the device. That downward pressure depresses some combination of Pogo Pins, which are affixed in all planes but the vertical, and which make contact with the pins of the DUT and with the conductive points of the tray, leading to the system. The software analyzes the electrical paths created by the Pogo Pins and signals are routed to the appropriate pins, to test and program the device as required. The Preciser arms then lift and move aside, still geared together and synchronous with the Revolver, which picks up the tested device and replaces it with the next DUT. The configuration and mechanical synchronicity of this socket system permits the loading, testing, and unloading of devices without the requirement for slowing the rate at which the revolver operates, and therefore without slowing the production process.

Representative Embodiment of a Preferred Test Tray

The present invention also provides a Test Tray device comprised of a multiplicity of sockets, in which one or more of the sockets is redundant. For additional improvement of reliability, the individual sockets may also contain redundant probes. Finally, for a further improvement in reliability, a resistance-force feedback mechanism is provided which applies minimal contact force to the socket probes, thus extending their lifetimes.

Figure 6 shows a top view, and Figure 7 shows a side view of a preferred embodiment of a Test Tray of the invention. Test Tray 1 contains sockets 2 which are in contact with DUTs 3 and redundant sockets 5 which are not in contact with DUTs. Each socket contains a multiplicity of probes 4. If one of the sockets 2 fails, its indicator light 20 illuminates, and its corresponding DUT is transferred to a redundant socket 5. The Test Tray consists of N+K sockets, where K spare sockets are included for redundancy. In the example of Figure 6 and 7, N=5 and K=l. Each socket contains an array of probes, for example a Bed of Nails.

During operation, the tray is filled with N devices under test (DUTs), in one of several ways. For example, one way is to randomly distribute the N DUTs among the available sockets. Another way is to place the N DUTs in the first N sockets, and only to use the spare sockets in the event one of the first N sockets has failed.

Let S denote the lifetime of a single socket, measured in test cycles, and let Rs(t) denote the socket reliability function, which is equal to the probability that S>t. By definition, Rs(t) is a non-increasing function of time, such as the exponential function: Rs(t) = exp( -t/τ ) ( 0 ≤ t < ∞ ) where τ is a parameter equal to the mean socket lifetime. The Test Tray containing N+K sockets continues to operate so long as N or, more sockets are functioning. Assuming that socket failures occur independently, the overall reliability function for the Test Tray is:

R(N,K)= Rs^(N+K) + [N+K,l] Rg^¹"⁾ (1-Rs)¹ + [N+K,2] Rs ^N+K"2) (1-R_S)² + . . . [N+K,K] R_S ^(N+K"K) (1-R_S)^K where [n,m] denotes the number of combinations of n objects taken m at a time, and is equal to n! / ( m! (n-m)! )

For example, in the case N=5 with no spare sockets (K=0), R(5,0) = R_S ⁵ and with one spare socket (K=l),

R(5,l) = Rs⁶ + 6 Rs⁵ (1-Rs) = Rs⁵ (6 - 5Rs) As shown in Figure 9, R(5,l) is substantially greater than R(5,0), which indicates that the addition of even one spare socket greatly improves the overall Test Tray reliability. When a Test Tray is first put into operation, at time t=0, all of its sockets have Rs equal to one. As time progresses, the value of Rs decreases. According to Figure 9, when Rs drops to a value of 0.9, the values of R(5,l) and R(5,0) are approximately 0.9 and 0.6, respectively. Thus, the Test Tray with one redundant socket is 50% more likely to be operational at this point than a Test Tray with no redundant sockets. Furthermore, the use of spare sockets has a logistic advantage. When one of the sockets fails, the tray continues to operate, and a signal is provided to the operator to advise him that replacement of a faulty socket will be needed in the near future. The operator can then choose to schedule Test Tray maintenance to coincide with other maintenance operations, so that the down time of the in-line process is minimized. A second improvement in reliability may be achieved by adding spare probes to each socket. In the event that some of the outermost probes fail, the DUT can be shifted laterally, as shown in Figure 8, so that only functioning probes come into contact with the DUT. In a manner analogous to the above equation for R(N,K), one can calculate the socket reliability function Rs, in terms of the number of required. probes, N_P, and the number of redundant probes, K_P. The result clearly shows a marked increase in socket reliability for values of Kp > 1.

Figure 8 shows the use of redundant probes to enhance socket reliability. For simplicity, a side view of a single socket and DUT is shown. Figure 8A shows the socket with the DUT placed in its nominal contact position. Probes 6 are redundant and are not used in the nominal case. However, if probe 7 fails, then the DUT is shifted to the right, as in Figure 8B, so that it contacts redundant probe 6 on the right. If instead probe 8 fails, then the DUT is shifted to the left, as in Figure 8C, so that it contacts redundant probe 6 on the left. In this way, the socket remains operational even though one of the probes 7 and 8 has failed. In the case of sockets having a two-dimensional array of probes, peripheral rows and columns of probes are added to achieve the desired redundancy.

In addition, Figure 10 shows a third improvement in reliability at the level of the individual probe. A force is applied to the DUT so as to ensure good electrical contact between the DUT and each of the contacting probes within the socket. Inside each probe is a spring mechanism whose failure rate depends upon (a) the number of spring compression cycles, and (b) the magnitude of the applied compression force F. In the prior art, a fixed force of several tens of centi-Newtons is used to ensure a contact resistance, typically, of 50 milliohms or less. However, if the DUT contacts are free of contamination, a much smaller force F may be used to achieve the desired contact resistance, with a resulting increase in reliability of the probe spring mechanism. Figure 10 illustrates a feedback mechanism, in which the contact resistance R is measured for one or more probes, and the applied force F is varied in proportion to the value of R. In this way, a minimum of applied force is used, and the lifetimes of the individual probes are maximized. A portion of DUT 3 is shown, together with one of its contacts 9. Contact 9 is hemispherical in shape for a DUT of the ball-grid array (BGA) type. For other kinds of DUTs, contact 9 may have a different geometrical shape, such as an L-shape. The spring 11 inside probe 4 is compressed by means of applied force F. Failure of the spring, over time, depends upon the magnitude of F. Resistance meter 10 measures the contact resistance between the bottom of probe 4 and contact 9 of the DUT. A signal R proportional to the measured resistance is sent along signal channel 12 to a variable pressure device 13. Device 13 consists, for example, of a spring-loaded mechanism driven by a stepper motor. The magnitude of the applied force F is varied in proportion to signal R, so that only minimal force is used to maintain a desired contact resistance. Assembly and Post-Assembly Testing

Timing is a key factor in the efficient assembly of APCBs. In current technology, the time that completed boards reside in the unloader cartridge is dead time, unused. In the invention, the presence of a connector in that cartridge to support testing recaptures that dead time, performing tests while the next board is being unloaded and stored in the unloader cartridge. Therefore, the addition of connectors within the unloader's cartridge reduces assembly footprint, exploits what was once dead time, and supports an automatic process. The invention also provides an algorithm that supports the automatic conversion of existing test apparatus to the new technology. ICT end-users that seek to convert to the invention will use a "Layout Converter" algorithm, which generates a new layout that is functionally/electrically the same as the previous layout, but fits with the new online technology. The user will then use the "Pattern Conversion" algorithm to convert the test patterns, originally written for ICT, to those required by the new technology.

In the figures, Figure 11 depicts the current technology of SMT assembly line flow. After the PCB is installed into the P&P machine, the P&P handler picks devices from mechanical feeders and places them at exact locations on the board. After completing the P&P phase, the PCB moves to the oven to solder the devices onto the board. The next step is testing the PCB, which is a separate phase that ordinarily requires manual assistance. The boards are carried to the ICT or to a custom-made tester for testing. At this phase, the PCB goes to a fixture (Bed-Of-Nails or Flying Probes) that generates the test pattern of the ICT. Testing time can take from a few seconds to several minutes, and therefore must be shifted offline because it would otherwise delay the entire production sequence. Since testing takes much longer than assembly phase, it is considered to be a " bottle-neck" and increases inventory.

Figure 12 illustrates one concept of the present invention, that is, replacing ICT with component or device level tests and PCB board level tests. Device level tests would include all of the tests that are related to the component itself, for example, functionality of the component, a check of the value and tolerance of passive devices, alignment and orientation, programming and verifying NVM (Non Volatile Memory), and verifying that the device is part of the Bill-Of- Materials. PCB board level testing includes the rest of the tests that the PCB must pass in order to reach the level of quality required. For example: conductivity checks, presence of components, functionality of the PCB, and the like. The present invention offers an Online-PCB-Testing-System (OPTC) as illustrated in Figure 13, which is divided into two parts. The first part is an online device tester (pre-assembly tester), which is located inside or outside the P&P machine. In the first case there will be a Test- Tray (Figure 14) located inside the P&P machine. In the second case there will be a Test-Feeder (Figures 28-31) outside the P&P machine, and attached to it. The pre-assembly tester will perform all the "device level" tests and will sort out all the faulty components. The post- assembly tester will be located inside the unloader machine and will perform the rest of the testing. Using the present invention, the board will exit the SMT assembly line fully tested and ready to be shipped. The statistical results of the faulty devices from the pre-assembly tester, and the results of the faults in the APCB from the post-assembly tester, will be stored in one database for tracing, fault analysis, and quality diagnostics.

As mentioned above, one of the options for the pre-assembly Test-Tray, is a mechanical chassis that holds a number of sockets and grippers, with a Bed of Nails comprised of Pogo Pins as one means to establish electric connection to the pre-assembly Test Tray (Figure 14). The unique structure of the Test Tray enables the P&P handler to place the PED devices on the top of the sockets as fast as possible, and with the required precision. The P&P handler will not need to hold the PEDs on top of the sockets for the entire test time, but after placing the PED on the top of the socket, the P&P handler can leave the PED and continue in its cycle because unique grippers, as an integral part of the test socket, will rotate and descend to press the PED toward the socket in order to establish a good electrical connection. Below each of the Test-Tray sockets and connected to it, there is a tester to generate the specific required test pattern signals for testing the device. The location of the Test-Tray within the P&P device is where it is possible to place and pick a device.

The P&P head (nozzles) will collect the PEDs to be tested from the mechanical feeder, will place the PEDs on the top of the pre-assembly tester's sockets, and will continue to assemble the rest of the PCB with components that do not need to be tested. After the pre- assembly test is completed, the P&P head will collect the tested PEDs from the Test-Tray and place the tested PEDs in the correct locations on the PCB.

Figure 15 illustrates one module of a socket with a gripper, for holding the PED and establishing electrical conductivity. In this module there are two DC motors that are controlled to ensure the exact location on the PED where the gripper holds the device, and the pressure at which the gripper will press the PED into the socket. Figure 16 illustrates one cycle of placing one PED on the socket of the present invention, which comprises the following phases: a. The socket is empty and the gripper is open, a free socket is awaiting a fresh PED; b. The P&P head places the PED on the top of the socket; c. The first motor bring the gripper's arm to the exact location above the PED; d. The second motor moves the gripper's arm down and controls the pressure on the PED.

As shown in Figure 17, two configurations of the socket in the present Test Tray depict various unique features in the present invention: a. The socket is disassembled, exposing the socket's internal structure; b. The socket is assembled and connected to the PCB. In the disassembled socket, it is possible to see the Pogo Pins that will establish electric connection between the device and the PCB. The PCB is part of the tester/programmer that will generate the electric signals for testing and programming. The assembled socket will be mounted on the PCB, and will enable the P&P handler to place the device without the risk of collisions.

Since the present system is divided into two different sub-systems, it is advantageous to control the system from one place as depicted in Figure 18, hence the two testers (pre-assembly and post-assembly) are connected to a local network, in order to control and monitor the testing system from a single location.

Figure 19 shows the connection of the internal test pads on the board using boundary scan (BS) technology.

Figure 20 shows the assembled and soldered PCB being inserted into the cartridge, a step that is common between the current SMT technology and in the present invention. In the present invention, the post-assembly tester will generally be mounted on the back of the cartridge, and the PCB will be connected to it.

Figure 21 depicts top views of two different cartridge widths. One is shorter then the other. The only difference will be in the connector. In the current technology, for every new board design, the user must design and build a new fixture that typically costs $5-$ 10k. The Post-Assembly Board Tester executes all required tests that can be performed on an

APCB. This tester is mounted on the Unloader machine and is capable of testing the APCB via an electrical connector (Figure 21). When the board completes the SMT assembly line cycle (after all parts have been assembled and soldered), the board is unloaded into a cartridge inside the unloader (Figure 20). After the PCB is inserted into the cartridge, the PCB edge reaches the electrical connector that is mounted at the rear of the cartridge (Figure 21). The post-assembly board tester (Figure 24) will then initiate the test pattern of the completed APCB. In Figures 22 and 23, a Mix Signal Testing Data Collector is shown. When designing the

PCB board layout, it is important to define which of the signals need to be tested after the PCB is assembled. Connecting all the digital signals that are topologically close into one digital TDC, and connecting all the analog signals that are topologically close into one analog TDC, by using the Boundary Scan protocol (IEEE 1149.4), enables access to every signal that needs to be tested. The internal structure of the TDC is described in detail at IEEE 1149.4 standard.

Figure 24 illustrates the post-assembly tester generating the test pattern that is applied to the APCB while the APCB is inserted into the connector at the rear of the cartridge in the Unloader machine. All the test results are sent to the remote database (DB) through the local network connection. The top panel in Figure 25 shows the gripper of the present Test Tray from a side view, and the bottom panel shows the P&P revolver head.

In Figures 26-30, a Test-Feeder is illustrated as an alternative tester to the pre-assembly Test-Tray described above. The Test-Feeder is externally attached to the P&P machine. The PED components will be removed simultaneously from the tape and reel and inserted, again simultaneously, in the sockets. After programming and testing, they will be removed from the sockets and placed in a tape & reel strip that will be accepted by the P&P revolver.

As will be apparent from the above disclosure, current ICT technology in SMT assembly involves a number of disadvantages, including the following:

1. ICT requires additional surface area on the PCB, for specific pads, and thus entails additional expense and expertise.

2. In many cases there is no room on the PCB for specific ICT pads.

3. When there is room on the PCB for the ICT pads, the system can't program in parallel, and can handle only serial programming/testing.

4. ICT is executed only after the soldering of the components. Faulty components require rework of the PCB. 5. Large footprint required for ICT machines. 6. ICT technology can handle only one panel at a time, and therefore parallel programming/testing is conceptually impossible.

7. ICT is an additional stage in the assembly process and requires significant time delay in the production line.

8. With ICT technology, assembly is much faster than programming and testing. This increases time to market.

9. With conventional ICT, a specific Bed of Nails design and production cycle is required for each type of PCB.

10. Bed of Nails or Flying Probes significantly reduces signal integrity and performance.

11. Yield - the main cause for today's poor yield (-85%) is the ICT technology that depends upon Bed of Nails or Flying Probes.

12. Failure Analysis is done at the PCB level rather than at the component level.

13. Conventional ICT technology requires a manual process.

A comparison of the costs and features of the present invention versus the conventional ICT technology is illustrative of the benefit of the present invention:

With respect to the above description then, it is to be realized that the optimum dimensional relationships for the parts of the invention, to include variations in size, materials, shape, form, function and manner of operation, assembly and use, are deemed readily apparent and obvious to one skilled in the art, and all equivalent relationships to those illustrated in the drawings and described in the specification are intended to be encompassed by the present invention.

All patents and patent applications cited in this specification are hereby incorporated by reference as if they had been specifically and individually indicated to be incorporated by reference.

Although the foregoing invention has been described in some detail by way of illustration and Example for purposes of clarity and understanding, it will be apparent to those of ordinary skill in the art in light of the disclosure that certain changes and modifications may be made thereto without departing from the spirit or scope of the appended claims.

Claims

Claims:

1. A method for assembling an assembled printed circuit board (APCB) in an integrated assembly apparatus, comprising the steps of: (a) receiving, in the assembly apparatus, a programmable electronic device (PED) to be programmed and a printed circuit board (PCB);

(b) automatically programming the PED in the assembly apparatus;

(c) automatically testing the programmed PED in the assembly apparatus; and

(d) assembling the APCB in the assembly apparatus by automatically assembling the programmed and tested PED and the PCB so as to form the APCB.

2. The method of claim 1, further comprising discarding the programmed PED if the device fails an element of the test, and repeating steps (a), (b) and (c) with a replacement PED.

3. The method of claim 1, wherein step (c) includes the step of testing the programmed PED for at least one parameter selected from the group consisting of device functionality, program verification, bill-of-materials verification, and device alignment on the printed circuit board.

4. The method of claim 1 , further comprising the step of testing the programmed

PED after assembling the APCB.

5. The method of claim 4, wherein the step of testing the programmed PED after assembling the APCB comprises testing for at least one parameter selected from the group consisting of device functionality, bill-of-materials verification, and device conductivity on the printed circuit board.

6. An assembly apparatus capable of automatically assembling an assembled printed circuit board (APCB), the apparatus comprising: means for receiving a programmable electronic device (PED) to be programmed; means for automatically programming the PED; means for automatically testing the PED; means for receiving a printed circuit board (PCB); and means for automatically assembling the programmed PED and the PCB so as to form the APCB.

7. The apparatus of claim 6, further comprising means for discarding the programmed PED if it fails an element of the test.

8. The apparatus of claim 6, further comprising means for testing the programmed PED after assembly of the APCB.

9. The apparatus of claim 6, wherein the means for programming includes a means for transferring a sequence of operating codes into a memory of the PED.

10. The apparatus of claim 6, wherein the PED is a programmable logic array, and wherein the means for programming includes a means for transferring an aπangement of gating logic instructions into the PED.

11. The apparatus of claim 6, further comprising means for detecting and preventing interference between the testing means and the assembly means during the testing of the PED.

12. The apparatus of claim 11 wherein said detection and prevention means comprises an optical switch.

13. The apparatus of claim 6, wherein said means for testing the PED includes vacuum means for retaining the PED in the testing means for at least a portion of the testing sequence.

14. An in-line programming and assembly apparatus capable of automatically programming and testing a programmable electronic device (PED) and assembling an assembled printed circuit board (APCB) comprising: an input interface for receiving a PED, wherein the PED is received at the input interface; a programming device for automatically programming the PED; a placement device capable of picking up the PED from, and placing the PED at, a plurality of specific locations, wherein the placement device picks up the PED and places it in a programming site in the programming device, and wherein the PED is programmed by the programming device; a testing device capable of testing the programmed PED wherein the programmed PED is tested by the testing device, and wherein the placement device picks up the PED and places it in a testing site in the testing device; and a conveyor for receiving a printed circuit board (PCB) and moving the PCB through the assembly apparatus, wherein the PCB is received by the conveyor; wherein the placement device picks up the programmed and tested PED from the testing site and places the programmed and tested PED on the PCB board so as to form an APCB.

15. The apparatus of claim 14, further comprising a central control unit communicably coupled to the placement device, the programming device, the testing device and the conveyor, for coordinating operations of the placement device, the programming device, the testing device and the conveyor.

16. The apparatus of claim 14, wherein the input interface includes a device tray shuttle for receiving a device tray holding one or more programmable devices.

17. The apparatus of claim 14, wherein the programming device is capable of concuπently programming and testing multiple device types.

18. The apparatus of claim 14, further comprising a second testing device for testing the programmed PED after assembly of the APCB.

19. The apparatus of claim 14, wherein the testing device includes a means for detecting and preventing interference between the testing device and the assembly device during the testing of the PED.

20. The apparatus of claim 19 wherein said detection and prevention means comprises an optical switch.

21. The apparatus of claim 14, wherein the testing device includes vacuum means for retaining the PED in the testing device for at least a portion of the testing sequence.

22. The apparatus of claim 14, further comprising a second testing device capable of testing the programmed PED and the APCB after the APCB is assembled.

23. The apparatus of claim 14, the testing device further comprising a plurality of sockets wherein at least one of the sockets is redundant.

24. The apparatus of claim 23 wherein at least one of the sockets comprises a plurality of test probes, and wherein at least one of the probes is redundant.

25. The apparatus of claim 14, the testing device further comprising a feedback mechanism comprising means for measuring the contact resistance of a combination of at least one probe in a socket, and means for varying the contact force applied to said socket in proportion to said measured contact resistance.