WO2003094507A1 - Dispositif et procede de traitement de signaux video, support d'enregistrement et programme - Google Patents
Dispositif et procede de traitement de signaux video, support d'enregistrement et programme Download PDFInfo
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- WO2003094507A1 WO2003094507A1 PCT/JP2003/005488 JP0305488W WO03094507A1 WO 2003094507 A1 WO2003094507 A1 WO 2003094507A1 JP 0305488 W JP0305488 W JP 0305488W WO 03094507 A1 WO03094507 A1 WO 03094507A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
- H04N5/10—Separation of line synchronising signal from frame synchronising signal or vice versa
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
Definitions
- the present invention relates to a video signal processing device.
- input video signal For example, input video signal
- Typical conventional cyclic noise reduction circuits are represented by NTSC, PA] L, etc.
- Video signals are processed.
- VCR Video Cassette Recorder
- the normal 1x speed In addition to playback, irregular playback such as fast forward, rewind, and picture search is possible.
- the noise component is normally reduced from the input standard signal by the general cyclic noise reduction circuit mounted.
- the current field is an even field or an odd field. It will not be possible to determine exactly if there is. If the noise reduction operation including the interpolation processing by the interpolation filter 2 and the interpolation filter 5 is executed in such a state, it may not be possible to effectively reduce the noise.
- An example of such an inappropriate noise reduction operation is that the noise to be reduced appears to move upward or downward on the image. In this manner, the movement of the noise to be reduced by performing the noise reduction operation is more conspicuous than the case where the noise remains unchanged without performing the noise reduction operation. This has been shown to result in more unsightly images.
- a circuit for determining whether the input signal is a standard signal or a non-standard signal is added to a general recursive noise reduction device, and the input signal It is conceivable to execute the noise reduction operation only when is a standard signal.
- a first video signal processing device comprises: a field ID signal generating means for generating a field ID signal in accordance with a phase difference between a vertical synchronization signal of a video signal and a horizontal synchronization signal of the video signal; A first counting means for counting up a count value circulating in a predetermined range in response to a signal edge; and a count value circulating in a predetermined range in response to both edges of a field ID signal, respectively.
- a second counting means for counting up, and when the count value of the first counting means is the first value, a count value of the second counting means is obtained corresponding to an edge of the vertical synchronization signal.
- a determination unit that determines whether the video signal is a standard signal or a non-standard signal based on the count value of the acquisition unit and the second count unit acquired by the acquisition unit. Characterized in that it comprises a stage.
- the determining means determines that the video signal is a standard signal, and determines that the video signal is a standard signal. If the force value of the second force means is the second value, it is determined that the video signal is a non-standard signal, and the count value of the second count means acquired by the acquisition means is equal to the first value and the second value. If it is not one of the values of 2, the previous judgment result can be retained.
- the standard signal may be an interlaced video signal in which even fields and odd fields are alternately arranged.
- a first video signal processing method comprises: a field ID signal generating step of generating a field ID signal in accordance with a phase difference between a vertical sync signal of a video signal and a horizontal sync signal of the video signal; A first counting step that counts up a count value circulating in a predetermined range in response to a signal edge, and a count circulating in a predetermined range in response to both edges of the field ID signal, respectively. Processing of the second counting step for counting up the value and the first counting step. Obtaining the count value by the processing of the second counting step corresponding to the edge of the vertical synchronization signal when the count value obtained by the logical processing is the first value; and obtaining the count value obtained by the processing of the obtaining step. A judging step of judging whether the video signal is a standard signal or a non-standard signal based on the count value obtained by the process of the counting step (2).
- the program of the first recording medium of the present invention comprises: a field ID signal generating step of generating a field ID signal corresponding to a phase difference between a vertical synchronizing signal of a video signal and a horizontal synchronizing signal of a video signal; A first counting step for counting up a count value circulating in a predetermined range in response to the edge of the synchronization signal; and a circulating in a predetermined range in response to both edges of the field ID signal, respectively.
- Signal characterized in that it comprises a determining step you determine whether a is or nonstandard signal standard signal.
- a field ID signal generating step of generating a field ID signal corresponding to a phase difference between a vertical synchronizing signal of a video signal and a horizontal synchronizing signal of the video signal Correspondingly, a first counting step for counting up the count value circulating in a predetermined range, and a second counting step for counting up the count value circulating in a predetermined range in response to both edges of the field ID signal.
- the count value obtained by the processing of the second count step and the first count step is the first value
- the count value obtained by the processing of the second count step is obtained in accordance with the edge of the vertical synchronization signal.
- the video signal is standardized on the basis of the acquisition step and the count value obtained by the processing of the second count step acquired by the processing of the acquisition step.
- the method is characterized by causing a computer to execute a process including a determination step of determining whether the signal is a signal or a non-standard signal.
- the second video signal processing device of the present invention comprises: a field ID signal generating means for generating a field ID signal in accordance with a phase difference between a vertical synchronizing signal of the video signal and a horizontal synchronizing signal of the video signal; A first counting means for counting up a count value circulating in a predetermined range in response to a signal edge; and a count value circulating in a predetermined range in response to both edges of a field ID signal, respectively.
- a second counting means for counting up, and when the count value of the first counting means is the first value, a count value of the second counting means is obtained corresponding to an edge of the vertical synchronization signal.
- Determining means for determining whether the video signal is a standard signal or a non-standard signal based on the count value of the second counting means obtained by the obtaining means and the obtaining means; If, with respect to the video signal, characterized in that it comprises a noisyzu removing means for removing noisyzu from the video signal by images processing vary depending on the determination result of the determining means.
- the standard signal may be an interlaced video signal in which even fields and odd fields are alternately arranged.
- a second video signal processing method comprises: a field ID signal generating step of generating a field ID signal in accordance with a phase difference between a vertical sync signal of a video signal and a horizontal sync signal of the video signal; A first counting step that counts up a count value circulating in a predetermined range in response to a signal edge, and a count circulating in a predetermined range in response to both edges of the field ID signal, respectively. A second count step for counting up the value, and when the count value obtained by the processing of the first count step is the first value, the second count step is performed in response to the edge of the vertical synchronization signal.
- the program of the second recording medium of the present invention comprises: a field ID signal generating step of generating a field ID signal in accordance with a phase difference between a vertical synchronizing signal of a video signal and a horizontal synchronizing signal of a video signal; A first counting step that counts up a count value circulating in a predetermined range in response to an edge of the synchronization signal; and a cycling in a predetermined range in response to both edges of the field ID signal, respectively.
- a decision step for judging whether the signal is a standard signal or a non-standard signal, and removing noise from the video signal by performing different image processing on the video signal according to the decision result in the processing of the decision step It is characterized by including a noise removal step.
- a field ID signal generating step of generating a field ID signal corresponding to a phase difference between a vertical synchronizing signal of a video signal and a horizontal synchronizing signal of the video signal Correspondingly, a first counting step for counting up the count value circulating in a predetermined range, and a second counting step for counting up the count value circulating in a predetermined range in response to both edges of the field ID signal.
- the count value obtained by the processing of the second count step and the first count step is the first value
- the count value obtained by the processing of the second count step is obtained in accordance with the edge of the vertical synchronization signal.
- the video signal is sampled.
- a determination step for determining whether the signal is a quasi-signal or a non-standard signal, and noise for removing noise from the video signal by performing different image processing on the video signal according to the determination result in the processing of the determination step A process including a removing step is performed by a computer.
- the first count value that generates a field ID signal corresponding to the phase difference between the vertical sync signal of the video signal and the horizontal sync signal of the video signal and circulates in a predetermined range corresponding to the edge of the vertical sync signal Is counted up. Further, the second count value circulated in a predetermined range is counted up corresponding to both edges of the field ID signal. Further, when the first count value is the first value, a second count value is acquired corresponding to the edge of the vertical synchronization signal, and the video signal is obtained based on the acquired second count value. It is determined whether the signal is a standard signal or a non-standard signal.
- a field ID signal is generated corresponding to a phase difference between a vertical synchronization signal of the video signal and a horizontal synchronization signal of the video signal,
- a first count value circulated in a predetermined range is counted up in response to the edge.
- the second count value circulated in a predetermined range is counted up corresponding to both edges of the field ID signal.
- the first count value is the first value
- a second count value is acquired corresponding to the edge of the vertical synchronization signal, and the video signal is obtained based on the acquired second count value. It is determined whether the signal is a standard signal or a non-standard signal. Further, noise is removed from the video signal by performing different image processing on the video signal according to the determination result.
- FIG. 1 is a block diagram showing a configuration example of a cyclic noise reduction device according to an embodiment of the present invention.
- FIG. 2 is a diagram for explaining the interpolation processing by the interpolation filter of FIG.
- FIG. 3 is a diagram for explaining the interpolation processing by the interpolation filter of FIG.
- FIG. 4 is a block diagram showing a configuration example of the non-standard signal detection circuit of FIG.
- FIG. 5 is a flowchart for explaining the non-standard signal detection processing by the non-standard signal detection circuit of FIG.
- FIG. 6 is a timing chart showing the operation of the non-standard signal detection circuit of FIG.
- FIG. 7 is a timing chart showing the operation of the non-standard signal detection circuit of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- the recursive noise reduction device is a device that performs video signal processing, such as a VCR that records and reproduces video signals, a video tuner that supports terrestrial and satellite broadcasting, and a television receiver, such as the NTSC system and the PAL system. It is mounted on a device that processes video signals in the interlaced format.
- the recursive noise reduction device operates in synchronization with a line lock clock locked to a horizontal synchronization signal included in a video signal, and detects that a standard signal or a non-standard signal is input as an input video signal. It is assumed. Here, the standard signal and the non-standard signal will be described.
- a standard signal refers to a normal interlaced video signal. That is, the standard signal is an interlaced video signal in which odd fields and even fields are alternately present. If one horizontal scanning period is 1 H, vertical synchronization is performed between consecutive odd fields and even fields. The horizontal sync pulse positions (phases) are shifted by 0.5 H from each other with reference to the pulse. As a result, a spatial positional relationship between the horizontal lines of the pixels is obtained in an odd field and an even field. In the interlaced video signal, one frame image is formed by interlaced scanning of odd and even fields.
- a non-standard signal is a video signal that is output when, for example, a VC pauses, fast-forwards, rewinds, or performs irregular playback such as a picture search, and the horizontal synchronization is based on a vertical synchronization pulse.
- This is a video signal in which the positions of the pulses are in the same phase in the odd field and the even field.
- FIG. 1 shows a configuration example of a cyclic noise reduction apparatus according to an embodiment of the present invention.
- a digital video signal is input to an input terminal 1.
- This video signal is an interlaced video signal composed of an even field image and an odd field image, as represented by the NTSC system, the PAL system, and the like.
- the input video signal D in input to the input terminal 1 is supplied to the interpolation filter 2 and the subtracter 9.
- the subtractor 9 subtracts a noise component signal input from a non-linear processing circuit 8 described later from the input video signal D in and outputs the result to the output terminal 13 and the field memory 4. As a result, a video signal with reduced noise is output from the output terminal 13.
- the field memory 4 delays the noise-reduced video signal from the subtractor 9 by one field period, and outputs the delayed signal to the interpolation filter 5 as the previous field video signal Dpr.
- the interpolation filter 2 receives the video signal D in of the current field.
- the interpolation filter 2 and the interpolation filter 5 each perform vertical pixel interpolation by setting a predetermined coefficient for each vertical pixel of the input video signal. Note that the coefficient setting in each of the interpolating filter 2 and the interpolating filter 5 is switched alternately at the timing of each field cycle according to the phase relationship between the current field image and the field image one field before this. It has been done.
- the interpolated video signals D p 1 and D p output from the interpolated filters 2 and 5 are obtained.
- the spatial phase relationship of the pixels in the vertical direction is made uniform between the two.
- the interpolation video signal D p 1 at the current field timing from the interpolation filter 2 is written to the work memory 3.
- the interpolated video signal D p 2 delayed by one field from the current field from the interpolation filter 5 is written to the work memory 6.
- interpolation filter 2 basic interpolation processing by interpolation filter 2 and interpolation filter 5 is described. This will be described with reference to FIGS.
- the input video signal D in input to the interpolation filter 2 is a video signal of an odd field f1, as shown in FIG.
- the previous field video signal D pre inputted to the interpolation filter 5 is a video signal of even field ⁇ 2.
- the pixels P 11 and P 12 of the previous field video signal D re that is the even field ⁇ 2 are: They are positioned so that they are spatially displaced alternately in the vertical (vertical) direction.
- the distance from each of the vertically adjacent pixels in one field is equal to the distance of L / 2. This means that the other field pixel is located at the intermediate position.
- the pixels P 1 1 and P 1 2 of the even field f 2 are located at positions below the pixels P 1 and P 2 which are vertically adjacent to the odd field f 1 by a distance of LZ 2 respectively. Is located. Further, the pixel P2 is located at an equal distance LZ2 from the pixels P11 and P12 adjacent to each other in the vertical direction of the even field f2.
- the interpolation filter 2 generates a pixel D ⁇ 1 of the interpolation video signal by using a pixel of the input video signal D in which is an odd field f1.
- the interpolation filter 5 generates pixels of the interpolated video signal Dp2 using the pixel data of the previous field video signal Dpre that is the even field f2.
- the pixel P3 of the interpolated video signal Dp1 is located at a distance of 3: 1 with respect to the interval L between the pixel P1 and the pixel P2 of the input video signal Din (f1) before interpolation. That is, pixel P3 is at a distance of 3 LZ4 from pixel P1 and at a distance of LZ4 from pixel P2. Therefore, the coefficient for interpolation in the interpolation filter 2 in this case is set to 1: 3 accordingly. That is, pixels P 1 and The values of pixel P3 are calculated by weighting and averaging the values of pixels P1 and P2, taking the coefficients corresponding to the values of P1 and P2 as 1/4 and 3/4, respectively.
- the pixel P13 of the interpolated video signal Dp2 is at a distance of 1: 3 with respect to the interval L between the pixel P11 and the pixel P12 of the previous field video signal Dpre (f2) before interpolation. That is, pixel P 13 is at a distance of L / 4 from pixel P 11 and at a distance of 3 LZ 4 from pixel P 12.
- the coefficients for the interpolation in the interpolating filter 5 are set to 3 Z, so that the coefficients corresponding to the values of the pixels P 11 and P 12 are respectively 3
- the value of pixel P 13 is calculated by weighting and averaging the values of pixels P 11 and P 12 with these coefficients.
- each pixel of 2 has the same vertical position.
- Fig. 3 shows the reverse case of Fig. 2, i.e., the input video signal D in input to the interpolation filter 2 is a video signal of an even field f2, and the previous field video input to the interpolation filter 5 This shows a case where the signal D pre is a video signal of the odd field f1.
- the pixels P 1 and P 2 of the input video signal D in that is the even field f 2 the pixels P 1 1 and P 2 of the previous field video signal D pre that is the odd field f 1
- the vertical relationship is different from that in FIG.
- the pixels P 11 and P 12 of the odd field f 1 are located at positions above the pixels P l and P 2 which are vertically adjacent in the even field f 2 by a distance of L / 2, respectively.
- the pixel P1 is located at a distance equal to the pixels P11 and P12 vertically adjacent to the odd field f1.
- the coefficient for interpolation in the interpolation filter 2 in this case is set to 3: 1 accordingly. That is, the value of the pixel P 3 is calculated by weighting and averaging the values of the pixels P 1 and P 2 with the coefficients corresponding to the values of the pixels P 1 and P 2 being / and 1/4, respectively. .
- the pixel P 13 of the interpolated video signal D p 2 is at a distance of 3: 1 with respect to the interval L between the pixel P 11 and the pixel P 12 of the previous field video signal D pre (f 2) before interpolation. That is, pixel P13 is at a distance of 3L_4 from pixel P11 and at a distance of LZ4 from pixel P12.
- the coefficients corresponding to the values of the pixels P 11 and P 12 are respectively set so that the coefficients for the capture in the capture filter 5 are 1: 3 accordingly.
- the value of the pixel P 13 is calculated by weighting and averaging the values of the pixels P 11 and P 12 using these coefficients.
- the pixel of the interpolated video signal D 1 that captures the input video signal D in of the even field f 2 and the interpolated video signal D p 2 that is obtained by interpolating the previous field video signal D pre of the odd field f 1 As shown in the figure, the pixels in the vertical direction are aligned in the vertical direction.
- the interpolation filter 2 uses the coefficient set for the interpolating filter 5 in FIG. 2, and the interpolating filter 5 is set for the interpolating filter 2 in FIG. The calculated coefficients are used.
- Work memories 3 and 6 store delay lines such as delay lines. It is composed of roads.
- the work memories 3 and 6 supply the interpolated video signals D pl and D p 2 to the motion vector detection circuit 10 respectively. Further, the work memories 3 and 6 are configured to supply the intercepted video signals D p 1 and D p 2 to the subtracter 7 for motion compensation processing based on the control from the memory controller 12.
- the motion vector detection circuit 10 applies a block matching method or the like to the interpolated video signals D p 1 and D p 2 having a time difference of one field input from each of the work memories 3 and 6 To detect the motion vector.
- the vector validity Z invalidity determination circuit 11 determines the validity of the motion vector detected by the motion vector detection circuit 10. That is, it is determined whether or not the motion vector detected by the motion vector detection circuit 10 is applied to motion compensation.
- the memory controller 12 controls the reading of the work memories 3 and 6 based on the determination result in the vector valid Z invalid determination circuit 11. That is, when the motion vector is determined to be valid by the vector validity Z invalidity determination circuit 11, the memory controller 12 performs a motion compensation process corresponding to the motion vector on the interpolated video signal. Then, a motion compensation control signal is output to work memories 3 and 6.
- the video signal read from each of the work memories 3 and 6 based on the control from the memory controller 12 is supplied to the subtracter 7.
- the subtracter 7 calculates a difference signal obtained by subtracting the video signal from the work memory 6 from the video signal from the work memory 3 and outputs the difference signal to the nonlinear processing circuit 8 as a motion-compensated signal.
- the nonlinear processing circuit 8 performs an attenuation process on the difference signal from the subtracter 7 using a predetermined characteristic curve. That is, by extracting a signal component having a small amplitude from the difference signal from the subtractor 7, a noise component signal composed of a noise component is extracted as a result. The extracted noise component signal is output to the subtractor 9.
- the subtracter 9 subtracts the noise component signal from the input video signal Din. In this way, the signal subjected to subtraction in the subtractor 9 is This is output from the output terminal 13 as a video signal with reduced noise. Also, by being written to the field memory 4, it is used for noise reduction processing at the next field timing.
- the field ID generation circuit 21 receives the horizontal synchronization signal and the vertical synchronization signal xVD corresponding to the current video signal input to the recursive noise reduction apparatus, and converts the standard signal (interlaced video signal) into a signal.
- a field ID that detects that the phase of the vertical sync signal is 0.5 H shifted from the horizontal sync signal in each vertical sync section, and alternately takes H (High) level or L (Low) level for each field
- the signal AFD is generated and output to the non-standard signal detection circuit 22.
- the field ID signal output from the field ID signal generation circuit 21 continuously takes H level or L level. Further, the field ID generating circuit 2 1, the preceding vertical synchronizing signal X A VD obtained by delaying the vertical synchronizing signal XVD corresponding to the current video signal by 1 H, and outputs a non-standard signal detection circuit 2 2.
- the non-standard signal detection circuit 22 includes a vertical synchronization signal xVD corresponding to the current video signal input to the recursive noise reduction apparatus, a preceding vertical synchronization signal xAVD from the field ID generation circuit 21 and a field synchronization signal. Using the field ID signal AFD from the ID generation circuit 21 as input, determine whether the video signal input to the cyclic noise reduction device is a standard signal or a non-standard signal, and a non-standard signal indicating the determination result The detection signal is output to the interpolation filters 2 and 5, and the nonlinear processing circuit 8.
- the preceding vertical synchronizing signal XAVD and the vertical synchronizing signal XVD are signals that take the L level only for one clock in one vertical cycle, as shown in A and B of FIG. It is assumed that the field ID signal AFD changes in synchronization with the rising edge of the preceding vertical synchronization signal xAVD as shown in FIG.
- the interpolation in which the non-standard signal detection signal is input is performed.
- the filter 2, the intercepting filter 5, and the nonlinear processing circuit 8 operate as described above, but the non-standard signal detection signal indicates that the video signal input to the recursive noise reduction device is a non-standard signal.
- the same coefficient is used for the interpolation by the interpolation filter 2 and the interpolation by the interpolation filter 5, and the interpolating process by the interpolation filter 2 and the interpolating filter 5 is not executed.
- One of three types of processing is performed, namely, processing that sets the output (noise component signal) of the non-linear processing circuit 8 to 0 so that noise removal is not substantially performed.
- the control circuit 23 reads a control program stored in the recording medium 24, and controls each circuit constituting the cyclic noise reduction device based on the read control program.
- FIG. 4 shows a configuration example of the non-standard signal detection circuit 22.
- the leading vertical sync signal XAVD is input to the free-running vertical sync edge counter 31, and the field ID signal AFD is input to the free-running field ID edge counter 32, and the vertical sync signal x VD is input to the comparison circuit 33.
- the free-running vertical sync edge counter 31 increments the count value circulating from 0 to 7 by 1 in synchronization with the edge of the preceding vertical sync signal XAVD, and increments the count value by the free-running field ID edge counter 32 and the comparison circuit. 3 Output to 3.
- the free-running field ID edge counter 32 increments the count value by one in synchronization with the rising edge and the falling edge of the field ID signal AFD.
- the self-running field ID edge counter 32 when the count value of the self-running vertical synchronization edge counter 31 (hereinafter referred to as V count value) is 7, as well as at the start of operation, Resets its own count value (hereinafter referred to as the FD edge count value) to 0 in synchronization with the rising edge.
- the comparison circuit 33 has a non-standard signal detection signal (indicating a non-standard signal) corresponding to the FD edge count value at the timing when the V count value is 7 and the vertical synchronization signal XVD indicates the L level. In this case, take the H level and use a standard signal. If it indicates, take L level) and output to the subsequent stage.
- the non-standard signal detection process is started when a video signal is input to the cyclic noise reduction device.
- step S1 the self-running vertical synchronizing edge counter 31 and the self-running field ID edge counter 32 each reset their force value to 0, and then start counting in synchronization with a predetermined signal.
- step S2 the comparison circuit 33 determines whether or not the V count value is 7 and the timing at which the vertical synchronization signal XVD indicates the L level, and if the V count value is 7 and the vertical It waits until it is determined that the timing of the synchronization signal x VD indicates the L level. If the V count value is 7 and it is determined that the timing at which the vertical synchronization signal XVD indicates the L level, the process proceeds to step S3.
- step S3 the comparison circuit 33 determines whether or not the FD edge count value is 7. If it is determined that the FD edge count value is 7, the process proceeds to step S4. In step S4, the comparison circuit 33 outputs the non-standard signal detection signal as an L level to the subsequent stage so as to indicate that the currently input video signal is a standard signal. The process returns to step S2, and the subsequent processes are repeated.
- step S3 If it is determined in step S3 that the FD edge count value is not 7, the processing proceeds to step S5.
- the comparison circuit 33 determines whether or not the FD edge count value is 0. If it is determined that the FD edge count value is 0, the process proceeds to step S6.
- step S6 the comparison circuit 33 outputs the non-standard signal detection signal as an H level to the subsequent stage so as to indicate that the currently input video signal is a non-standard signal. The process returns to step S2, and the subsequent processes are repeated.
- step S5 If it is determined in step S5 that the FD edge count value is not 0, that is, if the FD edge count value is 1 to 6, the process proceeds to step S7. move on.
- step S7 the comparison circuit 33 maintains the level of the non-standard signal detection signal currently being output.
- the soft decision that maintains the previous decision result is employed, so that the standard / non-standard decision does not frequently change. A stable determination will be made. The process returns to step S2, and the subsequent processes are repeated.
- FIGS. 6 and 7 show timing charts showing the operation of the non-standard signal detection circuit 22.
- A is the vertical sync signal XVp
- B is the preceding vertical sync signal XAVD
- C is the V count value
- D is the preceding field ID signal AFD
- E is the preceding Field ID signal Both edges of AFD
- F indicates FD edge count value
- G indicates non-standard signal detection signal.
- FIG. 6 shows an example in which, after it is determined that a video signal has changed from a standard signal to a non-standard signal, the determination as a non-standard signal is held by soft decision.
- FIG. 7 shows an example in which the video signal is determined to have changed from a standard signal to a non-standard signal, and then returned to the standard signal.
- the above-described series of processes can be executed by hardware, but can also be executed by software.
- the programs that make up the software must execute various functions by installing a computer built into dedicated hardware or by installing various programs.
- a recording medium 24 is provided separately from the computer to be distributed to provide the program to the user. Only Memory), DVD (including Digital Versatile Disc), Magneto-Optical Disk (including MD (Mini Disc)), or packaged media consisting of semiconductor memory, etc., as well as pre-installed in the computer
- the program, which is provided to the user in the, is recorded: It is composed of ROM, hard disk, etc. 'In this specification, the steps for describing a program recorded on a recording medium are not limited to processing performed in chronological order according to the described order, but are not necessarily performed in chronological order. It also includes processes that are executed individually. Industrial applicability
- a circuit having a simple circuit configuration and capable of stably determining whether an input video signal is a standard signal or a non-standard signal is realized. It becomes possible.
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP03720986A EP1501287A4 (en) | 2002-05-02 | 2003-04-28 | DEVICE AND METHOD FOR PROCESSING VIDEO SIGNALS, RECORDING MEDIUM, AND PROGRAM |
US10/482,675 US7092034B2 (en) | 2002-05-02 | 2003-04-28 | Video signal processing device and method, recording medium, and program |
KR10-2003-7017222A KR20050013052A (ko) | 2002-05-02 | 2003-04-28 | 영상 신호 처리 장치 및 방법, 기록 매체, 및 프로그램 |
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JP2002130583A JP3796751B2 (ja) | 2002-05-02 | 2002-05-02 | 映像信号処理装置および方法、記録媒体、並びにプログラム |
JP2002-130583 | 2002-05-02 |
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EP (1) | EP1501287A4 (ja) |
JP (1) | JP3796751B2 (ja) |
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JP3693104B2 (ja) * | 2001-09-14 | 2005-09-07 | ソニー株式会社 | 映像信号処理装置、及び映像信号処理方法 |
KR20060084849A (ko) * | 2003-09-04 | 2006-07-25 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 비디오 신호들의 견고한 디인터레이싱 |
JP2006019950A (ja) * | 2004-06-30 | 2006-01-19 | Toshiba Corp | 映像信号処理装置及び映像信号処理方法 |
JP4973031B2 (ja) * | 2006-07-03 | 2012-07-11 | ソニー株式会社 | ノイズ抑圧方法、ノイズ抑圧方法のプログラム、ノイズ抑圧方法のプログラムを記録した記録媒体及びノイズ抑圧装置 |
KR20100111467A (ko) * | 2009-04-07 | 2010-10-15 | 삼성전자주식회사 | 영상 데이터의 타입을 판정하는 영상기기 및 이에 적용되는 영상처리방법 |
CN113965662A (zh) * | 2021-10-26 | 2022-01-21 | 歌尔科技有限公司 | 音视频输出设备及其音视频延时校准方法及相关组件 |
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- 2002-05-02 JP JP2002130583A patent/JP3796751B2/ja not_active Expired - Fee Related
-
2003
- 2003-04-28 KR KR10-2003-7017222A patent/KR20050013052A/ko not_active Application Discontinuation
- 2003-04-28 WO PCT/JP2003/005488 patent/WO2003094507A1/ja not_active Application Discontinuation
- 2003-04-28 EP EP03720986A patent/EP1501287A4/en not_active Withdrawn
- 2003-04-28 CN CNB038007479A patent/CN1272958C/zh not_active Expired - Fee Related
- 2003-04-28 US US10/482,675 patent/US7092034B2/en not_active Expired - Fee Related
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JP2001054070A (ja) * | 1999-08-05 | 2001-02-23 | Matsushita Electric Ind Co Ltd | 磁気記録再生装置 |
JP2001285808A (ja) * | 2000-03-28 | 2001-10-12 | Fuji Photo Film Co Ltd | 画像処理装置および画像処理方法 |
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Also Published As
Publication number | Publication date |
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JP2003324630A (ja) | 2003-11-14 |
US7092034B2 (en) | 2006-08-15 |
EP1501287A4 (en) | 2005-11-23 |
JP3796751B2 (ja) | 2006-07-12 |
CN1547846A (zh) | 2004-11-17 |
US20040196407A1 (en) | 2004-10-07 |
EP1501287A1 (en) | 2005-01-26 |
KR20050013052A (ko) | 2005-02-02 |
CN1272958C (zh) | 2006-08-30 |
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