WO2003092233A1 - Procede et dispositif de mise en forme de signaux qpsk - Google Patents

Procede et dispositif de mise en forme de signaux qpsk Download PDF

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Publication number
WO2003092233A1
WO2003092233A1 PCT/US2002/012806 US0212806W WO03092233A1 WO 2003092233 A1 WO2003092233 A1 WO 2003092233A1 US 0212806 W US0212806 W US 0212806W WO 03092233 A1 WO03092233 A1 WO 03092233A1
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WIPO (PCT)
Prior art keywords
coefficient
value
address
output
coupled
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PCT/US2002/012806
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English (en)
Inventor
Steven Washakowski
Wesley G. Brodsky
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Raytheon Company
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Publication date
Application filed by Raytheon Company filed Critical Raytheon Company
Priority to AU2002252711A priority Critical patent/AU2002252711B2/en
Priority to JP2004500460A priority patent/JP2005524282A/ja
Priority to PCT/US2002/012806 priority patent/WO2003092233A1/fr
Priority to US10/511,862 priority patent/US7346125B2/en
Priority to CA002483985A priority patent/CA2483985A1/fr
Priority to EP02721801A priority patent/EP1497962A1/fr
Publication of WO2003092233A1 publication Critical patent/WO2003092233A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03834—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using pulse shaping

Definitions

  • This invention relates generally to modulation of RF carrier signals and more particularly to systems and techniques to shape baseband signals for QPSK modulation.
  • SRRC square root raised cosine
  • Typical filter circuits include a tapped delay line filter having filter taps spaced at l/(F da ) in time. Inputs bits come in at a symbol rate (Rs).
  • Rs symbol rate
  • the filter coefficients are chosen so that a response to an impulse signal is the SRRC characteristic waveform in the time domain.
  • RF radio frequency
  • This impulse signal consists of the value +1 (for a data "0") or -1 (for a data "1") followed by several samples of value 0.
  • +1 for a data "0”
  • -1 for a data "1”
  • Digital filters such as those described above are often implemented as field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs). Reducing the required circuitry to implement a particular filter can reduce the cost and size of the filter.
  • a device in accordance with the present invention, includes a plurality of coefficient memories, and each memory having an input address bus, a multiplexor input and a coefficient value output.
  • the device further includes a plurality of first shift registers, each having an input coupled to a respective one of the coefficient value outputs, a digital to analog (D/A) clock input and an output.
  • the device further includes a plurality of negative value circuits, each circuit having an input coupled to a respective
  • the device further includes a plurality of second shift registers, each having an input coupled to a respective one of the outputs of the plurality of 2:1 multiplexors, a digital to analog (D/A) clock input and an output, and an adder having a plurality of inputs coupled to respective ones of the plurality of second shift registers.
  • D/A digital to analog
  • a method for shaping a baseband signal includes providing a plurality of coefficient memories, each coefficient memory having a plurality of coefficients values, each of the plurality of coefficient values representing a filter response waveform value, and determining a coefficient memory address for each of the coefficient memories.
  • the method further includes addressing each of the plurality of coefficient memories, retrieving an addressed coefficient value from each of the plurality of coefficient memories, providing a negative value for each of the retrieved coefficient values, selecting in response to the baseband signal, one of the retrieved value and the negative value, summing the selected value for each coefficient for providing a shaped signal.
  • FIG. 1 is a block diagram of a data path processing circuit of a QPSK modulator according to the invention
  • FIGs. 2A-2D are schematics of a baseband shaping circuit according to the invention
  • FIG. 2E is a schematic of one stage of the baseband shaping circuit of FIGs.
  • FIGs. 3A-3C are schematics of a baseband shaping circuit according to a further aspect the invention.
  • FIG. 3D is a schematic of one stage of the baseband shaping circuit of FIG. 3.
  • FIGs. 4A-4D are schematics of a baseband shaping circuit according to a still further aspect of the invention. DETAILED DESCRIPTION OF THE INVENTION
  • two's complement logic coefficients and logic blocks refer to a negative representation of a digital signal value and in particular the negative value of a filter coefficient.
  • conventional logic building blocks for adders use two's complement arithmetic. It will be appreciated by those of ordinary skill in the art that other representations of the negative coefficient such as offset binary or signed magnitude representations can be used instead of the two's complement representation along with corresponding negative value logic circuits.
  • coefficient refers generally to a factor which is used to multiply an input bit stream for implementing a specific filter.
  • a coefficient includes a plurality of coefficient values which are discrete digital samples representing filter response waveform values of a particular filter waveform.
  • CO represent the first coefficient to be used in a specific filter.
  • Coefficient values CO O -CO N represent discrete samples of the coefficient, and these values are stored in a coefficient memory. The coefficient values are addressed by the coefficient, here CO, and the sample number 0 to N. N is determined by the relationship between the symbol rate and the D/A converter clock rate. For example, if the D/A clock rate is sixteen times the symbol rate, then N would be equal to fifteen and there would be sixteen samples per coefficient.
  • One inventive concept of this present invention resulted from the realization that because of the symmetry of the filter coefficients the storage requirements for coefficient values could be reduced.
  • coefficients are combined to reduce, for example by one-half, the amount of memory required to store baseband signal shaping filter values.
  • Address generation circuitry is provided to address the coefficient memories to provide the coefficient values in the proper order in response to the baseband signals.
  • an exemplary QPSK modulator 100 includes a transmit data interface 102 coupled to an in-phase baseband bit shaping circuit 1041 and a quadrature baseband bit shaping circuit 104Q (generally referred to as baseband bit shaping circuits 104).
  • the baseband bit shaping circuits 1041 and 104Q each include an input to receive a serial bit stream provided by a plurality of in-phase data symbols and quadrature data symbols respectively.
  • the baseband bit shaping circuits 1041 and 104Q each receive timing and control signals from timing and control circuit 118 including a master clock signal, a digital to analog converter (D/A) clock signal and a symbol (SYM) clock input, and each circuit 1041 and 104Q includes a D/A output.
  • D/A digital to analog converter
  • SYM symbol
  • the QPSK modulator 100 further includes a pair of digital to analog converters (D/A) 106 each coupled to one of the respective baseband bit shaping circuits 1041 and 104Q D/A outputs.
  • the D/As are coupled to an RF modulator 108 which is coupled to an upconvertor 110.
  • the upconvertor 110 is coupled to a power amplifier 112 which is coupled to a diplexer 114 which is coupled to an antenna 116 in a known manner.
  • the QPSK modulator 100 including portions of the transmit data interface 102 and the baseband bit shaping circuits 104 are implemented in a field programmable gate array (FPGA) in a satellite communications modulator.
  • the transmit data interface 102 and the baseband bit shaping circuits 104 process the data (grouped as symbols) and provide the processed signals as discrete digital waveform values to the dual D/A's 106.
  • the transmit data interface 102 provides serial data to the baseband bit shaping circuits 104 to provide the in phase and quadrature waveforms to modulate a radio frequency carrier.
  • the transmit data interface 102 selects between a synchronous serial interface or asynchronous parallel interface for transmit data.
  • the external transmit circuitry Utilizing the synchronous serial interface, the external transmit circuitry provides two bits of each data symbol (multi-bit binary data), including one bit I and one bit Q on each rising edge of the clock symbol clock provided by the timing and control circuit 118.
  • asynchronous parallel interface data to be transmitted is delivered as symbols to the transmit data interface 102 through the byte wide control/status bus and buffered in a first-in first-out register (FIFO) (not shown).
  • FIFO first-in first-out register
  • the FIFO which is implemented as part of the transmit data interface 102, allows an external processor (not shown) to send multiple bytes of message data to the transmit data interface 102 prior to transmission.
  • the byte wide output of the FIFO is then parallel to serial converted into two bit symbols for QPSK modulation on each rising edge of the clock symbol clock. It will be appreciated that the exemplary embodiment of FIG. 1 illustrates one of several possible configurations for the QPSK modulation 100.
  • the baseband bit shaping circuits 104 shapes the serial data supplied by the transmit data interface and provides the digital waveform representing the filtered baseband signals to the digital to analog converters 106.
  • the digital to analog converters 106 provide an analog waveform to the RF modulator 108 to modulate an RF carrier signal which is converted to a higher frequency by the upconvertor 110.
  • the power amplifier 112 amplifies the upconverted signal which is then received by the diplexer 114. In a transmit mode, the diplexer 114 directs the amplified upconverted signal to the antenna for transmission.
  • an in-phase baseband bit shaping circuit 2001 similar to the baseband bit shaping circuit 1041 (FIG. 1), includes a tapped delay line 2021 having a plurality of delay elements 203 and a plurality of taps 205 and coupled to an in-phase data bit stream.
  • the circuit 2001 further includes a plurality of stages 204a- 204n (generally referred to as stage 204), each stage coupled to a corresponding tap 205 of the delay line 2021.
  • Each stage 204 has an output coupled to a corresponding input of an adder 2061 which has an output coupled to an input of a sealer circuit 2081.
  • the sealer 2081 has an output which is coupled to an in-phase D/A (not shown).
  • a quadrature baseband bit shaping circuit 200Q includes a similar arrangement of circuits.
  • the quadrature baseband bit shaping circuit 200Q similar to the baseband bit shaping circuit 104Q (FIG. 1), includes a tapped delay line 202Q having a plurality of delay elements 213 and a plurality of taps 215 and coupled to an quadrature data bit stream.
  • the circuit 200Q further includes a plurality of stages 214a-214n (generally referred to as stage 214), each stage coupled to a corresponding tap 215 of the delay line 202Q.
  • Each stage 214 has an output coupled to a corresponding input of an adder 206Q which has an output coupled to an input of a sealer circuit 208Q.
  • the sealer 208Q has an output which is coupled to an in-phase D/A (not shown).
  • each stage 204 of the baseband shaping circuit 2001 of FIGs. 2A-2D includes a coefficient memory 220 coupled to a coefficient address generator 228 through an address bus 230.
  • the coefficient memory 220 includes a clock input signal 232 coupled to the coefficient address generator 228.
  • the coefficient memory 220 includes coefficient memory output 222 which is coupled to a first input of a multiplexor 226.
  • the coefficient memory is also coupled to a negative value circuit 224, here, a two's complement circuit to provide a negative value of the coefficient memory output 222 to a second input of the multiplexor 226.
  • the multiplexor 226 includes a select input 234 coupled to the corresponding tap 205 of the delay line 202 (FIGs.
  • the baseband bit shaping circuits 200 provide the digital signal processing necessary for spectral confinement of the modulated output carrier.
  • the coefficient address generator 228 is clocked by the D/A clock to provide coefficient addresses for addressing the coefficient memories to provide waveform samples at the D/A clock frequency.
  • the baseband bit shaping waveform is a square root raised cosine (SRRC) waveform with various roll-off factors. In one embodiment the roll-off factor is selectable at 25%, 35%, 50% and 70%.
  • SRRC square root raised cosine
  • the roll-off factor is held constant during a single transmission of a series of symbols which is referred to as a burst.
  • Different sets of coefficient values are stored in the coefficient memory 220 for each roll-off factor. It will be appreciated by those of ordinary skill in the art that several memory arrangements can be provided including loading different sets of coefficient values into the memory 220 when different roll-off factors are selected or having a single larger memory with a different section for each set of coefficient values.
  • the coefficient address generator 228 addresses the selected set of coefficient values in the coefficient memory 220.
  • a particular roll-off factor is selected for a particular burst as a function of transmission bandwidth, and transmitter power amplifier 112 (FIG. 1), and receiver complexity.
  • Lower roll-off factors (e.g.; 25%) use less of the link bandwidth which is advantageous because the lower roll-off factor allows more of the limited bandwidth available to be used by other links.
  • the lower-roll off factor causes a higher ratio of peak transmitted power to average transmitted power. The higher ratio requires the transmitter power amplifier to have a higher peak power capability, which makes it more complex.
  • the lower roll-off factor requires a longer matched filter in the receiver which will receive the transmitted waveform. This makes the receiver more complex.
  • Higher roll-off factors (e.g.; 70%) use more of the link bandwidth which is disadvantageous because the higher factor allows less of the limited bandwidth available to be used by other links. But, the higher roll-off factor causes a lower ratio of peak transmitted power to average transmitted power.
  • the lower ratio allows the transmitter power amplifier have a lower peak power capability, which makes it less complex.
  • the lower roll-off factor requires a shorter matched filter in the receiver which will receive the transmitted waveform. This makes the receiver less complex. Providing the flexibility of switching between coefficient memories can require additional storage capacity, but the total storage requirements are reduced by the present invention. It will be appreciated by those of ordinary skill in the art, that once the coefficients are provided according to the present invention, memory banks or other arrangements of the coefficients corresponding to different roll-off factors can be selected using known techniques and the tradeoffs described above.
  • the stage 2041 operates as one tap of a digital filter having a tapped delay line structure which is, here, eight symbols in length with a predetermined set of coefficients for each tap based on the desired roll-off factor.
  • the data is multiplied by the coefficients, with the results from each tap summed in adder 2061, scaled by the sealer circuit 2081 and then used to drive the D/A converters 106 (FIG. 1).
  • This structure is similar for both the I and Q channels.
  • the stage 2041 is an interpolating filter tap, so for every symbol processed by the filter, there are N ⁇ T samples in the waveform provided to the D/A converter 106, where
  • N INT (D/A Clock Rate)/(Symbol Rate);
  • N INT N+1 ;
  • N refers to the sample number described above.
  • the symbol bit coefficients are "multiplied" by changing or not changing their sign, according to the value (+1 or -1) of each symbol. In one embodiment using twos complement arithmetic, this operation corresponds to using the coefficient value or its "two complement" value. Note that each symbol multiplies each coefficient only once. The effect is the same as if the filter was an 8 N IN long tapped delay line filter (for an 8-tap filter), with impulses (+1 or — 1 followed by [NIN T -1] OS) as the input to the tapped delay line.
  • the +1 or -1 is repeated INT times.
  • the transmitted spectrum of the waveform would be multiplied by a [sine(fx)/(fx)] function, which is defined as "sinc(fx)."
  • f is the frequency offset from the carrier and x is a factor which depends on the symbol rate.
  • a schematic of a baseband shaping circuit 300 includes tapped delay lines 3021 and 302Q similar to the delay line 2021 and 202Q of FIGs. 2 A-2D respectively.
  • the tapped delay lines 3021 and 302Q are coupled to an in-phase data bit stream (I Data) and a quadrature data bit stream (Q Data) respectively.
  • the circuit 300 further includes a plurality of stages 304a-304n, each stage coupled to a corresponding tap of delay line 3021 and302Q.
  • Each stage 304 has outputs coupled to a corresponding input of an adder/sealer circuit 3061 and of 306Q respectively.
  • the adder/sealer 3061 and 306Q have outputs which are coupled to an in-phase D/A (not shown) and quadrature D/A (not shown) respectively.
  • the circuit 300 includes a common coefficient address generator 308 having a clock input 310 which is coupled to the D/A sample clock, and an up address output 312 coupled to the coefficient memories of a first portion of the stages 304 and a down address output 314 coupled to the coefficient memories of a second portion of the stages 304.
  • a first plurality of stages 304 is coupled to an up address bus 312 coupled to the coefficient address generator 308 which is clocked by the D/A clock.
  • the coefficient address generator 308 is also coupled to a down address bus 314 coupled to a second plurality of the stages 304.
  • One inventive feature of the baseband shaping circuit 300 takes advantage of the fact that the same coefficients are used for each corresponding tap in the I and Q channels, thus allowing logic (e.g. address generators and multiplexors) and coefficient memories to be shared for both the I and Q channels.
  • logic e.g. address generators and multiplexors
  • each stage 304 of the baseband shaping circuit 300 of FIGs. 3A-3C includes a coefficient memory 320 coupled to the coefficient address generator 308 by address bus 330.
  • the coefficient memory 320 is coupled by the address bus 330 to a corresponding one of the up address bus 312 or the down address bus 314 as necessary.
  • the coefficient memory 320 is coupled to a coefficient memory output register 322 which is coupled to a first input of a multiplexor 3261 and a first input of a multiplexor 326Q.
  • the coefficient memory 320 is also coupled to a negative value circuit 324, here, a two's complement circuit to provide a negative value of the coefficient memory output 322 to a second input of the multiplexor 3261 and a second input of the multiplexor 326Q.
  • the multiplexor 3261 includes a select input 3341 coupled to the corresponding tap of the delay line 3021 (FIGs. 3A-3C) and an output 3401.
  • the multiplexor 326Q each includes a select input 334Q coupled to the corresponding tap of the delay line 302Q (FIGs. 3A-3C) and an output 340Q.
  • the address generator 308 provides an incrementing address, up address output 312 (starting at 0 and increasing) and a decrementing address, down address output 314 (starting at the maximum value and decreasing) to address the coefficient memories 320, taking advantage of the symmetry of the coefficients but reverse ordering to provide the symmetrically shaped waveform.
  • Stage 304 operates in a similar manner as stage 204 (described above in conjunction with FIG. 2E) with the additional feature of providing the addressed coefficient values and the negative coefficient values to both I data stream and the Q data stream at a rate clocked by the D/A clock.
  • an exemplary baseband shaping circuit 400 provides an inventive coefficient storage technique.
  • Circuit 400 includes a coefficient address generator 416 providing an address bus and a plurality of multiplexor most significant bit (MSB) outputs coupled to a multiplexor (MSB) input of a corresponding one of a plurality of coefficient memories 420a-420n (generally referred to as coefficient memory 420).
  • Outputs of the plurality of coefficient memories 420a-420n are coupled to a corresponding plurality of stages 418a- 418n (each stage generally referred to as stage 418) each having an in phase (I) output and a quadrature (Q) output.
  • I in phase
  • Q quadrature
  • the in-phase (I) outputs are coupled to corresponding stages of adders 4501 and 4521 having an output coupled to a scale and format converter 4701 which has an output coupled to an I D/A converter (not shown).
  • the quadrature (Q) outputs are coupled to corresponding stages of adders 450Q and 452Q having an output coupled to a scale and format converter 470Q which has an output coupled to a Q D/A converter (not shown).
  • the coefficient address generator 416 includes a plurality of multiplexors 402o 7 -402 3 (generally referred to as multiplexors 402), each of the multiplexors 402 having I and Q inputs coupled to corresponding outputs of a two stage I Channel input data (symbol) shift register 4401 and a two stage Q Channel input data (symbol) shift register 440Q.
  • the two stage shift registers 44OI and 44OQ include a shift registers 4421, 4441 and 442Q, 444Q respectively coupled in series and in parallel to provide I channel data and Q channel data each clocked by both the symbol clock and the D/A clock as shown in FIG. 4C.
  • the overall operation and signal flow of the circuit 400 starts with the I channel and Q channel shift registers 4401 and 440Q respectively in FIG. 4C.
  • the eight individual registers 4421a - 442Ig and 442Qa - 442Qg, respectively for each channel represent the eight taps of the delay line in the filter.
  • Symbol data is clocked into the "delay line" at the symbol clock rate.
  • the outputs of these registers 442 provide the inputs to the multiplexors 402 in the address generator 416 of FIGS. 4A- 4B and remain constant for the entire symbol period.
  • the same coefficient memory 420 is used to generate coefficients for both the I and Q channels during each D/A clock cycle. In the first half of the D/A clock cycle, the I channel coefficients are generated, then in the second half of the D/A clock cycle the Q channel coefficients are generated.
  • the outputs of these registers 442 also provide inputs to corresponding inputs of registers 444Ia-444Ig and 444Qa-444Qg (collectively referred to as registers 444).
  • the outputs of registers 444 provide outputs I0D-I7D, Q0D-Q7D as inputs to a digital logic circuit implementing the truth table shown in Table II which provides the SELI07- SELQ07, SELI16, SELQ16, etc.
  • the I0D-I7D, Q0D-Q7D output signals are the 10-17, Q0-Q7 signals delayed one D/A clock cycle to provide the correct timing relationship with respect to the coefficient memory 420 output.
  • the 10 and 17 outputs of registers 442a and 442g are selected by the state of SEL I/Q and are passed through multiplexor 402 u7 to the inputs of XOR gate 404 07 .
  • the Q0 & Q7 outputs of registers 442 are selected and passed through the multiplexor 402n 7 to the XOR gate 404 07 .
  • the output of the XOR gate 404 07 forms the most significant bit of the address into the coefficient memory as described in Table I below.
  • the XOR gate determines whether the symbol bits 10 & 17 have the same value (same value means same sign positive or negative). If symbol bits 10 & 17 have the same value , the coefficient value to be selected from the coefficient memories 420a is the 10 + 17 coefficient. If symbol bits 10 & 17 have different values (opposite signs), the 10 - 17 coefficient is selected. The desired coefficient is then accessed in the coefficient memories 420a and stored in the register 430 on the rising edge of the D/A clock.
  • the registers 430 are shown in FIG. 4A having the rising clock edge storage and positive (digital "1") enable (EN).
  • Signal 4341 SELI07 is generated by logic implementing a truth table as described in Table II below.
  • the multiplexor 426 provides true output of the register 430 for the first half of the samples for the current symbol (e.g. if there are eight D/A samples per symbol, the first half would be samples 0, 1, 2 and 3 and the second half would be 4, 5, 6 and 7).
  • the multiplexor 426 provides the negative (two's complement) output 424 of the register 430 for the second half of the samples.
  • the coefficient memory 420 provides either the coefficient value 10 + 17 or 10 - 17.
  • the signal 4341 SELI07 then selectively provides the two remaining coefficient combinations - (10 + 17) or (17 - 10).
  • the address counter most significant bit (ACCMSB) signal changes from a binary digital logic "1" to a "0" when there is a transition from the first half of the samples for a symbol to the second half of the samples.
  • the output is stored in registers 432 which provide the coefficient values as input to the adder chains 460 of FIG. 4D.
  • Each of the multiplexors 402 has two outputs which are coupled to two inputs of an exclusive or logic (XOR) gate 404 and the output of the logic gate 404 is coupled to the multiplexor (MSB) input of the corresponding coefficient memory 420.
  • the coefficient address generator 416 further includes a register 406 coupled to a modulator control/status bus and having an output coupled to an input of a multiple bit adder 408, here a six bit adder.
  • the adder 408 has an output coupled to a register 410 which has a clock input coupled to the D/A clock.
  • the register 410 has a first output which is the sum produced by the adder and each of the lower bits, here the lower five bits, which are coupled to a first input of an XOR gate array 412.
  • the register 410 has a second output which is the most significant bit produced by the adder 408 and is coupled to a second input of the XOR gate array 412 and to a second input of the adder 408.
  • the XOR gate array 412 has a multiple bit output which is coupled to the address bus input of the corresponding coefficient memory 420. Each lower order bit in the output of adder 408 is XOR'ed with the most significant bit produced by the adder 408. Equivalently in Table I, the XOR gate array 412 converts the ADDRESS to the corresponding NEW ADDRESS, which is combined, example with the output of the XOR gate 404o7 to provide the MEMORY ADDRESS for addressing the coefficient memory 420.
  • Each stage 418 which is similar to stage 304 (FIGs. 3A-3C), includes a pair of registers 4301 and 430Q, each register having a coefficient input coupled to a corresponding coefficient memory 420, a clock input coupled to the D/A clock and an enable input coupled to a SEL IQ.
  • the clock input to register 430Q is inverted by an inverter 427.
  • Each of the pair of registers 4301 and 430Q has an output coupled to a first input of a multiplexor 4261 and a multiplexor 426Q respectively.
  • the output of registers 4301 and 430Q is also coupled to negative value circuits 424, here, two's complement circuits to provide a negative value of the coefficient in registers 4301 and 430Q as outputs to respective second inputs of the multiplexor 4261 and the multiplexor 426Q.
  • the multiplexor 4261 includes a select input 4341 coupled to a SEL I/Q XY signal, and the multiplexor 4261 has a COEFF I XY output.
  • the multiplexor 426Q each includes a select input 434Q coupled to a SEL I/Q XY signal and a COEFF Q XY output.
  • a register 414 of the coefficient address generator 416 has an input coupled to the most significant bit produced by the adder 408 and a clock input coupled to the D/A clock, and provides a signal ACCMSBD to logic implementing a truth table (described below in more detail in conjunction with Table II) to provide the SEL I/Q XY signals.
  • the first adder stage 4501 includes a plurality of adders 460 having a pair of input coupled to the corresponding pair of COEFF I/Q XY outputs from stage 418, and an output coupled to a pipelined register 462.
  • the register 462 has an output coupled to an input of an adder 460 in a second adder stage 4521. It will be appreciated by those of ordinary skill in the art that the number and configuration of the adder stages 4501 and 4521 can be provided in several equivalent arrangements.
  • the first adder stage 450Q includes a plurality of adders 460 having a pair of input coupled to the corresponding pair of COEFF I/Q XY outputs from stage 418, and an output coupled to a pipelined register 462.
  • the register 462 has an output coupled to an input of an adder 460 in a second adder stage 452Q.
  • the number and configuration of the adder stages 450Q and 452Q can be provided in several equivalent arrangements.
  • the circuit 400 takes advantage of the symmetry in the coefficients (i.e. the same coefficient set is used for CO and C7, Cl and C6, C2 and C5, C3 and C4). It should be noted that some coefficients are accessed in reverse order to provide the trailing portion of the filter waveform. Further combining the coefficient pairs by storing the sums and differences in the coefficient memories 420 rather than the individual coefficients cuts coefficient storage requirements in half and an additional adder stage can be eliminated. Table I illustrates this coefficient storage approach for a sixteen coefficient values for each of eight filter tap coefficients.
  • the coefficient memory addresses are generated by the coefficient address generator 416 operating as a counter that counts the desired number of D/A samples per symbol (here up to the maximum number of 64 which is equal to the size of coefficient memory 420). The increment of the count varies based on the number of samples per symbol divided into the maximum number of 64. Register 406 is loaded with the selected increment. Therefore, for a given transmission rate generating D/A samples at a rate of 16 samples per symbol, the counter would increment by 4 each D/A clock cycle, thereby using every fourth coefficient value in the coefficient memory 420.
  • the address counter is implemented as an adder/accumulator where the increment is provided as input to the accumulator and the accumulated "sum" forms the actual address to the coefficient memory 420.
  • the baseband shaping circuit 400 supports more than one transmission rate which is related to power consumption. The transmission rate is selectable via a combination of the selectable frequency of the D/A clock and the increment value programmed into register 406.
  • the sum and difference waveform values represented by the positive coefficient values (also referred to as the true values) and the two's complement (negative) coefficient values are selected by the multiplexors 426 based upon the value of the data symbols at the 8 taps of the filter shift registers 442 (registers that are clocked on the symbol clock, not the D/A clock) and the current count of the D/A sample number (i.e. if there are 64 samples per symbol, which of the 64 samples is currently selected).
  • the determination of when to negate the coefficient value is based on the two data bits from the tapped delay line, here two stage I/Q Channel input data (symbol) shift registers 440, and the most significant bit of the coefficient address generator 416 since this bit indicates the need for reverse order pairing as shown in the New Pairings column of Table I.
  • the coefficient address generator 416 provides a means to step through the coefficient memory in increments of 1, 2, 4, 8, 16 or 32, which corresponds to 64, 32, 16, 8, 4, 2 D/A samples per symbol.
  • the most significant bit (MSB) of the address counter adder 408 is used to invert the rest of the counter address output bits in the XOR array 412 to take advantage of the symmetry of the coefficients as seen at mid-symbol (i.e. if required to generate 16 D/A samples per symbol, the first 8 coefficients will be a mirror image of the last eight as referenced to mid-symbol as seen in reference to the New Pairings column in Table I).
  • the output of the XOR gate 404 07 , the signal MSB07 is simply an XOR of the two data symbol bits from the two taps of the filter shift registers 442 combined to operate on the given coefficient memory (CO & C7, Cl & C6, C2 & C5, C3 & C4), here for example CO & C7.
  • This XOR output indicates whether the bits are the same or different. If they are the same, this means the coefficient to be used will be either CO + C7 or -(CO + C7). If they are different, this means the coefficient to be used will be either CO - C7 or -(CO - C7) (note only CO + C7 and CO - C7 are actually stored in memory and the negative of these coefficient values is created with digital logic.
  • XY indicates the coefficient pair.
  • Table II includes the logical relationship between the most significant bit of the address counter (adder/accumulator) and the two data symbol bits to generate the SELI/Q XY signals (e.g. SELI07, SELQ07) which determines whether the positive or negative value of the coefficient memory value (i.e. CO + C7 or -(CO + C7)) is provided as output to the adder stages 450 and 452.
  • the mathematical processing of a given input symbol cannot be performed in a single system clock cycle (i.e. symbol data input to first D/A sample out), therefore, the process is divided into a number of steps, each performed in a single clock cycle.
  • the implementation is then "pipelined" where the registers 462 are placed at the output of each processing step to resynchronize the outputs to the system clock.
  • Table I represents only the CO and C7 coefficient set pairing. A similar pairing exists the remaining coefficient sets Cl & C6, C2 & C5 and C3 & C4.
  • each coefficient for example, CO comprises a set of coefficient values COo -C0 n where n equals the number of samples to be provided at the D/A clock rate for a given symbol period.
  • the circuit 400 provides as many as 64 discrete samples per symbol.
  • Table I provides an example having sixteen samples per symbol for clarity.
  • the pairings column of Table I represent the values used from the two coefficients CO and C7 to produce any of the 16 discrete output samples.
  • Cl has been paired with C6, C2 with C5 and C3 with C4.
  • the symmetry column of Table I illustrates the symmetry in the coefficients for CO and C7. The same symmetry applies to Cl with C6, C2 with C5 and C3 with C4.
  • the New Pairings column of Table I substitutes the CO value for the C7 value to translate the coefficient values to a single set of 16 values, in this case the CO values.
  • the new address column of Table I shows that based on the new pairings, the initially required address range shown in the first column is reduced by a factor of two since the coefficient values in the new pairings column repeat (i.e. each pairing is used twice).
  • the memory address and memory content columns of Table I represent the physical address scheme implemented in circuit 400 and contents of the memory which provides two of the possible four combinations of the two coefficient values (COx + COy or COx - COy). The remaining two possible values are obtained by taking negative value, here for example the two's complement of the values (-COx- COy or -COx + COy, respectively).
  • the logic as shown by the truth table of Table II represents the implementation of the lookup table and the coefficient values based on the memory address and memory content columns of Table I.
  • ACCMSBD represents the output signal of register 414
  • I/Q XD and I/Q YD represent the corresponding outputs of the shift registers 4441 and 444Q of the two stage I Channel input data (symbol) shift register 4401 and the two stage I Channel input data (symbol) shift register 440Q.
  • the logic in the truth table also includes the combination of both I and Q channel lookups in a single set of 4 coefficient tables rather than one for each (i.e. the coefficient memories are timeshared between the two channels).
  • the XOR array 412 of the coefficient address generator 416 After the coefficient address generator 416 counts up to the mid-range value (in Table I the mid-range is eight counting zero to seven), the XOR array 412 of the coefficient address generator 416 performs an exclusive or logic operation of the most significant bit with the current address count and then counts down the address because only thirty-two values (eight values in Table I) for each coefficient are required.
  • the additional bit which is concatenated on to the five bits in the circuit 400 designed for 64 samples per symbol bit (three bits in the Table I example designed for 16 samples per symbol bit) represents a control bit that selects the desired pair of coefficient values from the memory (i.e. either COx + COy or, COx - COy) based on whether the data symbol for 10 is the same or different from 17.
  • the SELI07 or SELQ07 is used as determined by the truth table logic of Table II to select either the positive or negative coefficient value for either the I or Q channel.
  • the baseband bit shaping techniques can also be used for digital low pass filters having with symmetric coefficients.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

L'invention concerne un dispositif de mise en forme de bande de base qui comprend une pluralité de mémoires de coefficients, chaque mémoire comprenant un bus d'adresse d'entrée, une entrée de multiplexeur et une sortie de valeur de coefficient. Ce dispositif comprend également une pluralité de premiers registres à décalage, présentant chacun une entrée raccordée à une des sorties respectives de valeur de coefficient, une entrée et une sortie d'horloge numérique/analogique. Ledit dispositif comprend également: une pluralité de circuits de valeur négative, chaque circuit présentant une entrée raccordée à une des sorties respectives des premiers registres à décalage, et une sortie; une pluralité de multiplexeurs, présentant chacun une première entrée raccordée à une des sorties respectives des premiers registres à décalage, et une deuxième entrée raccordée à une sortie respective de la pluralité de circuits de valeur négative. Ledit dispositif comprend en outre une pluralité de seconds registres à décalage, et un additionneur présentant une pluralité d'entrées raccordées à la pluralité de seconds registres à décalage.
PCT/US2002/012806 2002-04-23 2002-04-23 Procede et dispositif de mise en forme de signaux qpsk WO2003092233A1 (fr)

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AU2002252711A AU2002252711B2 (en) 2002-04-23 2002-04-23 Method and device for pulse shaping QPSK signals
JP2004500460A JP2005524282A (ja) 2002-04-23 2002-04-23 Ｑｐｓｋ信号をパルス整形する方法及びデバイス
PCT/US2002/012806 WO2003092233A1 (fr) 2002-04-23 2002-04-23 Procede et dispositif de mise en forme de signaux qpsk
US10/511,862 US7346125B2 (en) 2002-04-23 2002-04-23 Method and device for pulse shaping QPSK signals
CA002483985A CA2483985A1 (fr) 2002-04-23 2002-04-23 Procede et dispositif de mise en forme de signaux qpsk
EP02721801A EP1497962A1 (fr) 2002-04-23 2002-04-23 Procede et dispositif de mise en forme de signaux qpsk

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013146626A1 (fr) * 2012-03-30 2013-10-03 Nec Corporation Détection cyclostationnaire améliorée sur la base de l'estimation du facteur d'affaiblissement d'un filtre de transmission
EP3903457A4 (fr) * 2018-12-27 2022-08-31 Istanbul Medipol Universitesi Transmission à porteuse unique avec facteur de déroulement adaptatif pour systèmes de communication ultra-fiables et à faible latence

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4760904B2 (ja) * 2006-02-17 2011-08-31 日本電気株式会社 帯域制限方法及び無線通信システム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5648988A (en) * 1992-09-02 1997-07-15 Fujitsu Limited Communication system including a digital roll-off filter
US6031431A (en) * 1997-11-07 2000-02-29 Hitachi America, Ltd. Methods and apparatus for implementing modulators and programmable filters
US6144862A (en) * 1998-07-28 2000-11-07 Motorola, Inc. Pulse-shaping look-up table with transient suppression

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5648988A (en) * 1992-09-02 1997-07-15 Fujitsu Limited Communication system including a digital roll-off filter
US6031431A (en) * 1997-11-07 2000-02-29 Hitachi America, Ltd. Methods and apparatus for implementing modulators and programmable filters
US6144862A (en) * 1998-07-28 2000-11-07 Motorola, Inc. Pulse-shaping look-up table with transient suppression

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHOI JONG-KWAN ET AL: "Area-efficient pulse-shaping 1:4 interpolated FIR filter based on LUT partitioning", ELECTRONICS LETTERS, vol. 35, no. 18, 2 September 1999 (1999-09-02), IEE, STEVENAGE, GB, pages 1504 - 1505, XP006012640, ISSN: 0013-5194 *
TZU-CHIEH KUO ET AL: "A programmable interpolation filter for digital communications applications", CIRCUITS AND SYSTEMS, 1998. PROCEEDINGS OF THE 1998 IEEE INTERNATIONAL SYMPOSIUM ON MONTEREY, CA, US, 31 May 1998 (1998-05-31) - 3 June 1998 (1998-06-03), IEEE, NEW YORK, US, pages 97 - 100, XP010289192, ISBN: 0-7803-4455-3 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013146626A1 (fr) * 2012-03-30 2013-10-03 Nec Corporation Détection cyclostationnaire améliorée sur la base de l'estimation du facteur d'affaiblissement d'un filtre de transmission
EP3903457A4 (fr) * 2018-12-27 2022-08-31 Istanbul Medipol Universitesi Transmission à porteuse unique avec facteur de déroulement adaptatif pour systèmes de communication ultra-fiables et à faible latence

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JP2005524282A (ja) 2005-08-11
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EP1497962A1 (fr) 2005-01-19
AU2002252711B2 (en) 2006-05-04

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