WO2003075356A1 - Portion de contact de dispositif semi-conducteur et procede de fabrication associe, panneau de reseau de transistors en couche mince pour dispositif d'affichage contenant la portion de contact et procede de fabrication associe - Google Patents

Portion de contact de dispositif semi-conducteur et procede de fabrication associe, panneau de reseau de transistors en couche mince pour dispositif d'affichage contenant la portion de contact et procede de fabrication associe Download PDF

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Publication number
WO2003075356A1
WO2003075356A1 PCT/KR2002/000805 KR0200805W WO03075356A1 WO 2003075356 A1 WO2003075356 A1 WO 2003075356A1 KR 0200805 W KR0200805 W KR 0200805W WO 03075356 A1 WO03075356 A1 WO 03075356A1
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WIPO (PCT)
Prior art keywords
insulating layer
gate
wire
contact hole
data
Prior art date
Application number
PCT/KR2002/000805
Other languages
English (en)
Inventor
Chun-Gi You
Original Assignee
Samsung Electronics Co., Ltd.
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Publication date
Application filed by Samsung Electronics Co., Ltd. filed Critical Samsung Electronics Co., Ltd.
Priority to AU2002255377A priority Critical patent/AU2002255377A1/en
Publication of WO2003075356A1 publication Critical patent/WO2003075356A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G02F1/133555—Transflectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Definitions

  • the present invention relates to a contact structure of a semiconductor device, a manufacturing method thereof, a thin film transistor array panel for a display device including a contact structure, and a manufacturing method thereof.
  • a semiconductor device has multiple layers of wires interposed between interlayer insulating layers. It is desirable that the interlayer insulating layers are made of materials with low permittivity in order to m imize the interference between signals flowing through the different wires, and different layers of wires transmitting the same signals are electrically connected to each other through contact holes provided at the interlayer insulating layers.
  • the interlayer insulating layers include an organic insulating layer with low permittivity, which is commonly formed by spin coating.
  • the organic layer has a stepped height when the structure underlying the organic layer has a steep height difference, which causes the organic material to be localized onto a specific area during the spin coating.
  • LCD liquid crystal display
  • a reflective type LCD displaying images by reflecting external light
  • a transflective type LCD operating both in a reflective mode and a transmissive mode
  • this deteriorates the display characteristics.
  • an LCD is one of the most widely used flat panel displays.
  • LCD which includes two panels having electrodes and a liquid crystal layer interposed therebetween, controls the transmittance of light passing through the liquid crystal layer by realigning liquid crystal molecules in the liquid crystal layer with voltages applied to the electrodes.
  • TFTs thin film transistors
  • a panel with TFTs (“TFT array panel”) includes, in addition to the TFTs, signal wires including gate lines transmitting scanning signals, data lines transmitting image signals, gate pads transmitting the scanning signals from external devices to the gate lines, and data pads transmitting the image signals from external devices to the data lines.
  • the TFT array panel further includes pixel electrodes electrically connected to the TFTs and located in respective pixel areas defined by the intersections of the gate lines and the data lines.
  • a pixel electrode of a reflective type LCD or a transflective type LCD includes a conductive reflecting film, which preferably has embossment for increasing the reflecting efficiency to improve display characteristics.
  • the embossment of the reflecting film is formed by providing an organic insulating layer with unevenness under the reflecting film-
  • the stepped height of the organic insulating layer due to the steep height difference of the underlying structure gives the poor profile of the unevenness of the organic insulating layer, thereby causing the non-uniform embossment of the reflecting film to generate strains.
  • the present invention forms an organic insulating layer pattern exposing an insulating layer, and then forms a contact hole at the exposed portion of the insulating layer, which exposes a wire. There is no height difference due to the contact hole of the insulating layer when forming the organic insulating layer.
  • a method of manufacturing a contact structure of a semiconductor device forms a first wire on a substrate, and then forms a first insulating layer covering the first wire.
  • an organic insulating material is deposited on the first insulating layer and patterned to form a second insulating layer having a first contact hole exposing a portion of the first insulating layer opposite the first wire.
  • the exposed portion of the first insulating layer through the first contact hole is patterned by photo etch using a photoresist pattern to form a second contact hole exposing the first wire, and then a second wire connected to the first wire through the second contact hole is formed.
  • the first insulating layer includes silicon nitride or silicon oxide and the second wire includes reflective conductive material.
  • the second contact hole preferably exposes a boundary of the first contact hole.
  • the second insulating layer have an uneven patter on its surface.
  • the above described method of manufacturing a semiconductor device may be applicable to a method of manufacturing a thin fil transistor array panel for a liquid crystal display.
  • a gate wire including a gate line and a gate electrode connected to the gate line is formed on an insulating substrate, and then a gate insulating layer is deposited.
  • a semiconductor layer and a data wire are formed.
  • the data wire includes a data line intersecting the gate line to define a pixel area, a source electrode connected to the data line and placed close to the gate electrode, and a drain electrode placed opposite the source electrode with respect to the gate electrode is formed.
  • a first insulating layer is deposited, and an organic insulating material is spin-coated on the first insulating layer.
  • the organic insulating material is patterned to form a second insulating layer having a first contact hole exposing a portion of the first insulating layer opposite the drain electrode. Then, the exposed portion of the first insulating layer is patterned by photo etch with a photoresist pattern to form a second contact hole exposing the drain electrode along with the first contact hole. A pixel electrode connected to the drain electrode through the first and the second contact holes is formed.
  • the pixel electrode may include a transparent conductive electrode or a reflective conductive film.
  • the second insulating layer have an unevenness pattern on its surface.
  • the pixel electrode includes both the transparent electrode and the reflective film, it is preferable that the reflective film have an aperture in a pixel area.
  • the data wire and the semiconductor layer may be concurrently formed by photo etch using a photoresist pattern with position-dependent thickness.
  • the gate wire may further include a gate pad connected to one end of the gate line
  • the data wire may further include a data pad connected to one end of the data line
  • the first insulating layer or the gate insulating layer may have a third contact hole exposing the gate pad or the data pad.
  • the thin film transistor array panel may further include a subsidiary pad electrically connected to the gate pad or the data pad through the third contact hole made of the same layer as the pixel electrode.
  • Figs. 1A to 1C are sectional views of a contact structure of a semiconductor device sequentially illustrating a manufacturing method thereof according to an embodiment of the present invention
  • Fig. 2 is a layout view of a TFT array panel for a transflective type LCD according to an embodiment of the present invention
  • Fig. 3 is a sectional view of Fig. 2 taken along the line III-IIT;
  • Fig. 4A, 5A, 6A, IK, 8A and 9A are layout views of a TFT array panel for a transflective type LCD in the intermediate steps of a manufacturing method thereof according to an embodiment of the present invention
  • Fig. 4B is a sectional view of Fig. 4A taken along the line IVB-IVB';
  • Fig. 5B is a sectional view of Fig. 5A taken along the line V-V and illustrates the step following the step shown in Fig. 4B;
  • Fig. 6B is a sectional view of Fig. 6A taken along the line VIB-VIB' and illustrates the step following the step shown in Fig. 5B
  • Fig. 7B is a sectional view of Fig. 7A taken along the line VIIB-VIIB' and illustrates the step following the step shown in Fig. 6B;
  • Fig. 8B is a sectional view of Fig. 8A taken along the line VIIIB-VIIIB' and illustrates the step following the step shown in Fig. 7B;
  • Fig. 9B is a sectional view of Fig. 9A taken along the line IXB-IXB' and illustrates the step following the step shown in Fig. 8B;
  • Fig. 10 is a layout view of a TFT array panel for a reflective type LCD according to a second embodiment of the present invention
  • Fig. 11 is a sectional view of the TFT array panel shown in Fig. 10 taken along the line XI-XI';
  • Fig. 12 is a layout view of a TFT array panel for an LCD according to a third embodiment of the present invention
  • Fig. 13 is a sectional view of the TFT array panel shown in Fig. 12 taken along the line XII-XII';
  • Fig. 14 is a layout view of a TFT array panel for an LCD according to a fourth embodiment of the present invention.
  • Figs. 15 and 16 are sectional views of the TFT array panel shown in Fig. 14 taken along the line XN-XV' and the line XVI-XVT, respectively;
  • Fig. 17A is a layout view of a TFT array panel in the first step of a manufacturing method thereof according to the fourth embodiment of the present invention.
  • Figs. 17 B and 17C are sectional views of Fig. 17A taken along the lines XVIIB-XVIIB' and XVIIC-XVIIC, respectively;
  • Figs. 18A and 18B are sectional views of Fig. 17A taken along the lines XVIIB-XVIIB' and XVIIC-XVIIC, respectively, and illustrate the step following the step shown in Figs. 17B and 17C;
  • Fig. 19A is a layout view of the TFT array panel in the step following the step shown in Figs. 18A and 18B;
  • Figs. 19B and 19C are sectional views of Fig. 19A taken along the lines XIXB-XIXB' and XIXC-XIXC, respectively;
  • Figs. 20A, 21A and 22A, and Figs. 20B, 21B and 22B are respective sectional views of Fig. 19A taken along the lines XIXB-XIXB' and XIXC-XIXC, respectively, and illustrate the steps following the step shown in Figs. 19B and 19C;
  • Fig. 23A is a layout view of the TFT array panel in the step following the step shown in Figs. 22 A and 22B;
  • Figs. 23B and 23C are sectional views of Fig. 23 A taken along the lines XXIIIB-XXIIIB' and XXIIIC-XXIIIC, respectively;
  • Fig. 24 A is a layout view of the TFT array panel in the step following the step shown in Figs. 23B and 23C;
  • Figs. 24B and 24C are sectional views of Fig. 24A taken along the lines XXIVB-XXIVB' and XXIVC-XXIVC and illustrate the sequence of the step following the step shown in Figs. 23B and 23C, respectively.
  • a semiconductor device has multiple layers of wires interposed between interlayer insulating layers. It is desirable that the interlayer insulating layers are made of materials with low permittivity in order to lnmirnize the interference between signals flowing through the different wires, and different layers of wires transmitting the same signals are electrically connected to each other through contact holes provided at the interlayer insulating layers.
  • An interlayer insulator preferably includes an insulating layer preferably made of silicon nitride or silicon oxide and an organic layer made of organic insulating material with low permittivity.
  • the insulating layer is preferably formed by chemical vapor deposition ("CVD"), while the organic layer is preferably formed by spin coating.
  • the insulating layer is patterned after forming the organic layer on the insulating layer in order to improve the stepped height of the organic layer due to the depth of a contact hole pre-provided at the insulating layer exposing an underlying wire when coating the' organic layer after patterning the insulating layer to form the contact hole, which causes the organic material to be localized onto a specific area during the spin coating.
  • FIG. 1A to 1C are sectional views of a contact structure of a semiconductor device sequentially illustrating the steps of a manufacturing method thereof according to an embodiment of the present invention.
  • a first insulating layer 310 preferably made of silicon nitride or silicon oxide is deposited on a substrate 100 provided with a first wire 200 thereon as shown in Fig. 1A.
  • a second insulating layer 320 preferably made of organic insulating material with low permittivity is coated on the first insulating layer 310 to form an interlayer insulator 300.
  • the second insulating layer 320 is patterned by photolithography using a mask to form a first contact hole 330 exposing a portion of the lower insulating layer 310 on the first wire 200.
  • 310 is patterned to form a second contact hole 340 by photo etch using a photoresist pattern 400 having an aperture located inside the first contact hole 330.
  • a conductive material is deposited on the second insulating layer 320, and patterned by photo etch using a mask to form a second wire 500 electrically connected to the first wire 200 through the first and the second contact holes 330 and 340.
  • the resultant contact structure of a semiconductor device includes a sidewall having a stepwise structure without undercut because the first contact hole 330 exposes the top surface of the first insulating layer 310.
  • the method of manufacturing a contact structure of a semiconductor device removes the localized distribution of organic material onto a specific area due to the height difference during spin coating by spin-coating the second insulating layer 320 made of organic insulating material before patterning the first insulating layer 310.
  • the method of manufacturing a contact structure of a semiconductor device according to this embodiment of the present invention is adaptable to a TFT array panel for an LCD and a manufacturing method thereof.
  • Fig. 2 is a layout view of a TFT array panel for a reflective type LCD according to a first embodiment of the present invention
  • Fig. 3 is a sectional view of the TFT array panel shown in Fig. 2 taken along the line III-III'.
  • a gate wire is formed on an insulating substrate 10.
  • the gate wire includes either a single layer preferably made of silver, silver alloy, aluminum, and aluminum alloy having low resistivity, or multiple layers including the single layer.
  • the gate wire includes a plurality of gate lines 22 extending substantially in a transverse direction, a plurality of gate pads 24 connected to one ends of the gate lines 22 for receiving gate signals from external devices and transmitting the gate signals to the gate lines 22, and a plurality of gate electrodes 26 of TFTs connected to the gate lines 22.
  • the gate wire may overlap pixel electrodes 82 and 86, which will be formed later, to form storage capacitors, or may include a plurality of storage electrodes applied with a predetermined voltage such as a common electrode voltage (which is applied to a common electrode of an upper panel and referred to as "a common voltage” hereinafter) from an external source such that the storage electrodes overlap the pixel electrodes 82 and 86, which will be described later, to form storage capacitors for improving the charge storing capacity of pixels.
  • a common electrode voltage which is applied to a common electrode of an upper panel and referred to as "a common voltage” hereinafter
  • the gate wire 22, 24 and 26 is covered by a gate insulating layer 30 preferably made of silicon nitride formed on the substrate 10.
  • a semiconductor layer 40 preferably made of amorphous silicon is formed on the gate insulating layer 30 opposite the gate electrodes 24, and an ohmic contact layer 55 and 56 preferably made of suicide or n+ hydrogenated amorphous silicon heavily doped with n type impurity is formed on the semiconductor layer 40.
  • a data wire is formed on the ohmic contact layer 55 and 56 and the gate insulating layer 30.
  • the data wire includes a conductive layer preferably made of conductive material with low resistivity such as aluminum and silver.
  • the gate wire includes a plurality of data lines 62 extending substantially in a longitudinal direction and intersecting the gate lines 22 to define pixel areas, a plurality of source electrodes 65 connected to the data lines 62 and extending to one portions 55 of the ohmic contact layer 54 and 56, a plurality of data pads 68 connected to one ends of the data lines 62 for receiving image signals from external devices, and a plurality of drain electrodes 66 separated from the source electrodes 65 and located on the other portions 56 of the ohmic contact layer 54 and 56 opposite the source electrodes 53 with respect to the gate electrodes 26.
  • a first insulating layer 70 preferably made of silicon nitride is formed on the data wire 62, 65, 66 and 68 and portions of the semiconductor layer 40, which are not covered by the data wire 62, 65, 66 and 68, and a second insulating layer 90 is formed on the first insulating layer 70.
  • the second insulating layer 90 is preferably made of photosensitive organic material having a good flatness characteristic.
  • the top surface of the second insulating layer 90 has an evenness pattern to maximize the reflecting efficiency of a reflecting film 86, which will be formed later.
  • the second insulating layer 90 is removed out, while the first insulating layer 70 is still remained.
  • This structure removes organic insulating material on the pad areas and thus is advantageously applicable to a chip on glass (“COG”) type LCD, where a plurality of gate driving integrated circuits (“ICs”) and a plurality of data driving ICs for respectively transmitting the scanning signals and the image signals to the gate pads 24 and the data pads 68 are directly mounted on the TFT array panel.
  • COG chip on glass
  • a plurality of contact holes 76 and 78 respectively exposing the drain electrodes 66 and the data pads 68 are provided at the first insulating layer 70, and a plurality of contact holes 74 exposing the gate pads 24 are provided at the gate insulating layer 30 and the first insulating layers 90.
  • the second insulating layer 90 has a plurality of contact holes 96 exposing the drain electrodes 66, the boundaries of the contact holes 76 of the first insulating layer 70 exposing the drain electrodes 66, and the flat surface of the first insulating layer 70.
  • a plurality of transparent electrodes 82 are formed on the second insulating layer 90.
  • the transparent electrodes 82 are located substantially in a pixel area, and electrically connected to the drain electrodes 66 through the contact holes 76 and 96.
  • a reflecting film 86 having an aperture 85 is formed on each transparent electrode 82.
  • an area T defined by the aperture 85 is referred to as a tiansmitting area, while the remaining area R is referred to as a reflecting area.
  • the transparent electrodes 82 are preferably made of transparent conductive material such as indium zinc oxide ("IZO") and indium tin oxide ("ITO”), while the reflecting films 86 are preferably made of aluminum, aluminum alloy, silver and silver alloy having reflectance.
  • Each reflecting film 86 preferably includes a contact assistant layer provided on a contact surface with the ti'ansparent electrode 82 to ensure good contact characteristics between the reflecting film 86 and the transparent electrode 82, and the contact assistant layer is preferably made of molybdenum, molybdenum alloy, chromium, titanium or tantalum.
  • a plurality of subsidiary gate pads 84 and a plurality of subsidiary data pads 88 are formed on the first insulating layer 70.
  • the subsidiary gate pads 84 and the subsidiary data pads 88 are connected to the gate and the data pads 24 and 68 through the contact holes 74 and 78, respectively.
  • the subsidiary gate and data pads 84 and 88 are not requisites but preferred to protect the gate and the data pads 24 and 68.
  • the subsidiary gate and data pads 84 and 88 are preferably made of the same layer either as the transparent electrodes 82 or as the reflecting film 86.
  • a method of manufacturing a TFT array panel for a transflective type LCD according to the first embodiment of the present invention will be now described with reference to Figs. 4A to 9B as well as Figs. 2 and 3.
  • a conductive material with low resistivity is deposited on a glass substrate 10, and patterned by photo etch using a mask to form a gate wire extending substantially in the transverse direction including a plurality of gate lines 22, a plurality of gate electrodes 26, and a plurality of gate pads 24.
  • a gate insulating layer 30 made of silicon nitride after sequentially depositing three layers including a gate insulating layer 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50, the doped amorphous silicon layer 50 and the semiconductor layer 40 are patterned using a mask to form a semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 opposite the gate electrodes 24. Subsequently, as shown in Figs.
  • a conductive layer for a data wire is deposited and patterned by photolithography using a mask to form a data wire including a plurality of data lines 65 intersecting the gate lines 22, a plurality of source electrodes 65 connected to the data lines 65 and extending onto the gate electrodes 26, a plurality of data pads 68 connected to one ends of the data lines 62, and a plurality of drain electrodes 66 separated from the source electrodes 65 and opposite the source electrodes 65 with respect to the gate electrodes 26.
  • portions of the doped amorphous silicon pattern 50 which are not covered by the data wire 62, 65, 66 and 68, are etched such that the doped amorphous silicon layer pattern 50 is separated into two portions 55 and 56 opposite each other with respect to the gate electrodes 26 to expose portions of the semiconductor pattern 40 between the two portions of the doped amorphous silicon layer 55 and 56.
  • Oxygen plasma treatment is preferably performed in order to stabilize the exposed surfaces of the semiconductor layer 40.
  • silicon nitride is deposited by CVD to form a first insulating layer 70, and a photosensitive organic material having a good flatness characteristic is coated on the first insulating layer 70 to form a second insulating layer 90 before patterning the first insulating layer 70.
  • the spin-coating of the second insulating layer 90 before patterning the first insulating layer 70 according to this embodiment of the present invention prevents the localized distribution of organic material onto a specific area since there is no height difference due to the first insulating layer 70 during the spin coating.
  • the second insulating layer 90 is patterned by photolithography using a mask to form a plurality of contact holes 96 exposing portions of the first insulating layer 70 opposite the drain electrodes 66 and simultaneously to form an unevenness pattern on the surface of the second insulating layer 90. Furthermore, portions of the second insulating layer 90 at the pad areas provided with the gate pads 24 and the data pads 68 are removed to expose the first insulating layer 70.
  • the first insulating layer 70 and the gate insulating layer 30 are patterned by photo etch using a photoresist pattern 1000 to form a plurality of contact holes 74, 76 and 78 exposing the gate pads 24, the drain electrodes 66, and the data pads 68, respectively.
  • the contact holes 76 of the first insulating layer 70 exposing the drain electrodes 66 are placed inside the contact holes 96 of the second insulating layer 90 such that the boundaries and the flat surfaces of the first insulating layer 70 are exposed, and therefore the contact structures have stepwise shapes without undercut. It is preferable that the width of the exposed surface of the first insulating layer 70 at the contact structure is 0.1 microns or more.
  • ITO or IZO is deposited and patterned using a mask to form a plurality of transparent electrodes 82 connected to the drain electrodes 66 through the contact holes 76 and 96, a plurality of subsidiary gate pads
  • each reflecting film 86 preferably includes a contact assistant layer made of material having a good contact characteristic with other materials to improve the contact characteristic with the transparent electrode 82.
  • the spin- coating of the second insulating layer 90 before patterning the first insulating layer 70 prevents the localized distribution of organic material onto a specific area since there is no height difference due to the first insulating layer 70 during the spin coating, thereby obtaining a uniform unevenness pattern on the second insulating layer 90.
  • the embossment of the reflecting film 86 following the unevenness pattern of the second insulating layer 90 is established to be uniform, and this prevents stains on a screen displaying images.
  • the method of manufacturing a TFT array panel according to this embodiment of the present invention completely prevents organic insulating material from remaining o the pad areas because the first insulating layer 70 is patterned after removing the organic insulating material from the pad areas in the formation of the second insulating layer 90. Therefore, the TFT array panel manufactured by this method is advantageously applicable particularly to a COG type LCD, where a plurality of gate driving ICs and a plurality of data driving ICs for respectively transmitting the scanning signals and the image signals to the gate pads 24 and the data pads 68 are directly mounted on the TFT array panel.
  • the manufacturing method according to the first embodiment of the present invention can be adapted to a method for manufacturing a TFT array panel for a reflective type LCD.
  • a TFT array panel for a reflective type LCD according to a second embodiment of the present invention will be described in detail with reference to Figs. 10 and 11.
  • the structure is almost the same as the structure according to the first embodiment.
  • a plurality of reflecting films 86 are located directly on a second insulating layer 90 and in direct electrical connection with a plurality of drain electrodes 66 through a plurality of contact holes 76 and 96.
  • the reflecting film 86 occupies the entire pixel area.
  • a method of manufacturing a TFT array panel for a reflective type LCD according to the second embodiment of the present invention is almost the same as the metliod according to the first embodiment, until the step of forming a plurality of contact holes 74, 76 and 78 at a first insulating layer 70.
  • a plurality of reflecting films 86 are formed by depositing and patterning a reflective conductive material immediately after forming the contact holes 74, 76 and 78 exposing a plurality of drain electrode 66, a plurality of gate pads 24, and a plurality of data pads 68 at the first insulating layer 70.
  • the manufacturing method according to the first embodiment of the present invention is also applicable to a method for manufacturing a TFT array panel for a transmissive type LCD.
  • a TFT array panel for a reflective type LCD according to a third embodiment of the present invention will be described in detail with reference to Figs. 12 and 13.
  • each gate line 22 of a gate wire 22, 24 and 26 has wider than the other portions to overlap corresponding transparent pixel electrodes 82 to obtain sufficient storage capacitance.
  • a data wire 62, 65, 66 and 68 includes a conductor pattern 64 for storage capacitors overlapping the gate lines 22, and the pixel electrodes 82 made of a transparent conductive material are placed directly on a second insulating layer 90.
  • the pixel electrodes are located substantially in pixel areas and electrically connected to a plurality of drain electrode 66 through contact holes 76 and 96.
  • the pixel electrodes 82 are electrically connected to the conductor pattern 64 through contact holes 72 and 92 provided at first and second insulating layers 70 and 90, and contact holes 74 provided at the first insulating layer 70 and a gate insulating layer 30 exposing gate pads 24 are wider than the gate pads 24.
  • a method of manufacturing a TFT array panel for a reflective type LCD according to the second embodiment of the present invention is almost the same as the method according to the first embodiment, until the step of forming contact holes 72, 74, 76 and 78 at a first insulating layer 70.
  • the method of manufacturing the TFT array panel according to the third embodiment of the present invention does not form an unevenness pattern on the surface of a second insulating layer 90, and provides a semiconductor layer 40 extending in the longitudinal direction along the data wire 62, 65, 66 and 68.
  • a transparent conductive material is deposited and patterned to form a transparent pixel electrode 86 immediately after forming the contact holes 72, 74, 76 and 78 exposing a plurality of drain electrodes 66, a plurality of gate pads 24, and a plurality of data pads 68 at the first insulating layer 70.
  • the above-described manufacturing method according to the embodiments of the present invention can be applied to a method of manufacturing a TFT array panel for a transmissive type LCD forming both a semiconductor layer and a data wire by photo etch using one photoresist pattern, thereby simplifying the manufacturing process.
  • This method will be described in detail with reference to accompanying drawings. First, a structure of a unit pixel of a TFT array panel for an LCD manufactured using four masks according to an embodiment of the present invention will be described with reference to Figs. 14 to 16.
  • Fig. 14 is a layout view of a TFT array panel for an LCD according to a fourth embodiment of the present invention
  • Figs. 15 and 16 are sectional views of the TFT array panel shown in Fig. 14 taken along the line XV-XV and the line XVI-XVT of Fig. 14, respectively.
  • a gate wire is formed on an insulating substrate 10.
  • the gate wire is preferably made of a material with low resistivity such as silver, silver alloy, aluminum and aluminum alloy.
  • the gate wire includes a plurality of gate lines 22, a plurality of gate pads 24, and a plurality of gate electrodes 26.
  • the gate wire further includes a plurality of storage electrodes 28 formed on the substrate, which are substantially parallel to the gate lines 22 and applied with a predetermined voltage such as a common voltage from an external source, which is also applied to a common electrode of an upper panel.
  • the storage electrodes 28 overlap a storage capacitor conductor pattern connected to pixel electrodes 82, which will be described later, to form storage capacitors for improving the charge storing capacity of pixels.
  • the storage electrodes 28 may be omitted if the storage capacitance due to the overlapping of the gate lines 22 and the pixel electrodes 82 to be described later are sufficient.
  • a gate insulating layer 30 preferably made of silicon nitride is formed on the gate wire 22, 24, 26 and 28, while covering the gate wire 22, 24, 26 and 28.
  • a semiconductor pattern 42 and 48 preferably made of hydrogenated amorphous silicon is formed on the gate insulating layer 30, and an ohmic contact layer pattern or an intermediate layer pattern 55, 56 and 58 preferably made of amorphous silicon heavily doped with n type impurity such as phosphorous is formed on the semiconductor layer 42 and 48.
  • a data wire made of an aluminum-based conductive material with low resistivity is formed on the ohmic contact layer pattern 55, 56 and 58.
  • the data wire includes a plurality of data portions 62, 65 and 68, a plurality of drain electrodes 66 of TFTs, and a storage capacitor conductor pattern 64.
  • Each data portion includes a data line 62 extending substantially in the longitudinal direction, a data pad 68 connected to one end of the data line 62 for receiving image signals from an external device, and a plurality of source electrodes 65 branched from the data line 62.
  • Each drain electrode 66 is separated from the data portion 62, 65 and 68, and placed opposite the corresponding source electrode 53 with respect to the corresponding gate electi'ode 26 or a channel portion of the associated TFT.
  • the storage capacitor conductor pattern 64 is placed on the storage electrodes 28. hi absence of the storage electrodes 28, the storage capacitor conductor pattern 64 is not provided.
  • the ohmic contact layer pattern 55, 56 and 58 plays a role of reducing the contact resistance between the semiconductor pattern 42 and 48 thereunder and the data wire 62, 64, 65, 66 and 68 thereover.
  • the olimic contact layer pattern 55, 56 and 58 has substantially the same shape as the -data wire 62, 64, 65, 66 and 68.
  • a data intermediate layer pattern 55 of the have substantially the same shapes as the data portions 62, 65 and 68, a drain intermediate layer pattern 56 as the drain electrodes 66, and a storage capacitor intermediate layer pattern 58 as the storage capacitor conductor pattern 68.
  • the semiconductor pattern 42 and 48 has the same shape as the data wire 62, 64, 65, 66 and 68 and the ohmic contact layer pattern 55, 56 and 58 except for the channel areas C of the TFTs.
  • a storage capacitor semiconductor pattern 48 has substantially the same shape as the storage capacitor conductor pattern 68 and the storage capacitor ohmic contact layer pattern 58, while a TFT semiconductor pattern 42 layer is a little different from the data wire and the rest of the ohmic contact layer pattern.
  • the TFT semiconductor pattern 42 is not disconnected to form channels of the TFTs.
  • An interlayer insulator including a first insulating layer 70 preferably made of silicon nitride and a second insulating layer 90 preferably made of organic insulating material with low permittivity is provided on the data wire 62, 65, 66 and 68 as in the third embodiment.
  • the first insulating layer 70 has a plurality of contact holes 76, 78 and 72 exposing the drain electrodes 66, the data pads 68, and the storage capacitor conductor pattern 64, respectively, and a plurality of contact holes 74 exposing the gate pads 24 together with the gate insulating layer 30.
  • the second insulating layer 90 is removed out from the pad areas to expose the first insulating layer 70, and the contact holes 72 and 96 expose the boundaries of the first insulating layer 70, which is a lower insulating layer, such that the sidewalls of the contact holes 92; and 96 have stepwise shapes.
  • a plurality of pixel electi'odes 82 receiving image signals from the TFTs and generating electric fields in cooperation with an electrode on an upper panel are formed on the low permittivity insulating layer 73.
  • the pixel electi'odes 82 are made of transparent conductive material such as IZO or ITO, and electrically connected to the drain electrodes 66 through the contact holes 76 and 96 to receive image signals. Furthermore, the pixel electrodes 82 overlap the adjacent gate lines 22 and the adjacent data lines 62 to increase the aperture ratio. However, the overlaps may be omitted.
  • the pixel electrodes 82 are connected to the storage capacitor conductor pattern 64 through the contact holes 72 and 92 to transmit the image signals.
  • a plurality of subsidiary gate pads 84 and a plurality of subsidiary data pads 88 are formed on the first insulating layer 70.
  • the subsidiary gate pads 84 and the subsidiary data pads 88 are located on the gate pads 24 and the data pads 24 and 68, respectively, and thus connected thereto through the contact holes 74 and 78, respectively.
  • the subsidiary gate pads 84 and the subsidiary data pads 88 are not requisites but preferred to protect the pads 24 and 68 and to complement the adhesiveness between the pads 24 and 68 and external circuit devices.
  • the contact holes 72 and 76 have stepwise shaped sidewalls due to exposed surfaces of the first insulating layer 70, and the surface of the first insulating layer 70 in the pad areas is exposed not to generate undercut. This prevents the disconnections of the pixel electrodes 82, the subsidiary gate pads 84, and the subsidiary data pads 88.
  • the subsidiary gate pads 84 and the subsidiary data pads 88 are located on the first insulating layer 70 at least in part.
  • transparent ITO or IZO is exemplified as materials for the pixel electrodes 82.
  • opaque conductive material for a reflective type LCD.
  • a gate wire including a plurality of gate lines 22, a plurality of gate pads 24, a plurality of gate electrodes 26, and a plurality of storage electrodes 28 is formed on a substrate 10 by depositing a conductive material or materials for the gate wire and patterning by photo etching using a first mask.
  • the gate wire has a single-layered structure including a single layer made of material with low resistivity such as aluminum, aluminum alloy, silver or silver alloy.
  • the conductive layer has a multiple-layered structure including the single layer and a layer made of conductive material with good contact characteristics with other materials, such as chrome, titanium, and tantalum.
  • a gate insulating layer 30, a semiconductor layer 40, and an intermediate layer 50 are sequentially deposited by CVD such that the layers 30, 40 and 50 bear thickness of 1,500-5,000 A, 500-2,000 A and 300-600 A, respectively.
  • a conductive layer 60 for a data wire with low resistivity is deposited by sputtering such that the layer 60 bears the thickness of 1,500-3,000 A, and subsequently a photoresist film 110 with the thickness of 1-2 microns is coated on the conductive layer 60. Subsequently, the photoresist film 110 is exposed to light through a second mask, and developed to form a photoresist pattern 114 and 112 as shown in Figs. 19A-19C.
  • the portions of the photoresist film on the remaining area B are removed.
  • the thickness ratio of the first portions 114 on the channel areas C to the second portions 112 on the data areas A is adjusted depending upon the etching conditions in the etching steps to be described later. It is preferable that the thickness of the first portions 114 is equal to or less than half of the thickness of the second portions 112, in particular, equal to or less than 4,000 A.
  • the position-dependent thickness of the photoresist film is obtained by several techniques.
  • a lattice pattern or semi-transparent films are provided on a mask.
  • the width of the portions between the slits or the distance between the portions, i.e., the width of the slits is smaller than the resolution of an exposer used for the photolithography.
  • thin films with different transmittances or with different thicknesses may be used to adjust the transmittance of the mask.
  • the thin portions 114 of the photoresist pattern may be obtained by performing a reflow process to flow a reflowable photoresist film into the areas without the photoresist film after exposing to light and developing the photoresist film, using a usual mask with transmissive areas completely transmitting the light and blocking areas completely blocking the light. Thereafter, the photoresist pattern 114 and the underlying layers, i.e., the conductive layer 60, the intermediate layer 50 and the semiconductor layer 40 are etched such that a data wire and the underlying layers are left over on the data areas A, only the semiconductor layer is left over on the channel areas C, and all of the three layers 60, 50 and 40 are removed from the remaining areas B to expose the gate insulating layer 30.
  • the exposed portions of the conductive layer 60 on the areas B are removed to expose the underlying portions of the intermediate layer 50.
  • both dry etching and wet etching is selectively used and preferably performed under the condition that the conductive layer 60 is selectively etched while the photoresist pattern 112 and 114 is hardly etched.
  • an etching condition capable of etching the photoresist pattern 112 and 5 114 as well as the conductive layer 60 would be suitable for dry etching since it is difficult to find a condition for selectively etching only the conductive layer 60 while not etching the photoresist pattern 112 and 114.
  • the first portion 114 should have relatively thick compared with that for wet etching in order to prevent the exposure of the underlying conductive layer 60 through the etching.
  • Both dry etching and wet etching are applicable to the conductive material for a data wire containing aluminum or aluminum alloy.
  • Wet etching preferably with an etchant CeNH0 3 , is preferred for Cr which is hardly removed by dry etching.
  • a very thin Cr film of about 500 A may be removed by dry etching.
  • a source/ drain conductor pattern 67 i.e., portions of the conductive layer on the channel areas C and the data areas A, and a storage capacitor conductor pattern 64 are left over, while portions of the conductive layer 60 on the remaining areas B is removed out to expose the underlying portions of the intermediate layer 50.
  • the remaining conductor patterns i.e., portions of the conductive layer on the channel areas C and the data areas A, and a storage capacitor conductor pattern 64 are left over, while portions of the conductive layer 60 on the remaining areas B is removed out to expose the underlying portions of the intermediate layer 50.
  • the photoresist pattern 112 and 114 are also etched to a predetermined thickness.
  • intermediate layer 50 on the areas B and the underlying portions of the semiconductor layer 40 are simultaneously removed by dry etching together with the first portions 114 of the photoresist film.
  • Sequential dry etch of the intermediate layer 50 and the semiconductor layer 40 may follow the dry etch of the conductor patterns 67 or in-situ etch process may be performed. The etch of the intermediate
  • the 30 layer 50 and the semiconductor layer 40 is preferably made in a condition that the photoresist pattern 112 and 114, the intermediate layer 50 and the semiconductor layer 40 are simultaneously etched while the gate insulating layer 30 is not etched. (It is noted that the semiconductor layer and the intermediate layer have no etching selectivity.) Particularly, the etching ratios of the photoresist pattern 112 and 114 and the semiconductor layer 40 are preferably equal to each other. For the equal etching ratios of the photoresist pattern 112 and 114 and the semiconductor layer 40, the thickness of the first portions 114 is preferably equal to or less than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.
  • the portions of the conductive layer 60 on the channel areas C and the data areas A i.e., the source/ drain conductor pattern 67 and the storage capacitor conductor pattern 64 are left over, while the portions of the conductive layer 60 on the remaining areas B are removed out.
  • the first portions 114 on the channel areas C are removed to expose the source/ drain conductor pattern 67
  • the portions of the intermediate layer 50 and the semiconductor layer 40 on the areas B are removed to expose the underlying portions of the gate insulating layer 30.
  • the second portions 112 on the data areas A are also etched to have reduced thickness. In this step, the formation of a semiconductor pattern 42 and 48 are completed.
  • Reference numerals 57 and 58 indicate intermediate layer patterns under the source/ drain conductor pattern 67 and under the storage capacitor conductor pattern 64, respectively.
  • the exposure of the portions of the source/ drain conductor pattern 67 on the channel areas C is alternatively obtained by a separate photoresist ("PR") etch back step, which is not necessary under the condition that the photoresist film is sufficiently etched.
  • PR photoresist
  • Residual photoresist remained on the surface of the source/ drain conductor pattern 67 on the channel areas C is then removed by ashing. Subsequently, as shown in Figs. 22A and 22B, the exposed portions of the source/ drain conductor pattern 67 on the channel areas C and the underlying portions of the source/ drain intermediate layer pattern 57 are etched to be removed. Dry etching may be applied to both of the source/ drain conductor pattern 67 and the source/ drain intermediate layer pattern 57. Alternatively, wet etching is applied to the source/ drain conductor pattern 67 while dry etching is applied to the source/ drain intermediate layer pattern 57. At this time, as shown in Fig.
  • top portions of the semiconductor pattern 42 may be removed to cause thickness reduction, and the second portions 112 of the photoresist pattern is etched to a predetermined thickness.
  • the etching is performed under the condition that the gate insulating layer 30 is hardly etched, and it is preferable that the photoresist film is so thick to prevent the second portion 112 from being etched to expose the underlying data wire 62, 64, 65, 66 and 68.
  • the source and the drain electrodes 65 and 66 are separated from each other while completing the formation of the data wire 62, 64, 65, 66 and 68 and the underlying ohmic contact layer pattern 55, 56 and 58.
  • the second portions 112 remained on the data areas A are removed.
  • the removal of the second portions 112 may be made between the removal of the portions of the source/ drain conductor pattern 67 on the channel areas C and the removal of the underlying portions of the intermediate layer pattern 57.
  • first insulating layer 70 As shown in Figs. 23A-23C.
  • a second insulating layer 90 is formed on the first insulating layer 70 by spin-coating photosensitive organic material having a good flatness characteristic and low permittivity before patterning the first insulating layer 70.
  • the spin-coating of the second insulating layer 90 before patterning the first insulating layer 70 according to this embodiment of the present invention prevents the localized distribution of the second insulating layer 90 onto a specific area because there is no height difference due to the first insulating layer 70 during the spin coating.
  • the second insulating layer 90 is patterned by photolithography using a mask to form a plurality of contact holes 96 and 92 exposing portions of the first insulating layer 70 on the drain electrodes 66 and the storage capacitor conductor pattern 68. At this time, the portions the second insulating layer 90 at the pad areas with the gate pads 24 or the data pads 68 are removed to expose the first insulating layer 70.
  • the first insulating layer 70 as well as the gate insulating layer 30 is patterned by photo etch using a photoresist pattern to form a plurality of contact holes 74, 76, 72 and 78 exposing the gate pads 24, the drain electrodes 66, the storage capacitor conductor pattern 64 and the data pads 68, respectively.
  • the contact holes 76 and 72 of the first insulating layer 70 exposing the drain electrodes 66 and the storage capacitor conductor pattern 64 are placed inside the contact holes 96 and 92 of the second insulating layer 90.
  • ITO or IZO with a thickness of 400-500 A is deposited and etched using a fourth mask to form a plurality of pixel electrodes 82 connected to the drain electi'odes 66 and the storage capacitor conductor pattern 64, a plurality of subsidiary gate pads 84 connected to the gate pads 24, and a plurality of subsidiary data pads 84 and 88 connected to the data pads 68.
  • the fourth embodiment of the present invention provides not only the advantage according to the first embodiment but also a simplified process that the data wire 62, 64, 65, 66 and 68, the ohmic contact layer pattern 55, 56 and 58 and the semiconductor pattern 42 and 48 thereunder are formed using one mask, and simultaneously, the source and the drain electrodes 65 and 66 are separated from each other in this step.
  • connection between driving ICs and pads of a TFT array panel for an LCD manufactured by these methods is implemented by using tape carrier packages ("TCPs") with driving ICs mounted on respective films or by means of the chip on film (“COF”) style.
  • TCPs tape carrier packages
  • COF chip on film
  • the electrical connection therebetween is obtained by means of the above described COG style which directly mounts driving ICs on a panel.
  • the organic insulating layer is spin-coated on the underlying insulating layer while maintaining the minimized height difference without patterning the underlying insulating layer, thereby preventing the organic insulating material from being localized in a specific area.
  • This prevents image stains in a reflecting type LCD to improve the display characteristics.
  • the boundaries of a lower insulating layer are exposed at contact portions such that the sidewalls of contact holes have a stepwise shape, thereby removing undercut in the contact portions. These prevent the disconnections at the contact portions to ensure the reliability of the contact portions, thereby improving the display characteristics of the product.
  • the miniinization of the photo etch steps when manufacturing a TFT array panel for an LCD simplifies the manufacturing process and reduces the production cost.

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Abstract

L'invention concerne la formation sur un substrat d'un fil de grille, dans une direction transversale, comprenant des lignes de grille, des électrodes de grille et des plages de grille. Une couche d'isolante de grille est ensuite formée, puis séquentiellement sont formées une couche semi-conductrice et une couche de contact ohmique. Un matériau conducteur est alors déposé et structuré afin de former un fil de données comprenant des lignes de données réalisant des intersections avec les lignes de grille, les électrodes de source, les électrodes de drain et les plages de données. Une première couche isolante en nitrure de silicium est déposée sur le substrat, puis une seconde couche isolante constituée de matériau isolant organique photosensible est déposée sur la première couche isolante. La seconde couche isolante est structurée afin de former une structure inégale sur sa surface et des premiers trous de contact exposant la première couche isolante opposée aux électrodes de drain. Puis, la première couche isolante est structurée en même temps que la couche isolante de grille par gravure photochimique au moyen d'une structure en photorésine afin de former des trous de contact exposant respectivement les électrodes de drain, les plages de grille, et les plages de données. Un oxyde d'indium-étain (ITO) ou d'indium-zinc (IZO) est ensuite déposé et structuré afin de former des électrodes transparentes, des plages de grille auxiliaires et des plages de données auxiliaires respectivement connectées aux électrodes de drain, aux plages de grille et aux plages de données. Enfin, un matériau conducteur réfléchissant est déposé et structuré afin de former des films réfléchissants comportant des ouvertures dans la zone de pixel sur les électrodes transparentes.
PCT/KR2002/000805 2002-03-07 2002-04-30 Portion de contact de dispositif semi-conducteur et procede de fabrication associe, panneau de reseau de transistors en couche mince pour dispositif d'affichage contenant la portion de contact et procede de fabrication associe WO2003075356A1 (fr)

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CN1623235A (zh) 2005-06-01
KR100885022B1 (ko) 2009-02-20
CN100380682C (zh) 2008-04-09

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