WO2001050508A1

WO2001050508A1 - Etch and ash photoresist removal process

Info

Publication number: WO2001050508A1
Application number: PCT/US2000/035602
Authority: WO
Inventors: Edward Yeh
Original assignee: Koninklijke Philips Electronics, Nv; Philips Semiconductors, Inc.
Priority date: 1999-12-30
Filing date: 2000-12-29
Publication date: 2001-07-12
Also published as: EP1166342A1; JP2003519912A

Abstract

Photoresist removal from a semiconductor chip is enhanced via a method and system that remove photoresist without causing photoresist popping and without causing undesirable etching of other structures on the chip. According to an example embodiment of the present invention, a photoresist mask layer formed on the substrate of a semiconductor wafer is used as a mask for etching a portion f the substrate. The semiconductor wafer is then ashed and an upper portion of the photoresist layer is removed that would otherwise pop and leave residue on the wafer. The remaining photoresist can then be removed in a conventional high-temperature asher.

Description

ETCH AND ASH PHOTORESIST REMOVAL PROCESS

Field of the Invention

The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for improving photoresist removal.

Background of the Invention

The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. Such technological advances are coupled with a heightened complexity of the manufacturing process and increasingly higher standards of reliability, performance, and consistency of semiconductor wafers.

As the manufacturing processes for semiconductor wafers become more complex, and as product standards for such wafers increase, methods for manufacturing these wafers become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently and meet performance standards. In addition, as technology advances, the cost of manufacturing the high tech wafers increases. The increased cost of wafers results in greater losses when the wafers are defective and must be repaired or thrown out.

One process commonly used for substrate removal during semiconductor wafer processing is plasma etching. One particular application involves forming a photoresist pattern on the wafer substrate and using the pattern in connection with plasma etching to form wafer structure. During the plasma etch process, the photoresist is exposed to the energetic bombardment of ions as well as to the etch chemistry itself. This exposure can transform an upper layer of photoresist into a hard crust layer. When this photoresist having a transformed layer is placed into a conventional high-temperature asher, the stress difference between the crust layer and the unchanged photoresist below (induced by the high temperature) causes the crust layer to pop off. Once the photoresist has popped, it is more difficult to strip and will often leave residue on the wafer. More aggressive ash processes, such as the addition of CF₄ and/or N₂/H, to the ash chemistry, or a more aggressive wet strip process, such as the addition of an HF dip, have been used to remove popped resist. However, a more aggressive ash or wet strip process causes undesirable etching of other structures on the wafer. The resist residue, if left on the wafer, can even act as a mask for later etch, implant, or HF- based wet strip steps. These and other problems associated with popped photoresist impede the ability to consistently manufacture reliable high-performance semiconductor wafers.

Summary of the Invention The present invention is directed to the removal of photoresist from a semiconductor wafer, and is exemplified in a number of implementations and applications, some of which are summarized below.

According to an example embodiment of the present invention, a photoresist layer is formed over the substrate of a semiconductor wafer, and the substrate is etched. After etching, the wafer is ashed at a temperature sufficiently low enough not to cause the crust layer of photoresist to pop. Once the upper portion, or crust, of the photoresist layer is removed, the remainder can be removed in a conventional ashing process. By removing the upper portion of the photoresist layer before conventionally ashing the chip, the portion of the photoresist layer that is hardened during the etching step will not be present, and the detrimental effects of photoresist popping are reduced or eliminated.

In another example embodiment of the present invention, the removal of the photoresist crust layer is performed sequentially in the same tool as the plasma etching process. Plasma etch tools are typically operated at the same low temperatures required for photoresist crust removal. A plasma etching arrangement is arranged to use the photoresist as a mask for etching the substrate. After the substrate has been etched, a first ashing step is adapted to ash the semiconductor chip at a temperature sufficiently low to remove an upper portion of the photoresist layer and inhibit photoresist popping. A second ashing step in a conventional high temperature asher follows to remove the remainder of the photoresist.

The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.

Brief Description of the Drawings The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:

FIG. 1 is a semiconductor chip having undergone pholoresist deposition and an etch process, for use in connection with an example embodiment of the present invention;

FIG. 2 shows the semiconductor chip of FIG. 1 having undergone a first ashing process, according to an example embodiment of the present invention; and

FIG. 3 is an arrangement for etching a semiconductor wafer and sequentially performing a first ashing process, according to another example embodiment of the present invention.

While the present invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Detailed Description

The present invention is believed to be applicable for a variety of different types of semiconductor devices, and the invention has been found to be particularly suited for devices requiring or benefiting from the formation of structure having about vertical side walls. While the present invention is not necessarily limited to such devices, various aspects of the invention may be appreciated through a discussion of various examples using this context.

In connection with an example embodiment of the present invention, it has been discovered that the addition of an inert gas, such as helium, to a conventional etch gas as it is supplied for etching a semiconductor chip substrate can improve the side wall profile of structure formed from the substrate during an etch process. In addition, the inert gas improves the profile while maintaining good etch selectivity to material such as oxide located in the chip.

According to an example embodiment of the present invention, a semiconductor chip having substrate formed over a thin oxide is etched. FIG. 1 shows such a chip 100 having a substrate 120 formed over a thin gate oxide layer 1 10, and a mask 130 formed over a portion 140 of the substrate 120. The substrate may, for example, include gate material such as poly-silicon or amorphous silicon. In one particular implementation, the substrate includes an anti-reflective coating over the substrate 120.

FIG. 2 shows the chip 100 of FIG. 1 being etched. A plasma 230 is generated from an etch gas 210 and an inert gas 220, and is then supplied to the substrate 120. The etch gas 220 may, for example, include a plurality of gases. The etch and inert gas supplies, the plasma power, and the etch pressure at which the plasma is supplied are sufficient to achieve about vertical side wall profiles 250 of the masked portion 140 while maintaining the high etch selectivity. In one example implementation, an etch pressure of between about 5 - 100 mTorr, a plasma source power (for controlling the plasma density) of between about 50-400 W, and a plasma bias power (for controlling the energy supplied to the ions) of between about 10-200 W provide conditions adequate for achieving the about vertical side walls.

The mask 130 masks the portion 140 of the substrate, and the remaining substrate is etched, as shown in FIG. 3. The resulting structure 340 formed from the masked portion 140 of the substrate has about vertical side walls 350. In one implementation, the selectivity of the etch gas to the thin oxide layer 1 10, while in the presence of the inert gas, is about infinite. The infinite select! \ ity permits the formation of the structure 340 without etching the thin oxide layer 1 10, thereby reducing the harmful effects of problems, such as microtrenching, associated with etch processes that are not as highly selective. In addition, the inert gas can also improve the resulting structure by removing depositions on the side walls.

The etch and inert gas supply to the chip can be accomplished in various manners. For instance, in one implementation the chip 100 is placed in an etch chamber, and the gases are supplied to the chip via a supply to the etch chamber. The etch gas 210 may include, for example, a typical etch gas chemistry used in highly selective Si/SiO₂ etch processes. Helium can be supplied as the inert gas and used with the highly selective Si/SiO₂ etch chemistry for etching the chip. In one example implementation, the helium is supplied at a volumetric flow rate of between about 25- 500 seem. In another example implementation, the helium is supplied at a flow rate of at least about 500 seem. In still another example implementation, the inert gas and the etch gas are mixed prior to their introduction to the chip.

Referring again to FIG. 3, the side walls 350 of the resulting structure 340 are shown to be close to vertical. In one implementation, the resulting side walls have an included angle θ of at least about 85°, and in another the included angle θ is about 90°. This resulting structure 340 is useful because vertical side walls exhibit improved performance over side walls having a tapered profile. Although FIGs. 1-3 show one structure 340, it should be noted that a plurality of such structures may be formed on the chip. In addition, the chip may be part of a semiconductor wafer having a plurality of chips, some or all of which having a structure formed in a similar manner.

The structure formed using the combination of the etch and inert gases as described herein can be used for various applications in semiconductor device manufacture and processing. For example, the structure 340 in FIG. 3 may include a gate used in connection with a transistor. In one example implementation, the thin oxide 1 10 is a gate oxide, and the chip 100 includes structure such as source and drain regions near the gate. The present invention is particularly advantageous for the formation of deep sub-micron gate structure. For example, in one implementation a gate having a width of less than about 0.20 microns is formed. In another implementation a gate having a width of about 0.15 microns is formed. In still another implementation, a gate having a width of less than about 0.15 microns is formed. FIG. 4 is a flow diagram of an example process for manufacturing a semiconductor chip, according to another example embodiment of the present invention. A thin oxide layer is formed over a semiconductor chip at block 410. After the oxide layer is formed, a substrate, such as gate material including poly- silicon or amorphous silicon, is formed over the oxide at block 420. A mask material is patterned over the substrate at block 430, and the chip is then placed in an etch chamber at block 440. The mask may be patterned, for example, for forming one or more gate structures on the chip. A vacuum is drawn on the chamber at block 450, and an etch gas and an inert gas are supplied to the etch chamber and a plasma is generated at block 460. In one implementation, the etch pressure is held about constant during the addition of the inert gas. The plasma anisotropically etches the unmasked substrate in a manner that forms about vertical side wall profiles on the masked structures that are not etched. The unmasked substrate is etched while etching little or none of the thin oxide layer. After etch is complete, the mask material is removed from the chip at block 470. Optionally, the chip may then be annealed or further processed in other manners.

In still another example embodiment of the present invention, a semiconductor chip is manufactured. The chip includes a gate structure having at least one side wall that is about vertical and an underlying thin oxide. The gate structure is formed by patterning a mask over the structure and etching the structure with a highly selective etch gas while in the presence of an inert gas. The inert gas facilitates the formation of about vertical side walls while not degrading the selectivity of the etch gas. In this manner, the resulting gate profile has side walls that are about vertical, and the thin oxide layer is not etched due to the use and maintenance of the highly selective etch process.

While the present invention has been described with reference to several particular example embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the present invention, which is set forth in the following claims.

Claims

What is claimed is:

1. A method for etching a semiconductor chip having substrate and a photoresist layer formed over the substrate, the method comprising: etching the substrate; and ashing the semiconductor chip at a temperature sufficiently low to remo\ e an upper portion of the photoresist layer and inhibit photoresist popping.

2. The method of claim 1, further comprising subsequently ashing the semiconductor wafer at a second higher temperature, the second higher temperature being sufficiently high to remove a remaining portion of the photoresist layer.

3. The method of claim 2, wherein subsequently ashing is done at a temperature of about 250°C to about 300°C subsequent to removing the upper portion of the photoresist layer.

4. The method of claim 1, wherein etching the substrate includes using an etch tool, and wherein the ashing is performed while the semiconductor wafer is in the etch tool.

5. The method of claim 1 , wherein etching the substrate includes using an etch tool, and wherein the ashing is performed outside of the etch tool.

6. The method of claim 1, wherein the ashing is performed in an asher.

7. The method of claim 3, wherein the semiconductor wafer is first ashed in an asher at the lower temperature, then heated to a temperature of about 250°C to 300°C for the subsequent ashing.

8. The method of claim 4, wherein the etch tool has upper and lower electrodes, and wherein the bottom electrode is at a temperature of about 20°C.

9. The method of claim 4, wherein the etch tool includes upper and lower electrodes, and wherein the ashing includes ashing for about 20 seconds under the following conditions: a pressure of about 200 Torr, 400 W RF at the upper electrode, 200 W RF at the lower electrode, an O₂ flow rate of about 70 seem, and a lower electrode temperature of about 20°C.

10. The method of claim 1 , wherein the ashing is performed at a temperature below about 100°C.

1 1. The method of claim 1 , wherein the ashing is performed at a temperature of about 20°C.

12. The method of claim 1 , wherein the ashing includes removing a crust layer of the photoresist formed during a plasma etch process.