WO2001045171A1 - Ldmos power package with resistive-capacitive stabilizing element - Google Patents

Ldmos power package with resistive-capacitive stabilizing element Download PDF

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Publication number
WO2001045171A1
WO2001045171A1 PCT/US2000/033225 US0033225W WO0145171A1 WO 2001045171 A1 WO2001045171 A1 WO 2001045171A1 US 0033225 W US0033225 W US 0033225W WO 0145171 A1 WO0145171 A1 WO 0145171A1
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Prior art keywords
input
terminal
terminals
flange
capacitor
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Application number
PCT/US2000/033225
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French (fr)
Inventor
Gary George Lopes
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Ericsson Inc.
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Publication date
Application filed by Ericsson Inc. filed Critical Ericsson Inc.
Priority to AU22555/01A priority Critical patent/AU2255501A/en
Publication of WO2001045171A1 publication Critical patent/WO2001045171A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
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    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
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    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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Definitions

  • the present invention pertains generally to the field of radio frequency (RF) power transistor devices and, more specifically, to methods and apparatus for impedance matching of LDMOS power transistor packages.
  • RF radio frequency
  • LDMOS metal oxide semiconductor
  • a typical LDMOS RF power transistor package (also referred to herein as a "RF power package” or just “power package”) generally comprises a plurality of electrodes formed on a semiconductor die, each electrode comprising a plurality of transistors. The individual transistors of each electrode are connected to respective common input (gate) and output (drain) terminals formed on the surface of the die.
  • a common ground (source) terminal substrate is formed on the underlying side of the die.
  • the die is attached, e.g., by a known eutectic die attach process, to a metal flange serving as a combined ground current reference, heat spreader and mounting device for the package.
  • a thermally conductive, but electrically isolating, e.g., aluminum oxide, "window” substrate is attached to the flange, surrounding the die.
  • Respective input and output lead frames are attached, e.g., at opposing ends, to a top surface of the window substrate, electrically isolated from the flange.
  • the input and output lead frames are coupled to the respective electrode input and output terminals via respective input and output transmission paths, which may also include one or more impedance matching elements interposed between the respective lead frames and electrode terminals. Impedance matching between circuit elements external to the power package and the respective electrode terminals on the die is crucial to proper operation of the amplifier device, especially at high operating frequencies.
  • One known approach for improving impedance control in a FET-based power transistor package is to provide a constant termination impedance in the input transmission path by incorporating input gate resistors into the respective electrodes on the die or, in the alternative, in circuitry external to the transistor device.
  • this approach requires re-designing the die mask and/or additional cost and space requirements for the external circuitry.
  • a common series resistor is incorporated into an input matching capacitor in the input (gate) transmission path of a LDMOS power package.
  • the resistor provides a constant impedance element, as "seen” in either direction in the input transmission path, thereby adding a further impedance control element, without requiring individual gate resistors to be incorporated in the silicon die transistor layout.
  • an LDMOS power package includes a conductive flange serving as a relative ground, with a dielectric window substrate attached to, and exposing a portion of, the flange.
  • a silicon die is attached to the exposed portion of the flange within the window substrate, the die having a plurality of electrodes formed thereon, the electrodes each having respective input (gate) terminals, output (drain) terminals and a common ground (source) terminal, the ground terminal electrically coupled to the flange.
  • An input lead is attached to the window substrate, electrically isolated from the flange, and is electrically coupled to the electrode input terminals via an input transmission path.
  • the input transmission path includes a matching capacitor attached to the flange, the input matching capacitor having a first terminal electrically coupled to the input lead and a second terminal electrically coupled to the electrode input terminals.
  • the first and second capacitor terminals are separated from the ground flange by a dielectric layer, with the first capacitor terminal electrically coupled to the second capacitor terminal by a resistive path forming a common gate resistor in the input transmission path.
  • the resistive path comprises a diffusion layer formed in dielectric layer of the input matching capacitor.
  • the resistive path may also be deposited on the dielectric layer of the input matching capacitor between the first and second terminals.
  • One advantage of the present invention is that high frequency, LDMOS power package performance can be enhanced with addition of a common series gate resistance in the package itself, without requiring a re-design of an existing silicon die mask. Another advantage is that that common input gate resistance is added without requiring further circuitry external to the transistor package.
  • FIG. 1 is a top view of a preferred LDMOS power package constructed in accordance with the present invention, including an input matching capacitor having a resistor formed thereon;
  • FIG. 2 is a top view of the input matching capacitor of FIG. 1;
  • FIG. 3 is partially cut-away side view of the input matching capacitor of FIG. 1;
  • FIG. 4 is a simplified schematic of the power package of FIG. 1;
  • FIG. 5 is a top view of an alternate embodiment of the power package of FIG. 1, including a plurality of input matching capacitors;
  • FIG. 6 is a simplified schematic of the power package of FIG. 5;
  • FIG. 7 is a top view of an further alternate embodiment of the power package of FIG. 1;
  • FIG. 8 is a top view of an input matching capacitor having a common resistor formed thereon in the power package of FIG. 7;
  • FIG. 9 is partially cut-away side view of the input matching capacitor of FIG. 8; and FIG. 10 is a simplified schematic of the power package of FIG. 7.
  • a first preferred LDMOS power package 20 generally includes a conductive mounting flange 22, e.g., made of a copper-tungsten alloy, which serves as a combined relative ground reference, heat spreader and mounting substrate.
  • the window substrate 24 has an inner perimeter 28, which defines a window 30 exposing a portion of the mounting flange surface 26.
  • a silicon die 32 having a plurality of interdigitated transistor electrodes 34 formed thereon is attached to the top flange surface 26 within the window 30.
  • the electrodes 34 have respective input (gate) terminals 36 and output (drain) terminals 38 formed on a top surface 38 of the die 36.
  • the electrodes 34 also have a common (source) terminal (40), e.g., made of gold or a gold alloy, formed on the underside of the die 36, which is attached to the flange surface 26, e.g., by ultrasonic scrubbing and/or thermal heating.
  • An input lead 42 is attached at one end of a top surface 44 of the window substrate
  • the LDMOS power package 20 may have other inputs and/or leads, such as a bias voltage lead, which are not directly related to the present invention and, thus, which are omitted for purposes of simplification.
  • a first plurality of conductive bond wires 48 couple the input lead 42 to a first terminal 50 of an input matching capacitor (MOSCAP) 52 attached to the flange surface 26.
  • a second plurality of bond wires 54 couple a second terminal 56 of the input MOSCAP 52 to the electrode input (gate) terminals 36 on the die 32.
  • the input MOSCAP 52 is preferably conventionally constructed from a silicon wafer 66.
  • a thin oxide layer (i.e., silicon dioxide) 70 is formed in the silicon wafer 66, e.g., by exposing the silicon to oxygen and high temperature. Alternately, the layer 70 could be formed by a diffused nitride.
  • the respective first and second terminals 56 and 58 are each preferably comprised of a thin, conductive metal layer, such as gold, which are deposited over the silicon dioxide layer 70.
  • a further (ground) terminal 68 comprising a thin layer of gold, or a gold alloy, is deposited on the underside of the silicon wafer 66 and attached directly to the flange surface 26, e.g., by ultrasonic scrubbing and/or thermal heating.
  • the first capacitor terminal 50 is relatively narrow and, preferably, has a width no greater than is necessary to allow for termination of the plurality of bond wires 48, e.g., 5- 6 mils in a preferred embodiment.
  • the second capacitor terminal 56 is significantly greater in width, e.g., 10 to 15 times greater in a preferred embodiment, such that the first terminal 50 contributes very little to the overall capacitance of the input MOSCAP 52 relative to the second terminal 56.
  • the MOSCAP 52 reduces, or steps down, the impedance "seen” on the input wires 48. The actual step down in impedance depends on many factors, including the number and length of the respective bond wires 48, and the operating parameters of the power package 120.
  • the first and second capacitor terminals 50 and 56 are electrically coupled through a resistor 72 formed by a diffusion of, e.g., platinum suicide, in the exposed silicon dioxide region extending between the first and second terminals 50 and 56.
  • the resistor 72 could be formed by could be a deposited layer extending between the respective terminals 50 and 56 on the surface of the silicon dioxide area 70.
  • a diffused resistor is preferred as it is generally more reliable than a deposited resistor.
  • the resistor 72 which is preferably uniform across the gap extending between the respective first and second capacitor terminals 50 and 56, provides a constant input impedance within the input transmission path of the power package 20.
  • input matching of the power package 20 is performed by selection of the value of the input matching MOSCAP 52, which is based on the relative size of the second terminal 56 and depth of the silicon wafer 66, as well as the resistance value of resistor 72 and the inductance of wires 48 and 54, which is based on the number and length of the respective groups of wires.
  • a further plurality of bond wires 58 couple the respective electrode output terminals 38 to a top-side terminal 60 of an output matching MOSCAP 62.
  • a second terminal (not shown) of the blocking capacitor 62 is coupled to the flange surface 26.
  • the output lead frame 46 is coupled to the output blocking capacitor 62 by a still further plurality of bond wires 64. Because the impedance of the respective electrode output terminals 38 is significantly higher than that of the input terminals, the "set-up" value of the output matching MOSCAP 62 will be much less than the "step down" value of input matching MOSCAP 52. In a preferred embodiment, the impedance seen at the input lead
  • FIG. 4 shows a simplified schematic representation of the power package 20, wherein the transmission inductance through the respective bond wires is designated by the corresponding reference numbers of the wires in FIG. 1.
  • the impedance at the electrode input terminals 36 is relatively low, e.g., less than two ohms in one known application, compared with the input lead impedance, typically 50 ohms, it may be desirable to employ a second input matching
  • MOSCAP 74 in the input transmission path of the power package (designated as 20'). In particular, instead of coupling the second terminal 56 of the first input
  • the plurality of bond wires couple capacitor terminal 56 to a first terminal 78 of a second input matching MOSCAP 74.
  • a second terminal (not shown) of the second input matching MOSCAP 74 is coupled to the flange surface 26.
  • a further set of bond wires 76 couple the capacitor terminal 78 to the low impedance electrode input terminals 36.
  • MOSCAP 74 further steps down the impedance on the input transmission path - i.e., as “seen” on the respective input wires 54 and 76. Again, the actual step down in impedance between the first input matching MOSCAP 52, second input matching MOSCAP 74 and the electrode input terminals 36 depends on many factors, including the selected number and length of the respective bond wires 54 and 76, and the operating parameters of the device 20'. Because the impedance at the output electrode terminals 38 is relatively higher than at the input terminals 134, only the single output matching MOSCAP 62 is normally employed to "step up" the impedance between the output electrode terminals 38 and the output lead 46.
  • FIG. 6 shows a simplified schematic representation of the power package 20', wherein the transmission inductance through the respective bond wires is again designated by the corresponding reference numbers of the wires in FIG. 5.
  • the exact location of the common gate resistance need not be adjacent the input lead, but can be suitably positioned anywhere in the input transmission path.
  • the location of the common gate resistance is moved in FIG. 7.
  • the first plurality of bond wires 48 couple the input lead 42 to the (only) terminal 56' of the first input matching capacitor 52'.
  • the second plurality of bond wires 54 couple capacitor terminal 56' to the first terminal 78' of the second input matching MOSCAP 74'.
  • the third plurality of bond wires 76 couple a second terminal 80 of the second input matching MOSCAP 74' to the electrode input terminals 36, with the first and second terminals 78' and 80 of MOSCAP 74' electrically coupled by a common gate resistor 82 formed in the MOSCAP surface.
  • the second MOSCAP 74' of power package 20" is preferably identical in construction to the MOSCAP 52 of packages 20 and 20', except that the resistor 82 is formed proximate the silicon die side of the input transmission path, ⁇ i.e., with the second terminal 80 is negligible in width compared with terminal 78'.
  • FIG. 10 shows a simplified schematic representation of the power package 20", wherein the transmission inductance through the respective bond wires is again designated by the corresponding reference numbers of the wires in FIG. 7.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Microwave Amplifiers (AREA)

Abstract

An impedance matched LDMOS power transistor package (20) includes a conductive flange (22) serving as a combined heat spreader, mounting mechanism and relative ground, with a dielectric window substrate (24) attached to, and exposing a portion of, the flange. A silicon die (32) is attached to the exposed portion of the flange within the window substrate, the die having a plurality of electrodes (34) formed thereon, the electrodes each having respective input (gate) (36) and output (drain) (38) terminals, the ground terminals (40) electrically coupled to the flange. An input lead (42) is attached to the window substrate, electrically isolated from the flange, the input lead electrically coupled to the electrode input terminals (36) via an input transmission path. The input transmission path includes an input matching capacitor (52) having a first terminal (50) electrically coupled to the input lead, a second terminal (56) electrically coupled to the electrode input terminals, and a ground terminal (68). The first and second capacitor terminals are separated from the ground terminal by a dielectric layer (70), with the first capacitor terminal electrically coupled to the second capacitor terminal by a resistive path (72), the resistive path forming a common gate resistor along the input transmission path.

Description

LDMOS POWER PACKAGE WITH RESISTIVE-CAP ACITIVE STABILIZING
ELEMENT
BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention pertains generally to the field of radio frequency (RF) power transistor devices and, more specifically, to methods and apparatus for impedance matching of LDMOS power transistor packages.
2. Background
The use of RF power transistor devices as signal amplifiers in wireless communication applications is well known. With the considerable recent growth in the demand for wireless services, such as personal communication services, the operating frequency of wireless networks has increased dramatically and is now well into the gigahertz frequencies. At such high frequencies, laterally diffused, metal oxide semiconductor (LDMOS) transistors have been preferred for RF power amplification applications, e.g., for use in antenna base stations.
A typical LDMOS RF power transistor package (also referred to herein as a "RF power package" or just "power package") generally comprises a plurality of electrodes formed on a semiconductor die, each electrode comprising a plurality of transistors. The individual transistors of each electrode are connected to respective common input (gate) and output (drain) terminals formed on the surface of the die. A common ground (source) terminal substrate is formed on the underlying side of the die. The die is attached, e.g., by a known eutectic die attach process, to a metal flange serving as a combined ground current reference, heat spreader and mounting device for the package. A thermally conductive, but electrically isolating, e.g., aluminum oxide, "window" substrate is attached to the flange, surrounding the die. Respective input and output lead frames are attached, e.g., at opposing ends, to a top surface of the window substrate, electrically isolated from the flange. The input and output lead frames are coupled to the respective electrode input and output terminals via respective input and output transmission paths, which may also include one or more impedance matching elements interposed between the respective lead frames and electrode terminals. Impedance matching between circuit elements external to the power package and the respective electrode terminals on the die is crucial to proper operation of the amplifier device, especially at high operating frequencies. One known approach for improving impedance control in a FET-based power transistor package is to provide a constant termination impedance in the input transmission path by incorporating input gate resistors into the respective electrodes on the die or, in the alternative, in circuitry external to the transistor device. However, this approach requires re-designing the die mask and/or additional cost and space requirements for the external circuitry.
Thus, it would be desirable to provide a power package design in which a constant termination impedance in the input transmission path is more easily provided.
SUMJY ARY OF THE INVENTION In accordance with the present invention, a common series resistor is incorporated into an input matching capacitor in the input (gate) transmission path of a LDMOS power package. In particular, the resistor provides a constant impedance element, as "seen" in either direction in the input transmission path, thereby adding a further impedance control element, without requiring individual gate resistors to be incorporated in the silicon die transistor layout.
In a preferred embodiment, an LDMOS power package includes a conductive flange serving as a relative ground, with a dielectric window substrate attached to, and exposing a portion of, the flange. A silicon die is attached to the exposed portion of the flange within the window substrate, the die having a plurality of electrodes formed thereon, the electrodes each having respective input (gate) terminals, output (drain) terminals and a common ground (source) terminal, the ground terminal electrically coupled to the flange. An input lead is attached to the window substrate, electrically isolated from the flange, and is electrically coupled to the electrode input terminals via an input transmission path.
The input transmission path includes a matching capacitor attached to the flange, the input matching capacitor having a first terminal electrically coupled to the input lead and a second terminal electrically coupled to the electrode input terminals. The first and second capacitor terminals are separated from the ground flange by a dielectric layer, with the first capacitor terminal electrically coupled to the second capacitor terminal by a resistive path forming a common gate resistor in the input transmission path.
In a preferred embodiment, the resistive path comprises a diffusion layer formed in dielectric layer of the input matching capacitor. Alternately, the resistive path may also be deposited on the dielectric layer of the input matching capacitor between the first and second terminals.
One advantage of the present invention is that high frequency, LDMOS power package performance can be enhanced with addition of a common series gate resistance in the package itself, without requiring a re-design of an existing silicon die mask. Another advantage is that that common input gate resistance is added without requiring further circuitry external to the transistor package.
As will be apparent to those skilled in the art, other and further aspects and advantages of the present invention will appear hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the present invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like reference numerals refer to like components, and in which: FIG. 1 is a top view of a preferred LDMOS power package constructed in accordance with the present invention, including an input matching capacitor having a resistor formed thereon;
FIG. 2 is a top view of the input matching capacitor of FIG. 1;
FIG. 3 is partially cut-away side view of the input matching capacitor of FIG. 1; FIG. 4 is a simplified schematic of the power package of FIG. 1;
FIG. 5 is a top view of an alternate embodiment of the power package of FIG. 1, including a plurality of input matching capacitors;
FIG. 6 is a simplified schematic of the power package of FIG. 5;
FIG. 7 is a top view of an further alternate embodiment of the power package of FIG. 1;
FIG. 8 is a top view of an input matching capacitor having a common resistor formed thereon in the power package of FIG. 7;
FIG. 9 is partially cut-away side view of the input matching capacitor of FIG. 8; and FIG. 10 is a simplified schematic of the power package of FIG. 7.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a first preferred LDMOS power package 20 generally includes a conductive mounting flange 22, e.g., made of a copper-tungsten alloy, which serves as a combined relative ground reference, heat spreader and mounting substrate. A dielectric window substrate 24, e.g., made of aluminum oxide ("alumina") or beryllium oxide, is attached to a top surface 26 of the mounting flange 22. The window substrate 24 has an inner perimeter 28, which defines a window 30 exposing a portion of the mounting flange surface 26.
A silicon die 32 having a plurality of interdigitated transistor electrodes 34 formed thereon is attached to the top flange surface 26 within the window 30. The electrodes 34 have respective input (gate) terminals 36 and output (drain) terminals 38 formed on a top surface 38 of the die 36. The electrodes 34 also have a common (source) terminal (40), e.g., made of gold or a gold alloy, formed on the underside of the die 36, which is attached to the flange surface 26, e.g., by ultrasonic scrubbing and/or thermal heating. An input lead 42 is attached at one end of a top surface 44 of the window substrate
24, electrically isolated from the flange 22. An output lead 46 is attached at an opposite end of the window substrate surface 44, also electrically isolated from the flange 22. The input lead 42 is electrically coupled to the electrode input (gate) terminals 36 via an input transmission path, and the output lead 46 is attached to the electrode output (drain) terminals 38 via an output transmission path. As will be appreciated by those skilled in the art, the LDMOS power package 20 may have other inputs and/or leads, such as a bias voltage lead, which are not directly related to the present invention and, thus, which are omitted for purposes of simplification.
A first plurality of conductive bond wires 48 couple the input lead 42 to a first terminal 50 of an input matching capacitor (MOSCAP) 52 attached to the flange surface 26. A second plurality of bond wires 54 couple a second terminal 56 of the input MOSCAP 52 to the electrode input (gate) terminals 36 on the die 32.
With reference to FIGS. 2 and 3, the input MOSCAP 52 is preferably conventionally constructed from a silicon wafer 66. A thin oxide layer (i.e., silicon dioxide) 70 is formed in the silicon wafer 66, e.g., by exposing the silicon to oxygen and high temperature. Alternately, the layer 70 could be formed by a diffused nitride. The respective first and second terminals 56 and 58 are each preferably comprised of a thin, conductive metal layer, such as gold, which are deposited over the silicon dioxide layer 70. A further (ground) terminal 68 comprising a thin layer of gold, or a gold alloy, is deposited on the underside of the silicon wafer 66 and attached directly to the flange surface 26, e.g., by ultrasonic scrubbing and/or thermal heating.
The first capacitor terminal 50 is relatively narrow and, preferably, has a width no greater than is necessary to allow for termination of the plurality of bond wires 48, e.g., 5- 6 mils in a preferred embodiment. The second capacitor terminal 56 is significantly greater in width, e.g., 10 to 15 times greater in a preferred embodiment, such that the first terminal 50 contributes very little to the overall capacitance of the input MOSCAP 52 relative to the second terminal 56. As will be appreciated by those skilled in the art, the MOSCAP 52 reduces, or steps down, the impedance "seen" on the input wires 48. The actual step down in impedance depends on many factors, including the number and length of the respective bond wires 48, and the operating parameters of the power package 120. In accordance with the present invention, the first and second capacitor terminals 50 and 56 are electrically coupled through a resistor 72 formed by a diffusion of, e.g., platinum suicide, in the exposed silicon dioxide region extending between the first and second terminals 50 and 56. Alternately, the resistor 72 could be formed by could be a deposited layer extending between the respective terminals 50 and 56 on the surface of the silicon dioxide area 70. Notably, a diffused resistor is preferred as it is generally more reliable than a deposited resistor. In either case, the resistor 72, which is preferably uniform across the gap extending between the respective first and second capacitor terminals 50 and 56, provides a constant input impedance within the input transmission path of the power package 20.
In particular, input matching of the power package 20 is performed by selection of the value of the input matching MOSCAP 52, which is based on the relative size of the second terminal 56 and depth of the silicon wafer 66, as well as the resistance value of resistor 72 and the inductance of wires 48 and 54, which is based on the number and length of the respective groups of wires.
A further plurality of bond wires 58 couple the respective electrode output terminals 38 to a top-side terminal 60 of an output matching MOSCAP 62. A second terminal (not shown) of the blocking capacitor 62 is coupled to the flange surface 26. The output lead frame 46 is coupled to the output blocking capacitor 62 by a still further plurality of bond wires 64. Because the impedance of the respective electrode output terminals 38 is significantly higher than that of the input terminals, the "set-up" value of the output matching MOSCAP 62 will be much less than the "step down" value of input matching MOSCAP 52. In a preferred embodiment, the impedance seen at the input lead
42 is substantially matched to the impedance seen at the output lead 46, e.g., to approximately fifty ohms. FIG. 4 shows a simplified schematic representation of the power package 20, wherein the transmission inductance through the respective bond wires is designated by the corresponding reference numbers of the wires in FIG. 1.
Referring to FIG. 5, because the impedance at the electrode input terminals 36 is relatively low, e.g., less than two ohms in one known application, compared with the input lead impedance, typically 50 ohms, it may be desirable to employ a second input matching
MOSCAP 74 in the input transmission path of the power package (designated as 20'). In particular, instead of coupling the second terminal 56 of the first input
MOSCAP 52 to the electrode input terminals 36, the plurality of bond wires couple capacitor terminal 56 to a first terminal 78 of a second input matching MOSCAP 74. A second terminal (not shown) of the second input matching MOSCAP 74 is coupled to the flange surface 26. A further set of bond wires 76 couple the capacitor terminal 78 to the low impedance electrode input terminals 36.
As will be appreciated by those skilled in the art, the second input matching
MOSCAP 74 further steps down the impedance on the input transmission path - i.e., as "seen" on the respective input wires 54 and 76. Again, the actual step down in impedance between the first input matching MOSCAP 52, second input matching MOSCAP 74 and the electrode input terminals 36 depends on many factors, including the selected number and length of the respective bond wires 54 and 76, and the operating parameters of the device 20'. Because the impedance at the output electrode terminals 38 is relatively higher than at the input terminals 134, only the single output matching MOSCAP 62 is normally employed to "step up" the impedance between the output electrode terminals 38 and the output lead 46.
FIG. 6 shows a simplified schematic representation of the power package 20', wherein the transmission inductance through the respective bond wires is again designated by the corresponding reference numbers of the wires in FIG. 5. Notably, the exact location of the common gate resistance need not be adjacent the input lead, but can be suitably positioned anywhere in the input transmission path. By way of further illustration, the location of the common gate resistance is moved in FIG. 7.
In particular, in a further variation of the power package, designated as 20", the first plurality of bond wires 48 couple the input lead 42 to the (only) terminal 56' of the first input matching capacitor 52'. The second plurality of bond wires 54 couple capacitor terminal 56' to the first terminal 78' of the second input matching MOSCAP 74'. The third plurality of bond wires 76 couple a second terminal 80 of the second input matching MOSCAP 74' to the electrode input terminals 36, with the first and second terminals 78' and 80 of MOSCAP 74' electrically coupled by a common gate resistor 82 formed in the MOSCAP surface.
As best seen in FIGS. 8 and 9, the second MOSCAP 74' of power package 20" is preferably identical in construction to the MOSCAP 52 of packages 20 and 20', except that the resistor 82 is formed proximate the silicon die side of the input transmission path, ~ i.e., with the second terminal 80 is negligible in width compared with terminal 78'.
FIG. 10 shows a simplified schematic representation of the power package 20", wherein the transmission inductance through the respective bond wires is again designated by the corresponding reference numbers of the wires in FIG. 7.
While preferred embodiments for providing a common gate resistor in the input transmission path of an LDMOS power package have been shown and described, as would be apparent to those skilled in the art, many modifications and applications are possible without departing from the inventive concepts herein.
Thus, the scope of the disclosed invention is not to be restricted except in accordance with the appended claims.

Claims

CLAIMS What is claimed is:
1. An LDMOS power transistor package, comprising: a conductive flange serving as a relative ground; a semiconductor die attached to the flange and having a plurality of electrodes formed thereon, the electrodes having respective input and output terminals; an input lead electrically isolated from the flange; and an input matching capacitor attached to the flange, the input matching capacitor having a first terminal electrically coupled to the input lead and a second terminal electrically coupled to the electrode input terminals, wherein the first and second capacitor terminals are separated from the ground flange by a dielectric material, with the first terminal electrically coupled to the second terminal through a resistive path.
2. The LDMOS power package of claim 1 , wherein the first capacitor terminal is substantially smaller than the second capacitor terminal and makes a negligible contribution to a total capacitance of the input matching capacitor.
3. The LDMOS power package of claim 1 , wherein the second capacitor terminal is substantially smaller than the first capacitor terminal and makes a negligible contribution to a total capacitance of the input matching capacitor.
4. The LDMOS power package of claim 1, wherein the resistive path comprises a diffusion layer formed in dielectric layer of the input matching capacitor.
5. The LDMOS power package of claim 1, wherein the resistive path is deposited on the dielectric layer of the input matching capacitor between the first and second terminals.
6. The LDMOS power package of claim 1 , wherein the input matching capacitor is one of a plurality of matching capacitors in an electrically conductive path coupling the input lead to the electrode input terminals.
7. The LDMOS power package of claim 1 , wherein the dielectric material is silicon.
8. An LDMOS power transistor package, comprising: a conductive flange serving as a relative ground; a semiconductor die attached to the flange and having a plurality of electrodes formed thereon, the electrodes having respective input (gate) terminals and output (drain) terminals; an input lead electrically isolated from the flange; and an input matching capacitor attached to the flange, the input matching capacitor having a first terminal electrically coupled to the input lead and a second terminal electrically coupled to the electrode input terminals, wherein the first and second terminals are separated from the ground flange by a dielectric layer, with the first terminal electrically coupled to the second terminal through a resistive path forming a common gate resistor.
9. The LDMOS power package of claim 8, wherein the first capacitor terminal is substantially smaller than the second capacitor terminal and makes a negligible contribution to a total capacitance of the input matching capacitor.
10. The LDMOS power package of claim 8, wherein the second capacitor terminal is substantially smaller than the first capacitor terminal and makes a negligible contribution to a total capacitance of the input matching capacitor.
11. The LDMOS power package of claim 8, wherein the input lead is coupled to the first capacitor terminal by a first plurality of bond wires, and the second capacitor terminal is coupled to the electrode input terminals by a second plurality of bond wires.
12. The LDMOS power package of claim 8, wherein the resistive path comprises a diffusion layer formed in dielectric layer of the input matching capacitor.
13. The LDMOS power package of claim 8, wherein the resistive path is deposited on the dielectric layer of the input matching capacitor between the first and second terminals.
14. The LDMOS power p ickage of claim 8, wherein the input matching capacitor is one of a plurality of capacitors in an electrically conductive path coupling the input lead to electrode input terminals.
15. An LDMOS power transistor package, comprising: a conductive flange serving as a relative ground; a dielectric window substrate attached to the flange, the substrate forming a window exposing a portion of the flange; a semiconductor die attached to the exposed portion of the flange within the substrate window, the die having a plurality of electrodes formed thereon, the electrodes each having respective input (gate) terminals, output (drain) terminals and a common ground (source) terminal, the ground terminal electrically coupled to the flange; and an input lead attached to the window substrate, the input lead electrically coupled to the electrode input terminals via an input transmission path including a first input matching capacitor attached to the flange, the first input matching capacitor comprising a first terminal electrically coupled to the input lead via a first portion of the input transmission path, and a second terminal electrically coupled to the electrode input terminals via a second portion of the input transmission path, wherein the first and second terminals are separated from the flange by a dielectric layer, with the first terminal electrically coupled to the second terminal by a resistive path forming a common gate resistor in the input transmission path.
16. The LDMOS power package of claim 15, further comprising a second input matching capacitor attached to the flange, wherein the first input matching capacitor is proximate the input lead, and the second input matching capacitor is proximate the electrode input terminals, respectively, in the input transmission path.
17. The LDMOS power package of claim 15, further comprising a second input matching capacitor attached to the flange, wherein the first input matching capacitor is proximate the electrode input terminals and the second input matching capacitor is proximate the input lead, respectively, in the input transmission path.
PCT/US2000/033225 1999-12-15 2000-12-06 Ldmos power package with resistive-capacitive stabilizing element WO2001045171A1 (en)

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EP0015709A1 (en) * 1979-03-10 1980-09-17 Fujitsu Limited Constructional arrangement for semiconductor devices
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EP0015709A1 (en) * 1979-03-10 1980-09-17 Fujitsu Limited Constructional arrangement for semiconductor devices
US4354163A (en) * 1980-04-30 1982-10-12 Ford Aerospace & Communications Corporation High voltage buffer amplifier
JPS5791542A (en) * 1980-11-29 1982-06-07 Toshiba Corp High frequency transistor device
US5371405A (en) * 1992-02-04 1994-12-06 Mitsubishi Denki Kabushiki Kaisha High-frequency high-power transistor

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