WO2001008314A2 - Method and apparatus for high-speed software reconfigurable code division multiple access communication - Google Patents
Method and apparatus for high-speed software reconfigurable code division multiple access communication Download PDFInfo
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- WO2001008314A2 WO2001008314A2 PCT/BE2000/000086 BE0000086W WO0108314A2 WO 2001008314 A2 WO2001008314 A2 WO 2001008314A2 BE 0000086 W BE0000086 W BE 0000086W WO 0108314 A2 WO0108314 A2 WO 0108314A2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/26—Circuits for superheterodyne receivers
- H04B1/28—Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70707—Efficiency-related aspects
- H04B2201/7071—Efficiency-related aspects with dynamic control of receiver resources
Definitions
- the present invention is- related to a communication device for W-CDMA signals which is software reconfigurable .
- the present invention is further related to a method for operating said device.
- the present invention aims to provide a W- CDMA apparatus which allows the implementation of various telecommunication standards, and various applications realisable according to these standards, without the need for a powerful DSP processor for the flexible part of the physical layer.
- a further aim is to provide said apparatus for various fading channel circumstances .
- Another aim is to provide said apparatus under the form of an Intellectual Property core.
- the present invention concerns a communication device for W-CDMA signal transmission and reception, which is software configurable, comprising: -a W-CDMA transmitter comprising RAM and/or registers; -a W-CDMA receiver comprising RAM and/or registers; and -signal acquisition means, characterised m that it further comprises a digital circuit for phase unbalance precompensation, said circuit comprising: - an input register holding the compensation angle, - means for performing arithmetic to acquire a change of the I,Q angle by the compensation angle.
- said communication device further comprises a circuit for noise and interference estimation, said circuit comprising :
- said communication device further comprises a circuit for initial synchronization, said circuit comprising : -a Matched Filter, energy calculation and accumulating RAM for slot synchronization,
- said communication device further comprises circuitry to generate packet data transmission, said circuitry comprising : -A data and activity bits holding buffer, -I , Q spreaders and gam control means, -scrambling code generator and scrambling means, -means for packet timing through RX frame edge triggering.
- the present invention is equally related to the use of a communication device according to the present invention, for RACH transmission m UMTS/FDD.
- Software reconfigurable means that parameters of a circuit and/or algorithmic alternatives for this circuit can be configured using software settings.
- the circuit itself is built up of logic, and contains memory (such as registers and/or RAM) which are preferably controlled by a processor subsystem, which performs the above mentioned software settings.
- memory such as registers and/or RAM
- Said communication device can further comprise a processor.
- Such a processor can be any kind of processor capable of changing the settings of the device. Examples of such processors are DSP processors, microprocessors, microcontrollers, FPGA, logic circuits and FSM circuits.
- the communication device is preferably characterised m that the processor is arranged to reconfigure the communication device.
- Said processor preferably controls the RAM and/or registers of said W-CDMA signal transmitter and receiver.
- the transmitter preferably comprises a first programmable pulse shaping filter and the receiver preferably comprises a second programmable pulse shaping filter which can be programmable to perform GMSK filtering while said transmitter and receiver are arranged to interface with a GSM fron -end.
- the processor can be arranged to perform the GSM protocol stack.
- the communication device of the present invention is arranged for waveform transmission and/or reception and/or acquisition of signals selected from the group consisting of UMTS, Satellite UMTS, Galileo, GPS, IS-2000, IMT-2000, CDMA2000, IS-95, 3GPP, 3GPP2 and ARIB signals.
- the transmitter of the device according to the present invention can comprise one or more elements selected from the group consisting of : "synchronisation hardware to slave transmit start epochs to events external to the transmitter; •a burst generator for realising discontinuous transmissions ; •a QPN channel containing one or more spreaders w th their own amplification of the output ,-
- the PN code generator can be realised as a RAM m which the PN codes are downloaded under control of the processor.
- the scrambling code generator can be realised as a programmable Gold Code generator.
- the QPN channel can be arranged to execute UMTS forward or return link transmission.
- the amplification of the spreader output is preferably arranged to perform transmit power control .
- the transmitter of the device according to the present invention preferably comprises a time interpolator to perform sub-chip time alignments (e.g. for S-CDMA) .
- the transmitter of the device according to the present invention can be arranged for multi-code transmission.
- the receiver of the communication device of the present invention can comprise: •A pulse shaping filter; •An optional level control block;
- Said receiver preferably further comprises a downconverter prior to said pulse shaping filter, m order to interface at a front -end at an intermediate frequency.
- It can also be arranged for execution of UMTS, Satellite UMTS, Galileo, GPS, IS-2000, IMT-2000, CDMA2000, IS-95,
- 3GPP, 3GPP2 and/or ARIB forward link and return link waveforms are examples of 3GPP, 3GPP2 and/or ARIB forward link and return link waveforms .
- the level control block preferably comprises:
- the level control block is preferably operated m a runtime control loop by the processor.
- the demodulator preferably comprises:
- Rake filter producing a signal at chip rate which is a coherent accumulation of channel corrected multipath components resulting from one base station; •a tracking unit, using said signal at chip rate for descramblmg and despread g a plurality of waveform channels ; which said Rake filter comprises : »a FIFO to buffer samples at chip rate, coming from said level control block; •a delay line containing a plurality of registers, the input of the delay line being connected to the output of «a plurality of finger blocks, the inputs of said finger blocks being connected to programmable tap positions on said delay line; and •a summator of complex outputs of said finger blocks at chip rate.
- the finger blocks are preferably respectively grouped m a late multipath group and an early multipath group, the Rake filter being arranged to accumulate the energies of the outputs of said late multipath group and said early multipath group, and to use these accumulated values to feed the time error detector of the DLL used for time tracking.
- the Rake filter can comprise memories to hold one or more of the following:
- the finger block preferably comprises:
- the finger can be arranged for slow and fast fading compensation, by programming the channel correction
- said channel correction Pilot filter for slow fading, said channel correction Pilot filter first performing a coherent accumulation over a slot, and secondly performing a weighted average over previous -previous, previous, actual and next obtained slot values, yielding a channel estimation per slot, which is applied by said channel corrector; and for fast fading, said channel correction Pilot filter first performing a coherent accumulation over a slot, and then deriving channel estimations through interpolating consecutive said coherent accumulations over a slot, yielding channel estimations with sub-symbol timing, which are applied by said channel corrector.
- the reference demodulator preferably comprises : •an accumulator of programmable length of the absolute values of samples at chip rate; and
- the reference demodulator can be arranged to operate in a runtime control loop by the processor.
- the demodulator is preferably arranged to perform satellite diversity.
- the communication device of the present invention can be arranged to perform accurate ranging measurements to geostationary satellites.
- a further aspect of the present invention is an Intellectual Property core comprising the communication device of the present invention (as a building block for inclusion in an integrated circuit) .
- Another aspect of the present invention is a method for operating a W-CDMA communication device of the present invention, characterised in that it comprises the following steps :
- Said waveform signals are preferably selected from the group consisting of UMTS, Satellite UMTS, Galileo, GPS, IS-2000, IMT-2000, CDMA2000, IS-95, 3GPP, 3GPP2 and ARIB signals.
- Said configuring is preferably done by a processor.
- Fig. 1 represents the global transmitter structure for the device of the present invention.
- Fig. 2 represents a QPN channel.
- Fig. 3 represents the use of a RAM block to generate PN-codes.
- Fig. 4 to 7 represent some possible RAM configurations for the device of the present invention.
- Fig. 8 illustrates the phase unbalance compensation.
- Fig. 9 represents a receiver architecture for the device of the present invention.
- Fig. 10, 11, 12 and 13 represent respectively a level control, a noise estimator, a general overview of a demodulator and a tracking unit usable in a device according to the present invention.
- Fig. 14 represents a possible configuration of a demodulator for UMTS mode, using only 1 tracking unit.
- Fig. 15 and 16 represent respectively a Rake
- Fig. 17 represents slotwise coherent pilot symbol accumulation according to the present invention.
- Fig. 18 represents finger energy calculation.
- Fig. 19 represents a slot weighing filter for the device according to the present invention.
- Fig. 20 shows an overview of the Rake finger process in the case of Channel Mode 0.
- Fig. 21 and 22 draw an overview of the Rake finger process in the case of Channel Mode 1.
- Fig. 23 illustrates the noise estimator.
- Fig. 24 represents the noise estimator's functional structure.
- Fig. 25 illustrates the SCH RX hardware.
- Fig. 26 represents the slot synchronization.
- Fig. 27 represents the PRACH TX hardware. Detailed description of the invention Abbre viati on s
- the transmitter contains a plurality of QPN channels 3 (Fig. 2) . These channels are e.g. combined in two sets of four QPN channels (set A and set B) and set C with only one QPN channel, as can be seen Fig. 1. [0061] Each set has a separate block for generating the PN-code 5 and separate synchronisation hardware 7 which defines the start of symbol transmission.
- the output of this part goes to the QPN channels of a set and defines a common symbol start moment for all QPN channels a set. This signal is generated as a selection of 1 out of a plurality of incoming signals with a programmable offset.
- the incoming sync channels can e.g. be generated by : another chip, TX timers, receiver pulse, acquisition hardware output, ...
- a counter at chip rate can be used. This gives an offset resolution of 1 'primary' chip.
- the range of the offset is [0:65535] . This is sufficient to give an offset of 1 frame for UMTS (40960 chips) .
- Each QPN channel 3 has the functional structure represented Fig. 2. Its functional elements are described below:
- symbl and actl are signals at symbolrate fslxx
- symbQ and actQ are signals at symbolrate fsQxx
- fslxx can differ from fsQxx.
- the spreading factor is set by the sfl 15 and sfQ 16 inputs.
- the spreaders can be (re) started via the sync signal 17.
- Symbol clock signals 19 are generated as a symbol reference for other hardware that requires symbol synchronous actions, like the gain controls 21.
- Each complex spreader 11 is followed by a separate gain control 21.
- Each output branch of a spreader is again separately gain controlled.
- a code generator 5 is foreseen per set.
- the sgfb inputs define the feedback position in the shift register, the init inputs are used to initialise the shift registers k at reset or restart.
- the poly inputs are used to program the polynomials to generate the Gold sequences.
- the rest signals are used to make generate a small section of the complete Gold code and then jump to the back to the mit value. If the register m the gold code generator reaches the rest state, the register is the following clock-cycle re-mitialised.
- Each set has a block 23 which can generate
- the block 23 contains a RAM of e.g. 8*1024 bits.
- An address generator selects one row 35 of this RAM with the x address, then these 8 bit are routed to the spreaders via a switch controlled by address y.
- the address generator 31 has a start 25, stop
- the address generator can be configured in different ways with the configure input 33. [0078] It is possible to stop the generators when the activity bit of a symbol is 0.
- BPSK streams 37, stream 0 and 5 have SF 2048, stream 1 has SF 512, stream 2 has SF 256, streams 3 and 4 have SF 1024; x counts from 1023 to 0, y changes between 2 values every 1024 chips.
- BPSK streams 37, stream 0 and 1 have SF 256, stream 0 uses continuously the same code, while stream 1 uses a sequence of 16 different codes.
- This scheme is usable for SCH transmission ' if the addresscounter is stopped when the activity bit is 0. x counts from 1023 to 0, y changes between 4 values every 1024 chips.
- -Fig 7 4 BPSK streams 37, stream 0 has SF 1000, stream 1 has SF 2000, stream 2 has SF 400, stream 3 has SF 600; x counts from 999 to 0 , y changes between 3 values every 1024 chips.
- variable spreading factor transmission e.g. OVSF codes UMTS
- the RAM is filled with replica's until the common multiple length is reached. In this way the symbols one set are multiple-symbol synchronous.
- the two combiners 38 after set A and set B at fcp rate output the sum of the 4 incoming complex numbers.
- Each scrambling code generator has its own synchronisation hardware block to generate the sync signal. (see Fig. 1) .
- the scrambling code generator contains 2 Gold code generators with 42 bit register, 2 RAMs of 256 bit, an interface for external input of codes and some extra hardware for UMTS to modify the Gold codes.
- the Gold code generators are functionally the same as the Gold code generators in the PN code generators .
- This is a classical Gold code generator with 42 bit registers which can generate any Gold code with any length up to (2 ⁇ 42)-1. It can also be used to generate any segment out of a Gold code smaller than (2 42)-1.
- the sgfb inputs define the feedback position the shift register, the mit inputs are used to initialise the shift registers at reset or restart.
- the poly inputs are used to program the polynomials to generate the Gold sequences.
- the rest signals are used to make generate a small section of the complete Gold code and then ump to the back to the mit value. If the register the Gold code generator reaches the rest state, the register is m the following clock-cycle re-mitialised .
- cl and cQ are any Gold code with any length of maximum (2 ⁇ 42) -1.
- cl and cQ come directly from a RAM of 256 bit . It must be possible to use only the first k bits m the RAM, with k smaller than 257.
- the preferred decimation factor is 2, however other decimation factors should be possible in future evolutions of UMTS if proven desirable .
- cl and c2 are constructed as the position wise modulo 2 sum of 40960 chip segment of two binary m- sequences generated by means of two generator polynomials of degree 41.
- the code c2 used in generating the quadrature component of the complex spreading code is a 1024 -chip shifted version of the code cl used in generating the in phase component.
- the scrambling is in fact an overlay spreading without changing the chiprate, the change in chip rate is done with the Hold 1-256 block.
- This block is used to do a chip phase shift with a resolution smaller than 1 chip. For every sample , one output sample is generated, input and output clock is the equidistant clock.
- the fixed upsamplmg with a factor of e.g. 4 (zero insertion) and a symmetrical programmable filter are realised as a complex oversamplmg polyphase filter.
- the output sampling rate f4c 4 * fc .
- Offset modula tion [0101] By setting offset to 1, the Q branch will be delayed with 0.5 chip.
- the cos and s values are frequency and phase controlable.
- the specifications below are not required for cellular, but can be used for satellite applications with demanding phase noise requirements.
- the sine and cosine values are generated with the 16 MSB of a s ⁇ 32,0> phase value.
- the 14 LSB of this 16 bit number go to 2 lookup tables which contain the values for sm and cos m [0,2*p ⁇ [ with a ga of 2047/2048.
- the lookup wordlength for s and cos quadrant 1 is u ⁇ ll,ll>.
- the 2 MSB of the s ⁇ 32,0> bit phase register are used to recover the quadrant, sm and cos are s ⁇ 12,ll> numbers.
- the output of the NCO is the complex signal (cos + j . sm) .
- the s ⁇ 32,0> bit phase register can be directly controlled via the TXPHASE input (s ⁇ 32,0>) or by integrating with wrap around the TXINC (s ⁇ 32,0>) value.
- TXINC should be set to -1073741824.
- the s ⁇ 32,0> phase register should be a part of the chip boot chain.
- Level Control 2 [0112] The purpose of this block is to condition the signal coming from the upconverter prior to the DA conversion. Phase unbalance compensa tion (Fig . 8)
- Digital phase unbalance compensation is used to remove the I,Q phase difference from 90 degrees prior to A/D conversion.
- phase unbalance compensation is done :
- tan( ⁇ ) is stored in the TGCR_AC variable.
- a range for 2 ⁇ is larger than 13 degrees.
- the resolution of 2 ⁇ is smaller than 1 degree .
- TGCR_AC The transfer of TGCR_AC is synchronous with the I0A symbol clock.
- This block performs a complex downconversion, with the NCO generated complex carrier, on the incoming complex signal .
- the output signal is expected to be a near baseband signal.
- Input and output are at fm rate.
- the complex receive stream coming from the downconverter is filtered by a programmable symmetrical FIR filter and downsampled with a factor RXD .
- RXD can be 1 or
- Inputs are at fin rate, outputs at f2ct rate.
- the noise estimator 63 (Fig. 11) provides a filtered complex noise correlation value which can be read by the microcontroller subsystem. This value could be used for setting thresholds in the acquisition hardware.
- the noise correlator 65 is just the accumulation of NC_lenght absolute values 64 of the complex input . In this way, an RSSI estimation is obtained.
- the filter is a simple hardware low-pass filter.
- Demodulator 67 In most modes the plurality of demodulators are used to support base station diversity for soft handover, however they can also be used for other purposes. In the following paragraphs the demodulator structure will be explained in more detail . [0125]
- Figure 12 gives a general overview of a demodulator 67. It consists of a number of tracking units 69 with their peripheral hardware like code generators and feedback signal generators like PED with PLL 70, TED with DLL 97, AED 91 with AGC 93. This will be discussed in more detail further.
- Each demodulator also has a Rake block 71 performing a combination of channel corrected multipath components. This block will also be discussed in more detail later. [0127] Not all the hardware in Fig. 12 is used at the same time. This depends on the configuration. It is possible to turn off idle blocks to save power. Tracking unit 69
- Fig. 13 has the same input: the complex signal coming from the common level control. It is possible to track one signal source with one tracking unit .
- a signal source can be a physical transmitter or it can be a multi -path component coming from one transmitter. So in one demodulator we can e.g. track 3 satellites or track 3 multi-path components (as an alternative to the use of the above mentioned Rake) from a terrestrial base-station.
- the functional blocks within a tracking unit are described below.
- Tracking uni t downconverter 45 and NCO 47 [0129] This block is used as actuator for the carrier phase/frequency tracking. A final downconversion is performed.
- Tracking uni t interpolator 74 wi th chip frequency control [0130] This block is used as actuator for the chip phase/frequency tracking. This is done by a pseudo-chip rate change. The outcoming chip rate is controlled via the
- the DINT input is used to change the INTMU continuously by adding DINT to the previous value of INTMU every cycle. This results in a change in chiprate by
- the input samples are equidistant at f2c rate.
- the output samples of the interpolator are not equidistant at f2cr rate.
- f2cr is between f2c/2 and 2*f2c. So all the hardware after the interpolator must be designed to work at 2*f2c although its nominal rate will be f2c.
- MEL ga te 75 [0135] This MEL gate 75 is only used in no-cellular modes; otherwise it's bypassed through the appropriate multiplexer settings.
- the incoming stream at f2cr is split in three streams at f2cr rate.
- E in.z A -2
- M in.z ⁇ -1
- L in
- each stream is spaced 0.5 chip.
- the M signal of Tracking unit 0 is also used as input for the Rake block, if it is activated (see further) .
- a phase controllable downsampling with a factor e.g. 2 is performed here by skipping 1 incoming sample of 2 incoming samples.
- D2 defines which phase to skip.
- the 3 multiplexers 81 allow to choose between which signal goes to the final correlators 83. This can be the downsampled signal coming from the MEL gate or it can be the Rake output at chip rate.
- Each tracking unit contains a number of QPN despreaders. Each despreader and each branch of the despreader can have a different spreading factor.
- This block is used as actuator for the signal amplitude tracking.
- Each Vamp 87 can have a different ga .
- the output of the Vamps are the soft symbols
- MD, MP, EP and LP which stands for Middle Data, Middle
- This block generates the complex PN-codes for the despreaders 85. This is a similar block as in the transmitter. So possibility to use a RAM, Gold code generator or an external input .
- Tracking unit 0 is equipped with e.g. 4 separate generators, unit 1 and 2 have only 1 generator. So the 4 despreaders in unit 1 and 2 use the same despreading code .
- the AED 91 is the error detector for the signal amplitude tracking.
- the AGC 93 does a filtering on this signal and outputs the signal going to the Variable amplifiers .
- Tracking unit 0 has 4 separate AED and AGC for each despreader in the tracking unit, while tracking unit 1 and 2 only have a common AED and AGC working on the
- the NCO of each tracking unit can be set by an external block like ARM software or can be controlled by the PLL.
- the PLL works on the MP signal. When the Rake is used, the PLL is turned off.
- the TEDO or TED1 are used as error detectors for the chip timing tracking.
- TED1 is used when the CCP is used as a signal source for the despreaders of the unit, while TEDO is used when classic Early-Late correlator tracking is done.
- the output of the TED 91 goes to the DLLs, chip frequency controling the interpolator.
- Rake receiver 101 performs a weighted coherent combination of a plurality of taps selected on a delay line of the chip stream, resulting into one new chip stream. To combine them weighted coherently a channel estimation (amplitude, phase) of each of the delayed chip streams is made. This block is discussed in detail further.
- the Rake-based demodulator configuration reuses almost everything from the tracking unit except for the PLL and PED .
- a large extra block that is not used when using Early-Late correlator tracking is the Rake 71. So roughly said the Rake-based demodulator consists of the Rake that generates a new chip stream from the incoming chip stream and the classic descrambler 83, despreader 85, ... hardware.
- This part performs the coherent combination of a plurality chip streams 107 into one new chip stream 109.
- the pilot symbols can have a SF from 4 to 256 and may be arbitrarily distributed over the slot.
- Fingers 0 to 4 contribute to the Late multipaths, fingers 5 to 7 to the Early multipaths. Note that there is no real 'Middle' finger, this means that in the case of a single path, the correlation energy will be split over finger 4 and 5 and one will never correlate at the 'top' of the correlation shape.
- the Rake In one of the possible ways of using the Rake, it will be initialised so that the strongest peak will be between finger 4 and 5. With the phase controllable decimation (D2) the chip phase can be set with a resolution of 1/2 chip.
- Each finger has as inputs: -Pcb : the codebit for despreading the pilot chipstream.
- the spreading code is stored in a RAM of 256 bits. This is a real signal, no QPN pilot is possible.
- -Psb the complex descrambling bits coming from the descrambling code generator.
- -Psy the data modulation on the pilot symbols.
- -Pac activity bit for pilot symbols. This eliminates the need for having the pilot portion as a continuous portion at the beginning of the slot. Again a RAM of 640x1 could be used. -Psf : The pilot SF .
- channel mode parameter selects the algorithm to use to make the channel estimations, (slow fading : 0, fast fading 1) .
- Each finger has a complex CCCP [x] output at chip rate. This is the delayed chips multiplied with the complex conjugate of the channel estimation of finger x. [0169] Each finger also has a FNx output at slot rate which is the energy of the coherent accumulation of all pilot chips/symbols in a slot of finger x. [0170] The sum of all FNx is calculated and goes to the pilot AGC. In this way CCCP will not be dependent on the pilot energy. [0171] As one has fixed finger spacing we only need a global DLL.
- ENL and ENE go to the DLL which feedbacks to the interpolator at the input of the demodulator using the Rake filter.
- Descrambler 117 [0175] The incoming chips are descrambled with Psb. This code and its phase is common for all fingers. The phase has to be set during an acquisition process initialising the Rake. Has the same functionality as the other descramblers .
- Complex pilot despreader 119
- the complex signal coming from the descrambler at chip rate is despread with the pilot PNcode (Pcb) , only 1 despreader, so the pilot must be a QPSK or BPSK signal .
- Pcb pilot PNcode
- Variable Amplifier 121 Variable Amplifier 121
- VAMP Variable Amplifier
- the initial gain must be set to a different value, eg to 1.0 for SF 256, to 64.0 for SF 4.
- Pilot filter 123 Slotwise coherent pilot symbol accumulation 124
- a coherent pilot symbol accumulation is done on a slot by slot basis.
- the Pac input defines if the symbol coming from the VAMP is a pilot symbol. See Fig. 17.
- Dva @fsymbB
- the pilot modulation must be removed first. This modulation is known a priori and must be present at the Psy input.
- Psy can take 4 values : +1, -j, +j , -1.
- Spj are the complex accumulation of these demodulated pilot symbols from the current slot, divided by the number of pilots (or multiplied by 1/number of pilot symbols) :
- Sp values are generated at slot rate fslot .
- the value is available at the end of the slot .
- This module is slot-synchronous .
- This block performs a filtering or interpolation on the Sp values.
- the output of this block is the channel estimation ces at chiprate.
- the multiplication after the filter is to have a FIR filter 129 with unity gain. To avoid a transient in the amplitude on the signal coming from the filter, 4 different values are stored for this gain.
- the first output of the filter gets gain CeFIRmult [0]
- the third CeFIRmult [2] and CeFIRmult [3] is used on sample number 4 leaving the filter and in steady state mode.
- All filter taps should be initialised to 0 at the start of the process.
- Channel mode 1 Fast fading 133 and 135 [0205] In this mode ces are interpolated values between the current and the previous Sp values entering the channel estimator. So ces changes at chip rate. See Fig.
- the incoming Sp values are positioned in the middle of the pilot portion to calculate the other complex values.
- the pipo (pilot position) input is used for this.
- pipo would be 768 or 769 (3/5*2560/2) .
- See Fig. 22 for an overview of the Rake fmger process 135 m case of channel mode 1.
- the different pilot symbols are demodulated and coherently accumulated giving the values SpO to Sp5.
- the channel estimations ces (I) for the chips I of slot 2 are calculated during slot 4 with the aid of Sp2 and Sp3.
- So the Present and Future slot is used to make the channel estimates.
- This block has as input the delayed chips Dl coming from the FIFO and the channel estimations per chip ces . [0212] The function of this block is to correct for the channel phase of the fmger and give a weight to the fmger. The outputs from the different fingers can then be combined (coherently) m one signal.
- Dro Dl*ces(*) with ces(*) the complex conjugates of ces.
- Each fmger output can be forced to zero with the zf signal .
- the purpose of this is to set a fmger to 0 when no (or very little) signal is present m that fmger to avoid the accumulation of a lot of noise.
- the zf signal is obtained by comparing the slotwise FN and a programmable threshold, zf is 1 if FN ⁇ - threshold.
- This block is to get an estimate of the noise power before the despreaders.
- the block is present on despreaders 0 of tracking unit R input, so at the output of the descrambler.
- the N estimator calculates :
- filter_out (1- ⁇ ) *filter_in + ⁇ *filter_out*z _1
- RR_NC_ALPHA is a ⁇ 6,6> number.
- SCH RX hardware (Fig. 25) [0220] 3 modes are possible : initial cell search, idle mode cell search and active mode cell search.
- Step 1 Slot synchronisation (fig. 26) [0221] In this step, the MS acquires slot synchronisation by doing a fast acquisition on Cp which is common to all Bss.
- the samples coming from the SRRC filter and at 2 fchip are sent through a matched filter 200 with the Cp code.
- the first 5120 moduli are written into the RAM. To get better reliability a non-coherent dwell is performed. This is done by adding the next 5120 points to the previous 5120 points already present in the RAM. This is repeated for the required number of dwells .
- the maximum detection module 201 finds the maximum in the last 5120 points written to the RAM, and returns the address of this value. This address identifies the slot edge.
- the correlators can be switched off during this stage.
- Step 2 Frame synchronisation and code-group identification
- Each BS belongs to 1 of 32 possible codegroups .
- Each codegroup uses a different sequence of 16 Cs codes on SCH2. From stepl the position of the secondary codes is known.
- the decision variables are obtained by non- coherently summing the correlator outputs corresponding to each 16 length sequence out of the 32 possible sequences and its 16 cyclic shifts.
- One decision variable is formed by adding 16 correlator outputs non-coherently (modulus) . The calculation of these 512 values is distributed over the 16 idle intervals (9/10) after each correlation.
- one of the 6 correlator outputs can be selected and the modulus is calculated.
- each of the codegroup table entries is selected, this selects 1 of the 6 correlator outputs and the modulus of these are written to one of the 512 used RAM positions during step2.
- slot n°2 each value in the RAM is added with 1 of the 6 correlator modulus outputs of slot2.
- Which correlator needs to be selected for each RAM address is selected by the x and y combination.
- This is repeated for the 16 slots, during slot n°16 the resulting values are the 512 decision variables which are sent through the maximum detector.
- the address coming from the maximum detection block identifies the codegroup and the phase shift.
- the frame edge can be determined from the shift. At least 16 slots have to be added non-coherently .
- One of the general TX channels is used to make the PRACH waveform. In that case the following things are required for the general TX channels :
- the MS acquires synchronisation to a BS (SCH channel) and reads different parameters from the BCCH channel (preamble spreading codes, available signatures, available access slots, ...) .
- the software 210 decides which parameters to use, these parameters are passed to the hardware via the interface block 211.
- the start of the access slot offset must be synchronous with the BCCH frame edge 214.
- the upconverter must be set to a Doppler precompensated IF in order to avoid big integration losses in the BS receiver.
- the data coming from the interface block is spread with a max SF of 256.
- the activity bit is set to 0.
- 256bit RAM is needed to store the PN codes .
- Gain stage The spread data is sent through a gain block 213. A different gain must be possible for I and Q branch.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mobile Radio Communication Systems (AREA)
- Dc Digital Transmission (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
Abstract
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU61415/00A AU6141500A (en) | 1999-07-23 | 2000-07-19 | Method and apparatus for high-speed software reconfigurable code division multiple access communication |
US10/048,142 US7327779B1 (en) | 1999-07-23 | 2000-07-19 | Method and apparatus for high-speed software reconfigurable code division multiple access communication |
EP00947689A EP1197008A2 (en) | 1999-07-23 | 2000-07-19 | Method and apparatus for high-speed software reconfigurable code division multiple access communication |
TW090101587A TW538604B (en) | 1999-07-23 | 2001-01-20 | Method and apparatus for high-speed software reconfigurable code division multiple access communication |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US14542699P | 1999-07-23 | 1999-07-23 | |
US60/145,426 | 1999-07-23 |
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WO2001008314A2 true WO2001008314A2 (en) | 2001-02-01 |
WO2001008314A3 WO2001008314A3 (en) | 2001-05-31 |
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PCT/BE2000/000086 WO2001008314A2 (en) | 1999-07-23 | 2000-07-19 | Method and apparatus for high-speed software reconfigurable code division multiple access communication |
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Country | Link |
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EP (1) | EP1197008A2 (en) |
AU (1) | AU6141500A (en) |
TW (1) | TW538604B (en) |
WO (1) | WO2001008314A2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0767544A2 (en) * | 1995-10-04 | 1997-04-09 | Interuniversitair Micro-Elektronica Centrum Vzw | Programmable modem using spread spectrum communication |
US5742637A (en) * | 1996-08-20 | 1998-04-21 | Golden Bridge Technology, Inc. | Fast phase estimation in digital communication systems |
EP0928084A2 (en) * | 1998-01-02 | 1999-07-07 | Mitsubishi Denki Kabushiki Kaisha | Universal modem for digital video, audio and data communications |
-
2000
- 2000-07-19 WO PCT/BE2000/000086 patent/WO2001008314A2/en active Application Filing
- 2000-07-19 EP EP00947689A patent/EP1197008A2/en not_active Withdrawn
- 2000-07-19 AU AU61415/00A patent/AU6141500A/en not_active Abandoned
-
2001
- 2001-01-20 TW TW090101587A patent/TW538604B/en active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0767544A2 (en) * | 1995-10-04 | 1997-04-09 | Interuniversitair Micro-Elektronica Centrum Vzw | Programmable modem using spread spectrum communication |
US5742637A (en) * | 1996-08-20 | 1998-04-21 | Golden Bridge Technology, Inc. | Fast phase estimation in digital communication systems |
EP0928084A2 (en) * | 1998-01-02 | 1999-07-07 | Mitsubishi Denki Kabushiki Kaisha | Universal modem for digital video, audio and data communications |
Non-Patent Citations (1)
Title |
---|
"Sirius Announces World's First Software Configurable W-CDMA Core for Third-Generation Wireless handsets and Base Stations" SIRIUS COMMUNICATIONS PRESS RELEASES, [Online] 14 June 1999 (1999-06-14), pages 1-2, XP002151828 BRUSSELS (BE) Retrieved from the Internet: <URL:HTTP://WWW.SIRIUSCOMM.COM/PRESSREALEA SES/PRESSCDMAX.HTM> [retrieved on 2000-10-25] * |
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Publication number | Publication date |
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EP1197008A2 (en) | 2002-04-17 |
TW538604B (en) | 2003-06-21 |
WO2001008314A3 (en) | 2001-05-31 |
AU6141500A (en) | 2001-02-13 |
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