WO2001001266A8 - Digital delay locked loop with output duty cycle matching input duty cycle - Google Patents
Digital delay locked loop with output duty cycle matching input duty cycleInfo
- Publication number
- WO2001001266A8 WO2001001266A8 PCT/US2000/012690 US0012690W WO0101266A8 WO 2001001266 A8 WO2001001266 A8 WO 2001001266A8 US 0012690 W US0012690 W US 0012690W WO 0101266 A8 WO0101266 A8 WO 0101266A8
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- duty cycle
- clock signal
- rising edge
- system clock
- falling edge
- Prior art date
Links
- 230000000630 rising effect Effects 0.000 abstract 6
- 230000005540 biological transmission Effects 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Information Transfer Systems (AREA)
- Pulse Circuits (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00932225A EP1105808A1 (en) | 1999-06-29 | 2000-05-10 | Digital delay locked loop with output duty cycle matching input duty cycle |
JP2001507208A JP2003503797A (en) | 1999-06-29 | 2000-05-10 | Digital delay-locked loop where output duty cycle matches input duty cycle |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US34285399A | 1999-06-29 | 1999-06-29 | |
US09/342,853 | 1999-06-29 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2001001266A1 WO2001001266A1 (en) | 2001-01-04 |
WO2001001266A9 WO2001001266A9 (en) | 2001-07-05 |
WO2001001266A8 true WO2001001266A8 (en) | 2001-08-09 |
Family
ID=23343555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/012690 WO2001001266A1 (en) | 1999-06-29 | 2000-05-10 | Digital delay locked loop with output duty cycle matching input duty cycle |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1105808A1 (en) |
JP (1) | JP2003503797A (en) |
WO (1) | WO2001001266A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100477808B1 (en) | 2002-05-21 | 2005-03-21 | 주식회사 하이닉스반도체 | Digital dll apparatus for correcting duty cycle and method thereof |
KR100685604B1 (en) | 2005-06-22 | 2007-02-22 | 주식회사 하이닉스반도체 | Delay locked loop for generating a internal clock signal with decreased jitter components |
DE102006051284B4 (en) * | 2005-10-26 | 2011-06-16 | Samsung Electronics Co., Ltd., Suwon | Duty cycle correction circuit, integrated circuit, phase locked loop circuit, delay locked loop circuit, memory device and method for generating a clock signal |
KR102540232B1 (en) * | 2017-12-21 | 2023-06-02 | 삼성전자주식회사 | A digital measurment circuit and a memory system using the same |
CN112698683B (en) * | 2020-12-28 | 2024-07-19 | 深圳市合信自动化技术有限公司 | Method, device and PLC (programmable logic controller) for solving transmission delay data errors by configurable bus |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2830735B2 (en) * | 1994-04-19 | 1998-12-02 | 日本電気株式会社 | Phase-locked timing generator |
US5815016A (en) * | 1994-09-02 | 1998-09-29 | Xilinx, Inc. | Phase-locked delay loop for clock correction |
US5712884A (en) * | 1995-03-31 | 1998-01-27 | Samsung Electronics Co., Ltd. | Data receiving method and circuit of digital communication system |
US5828257A (en) * | 1995-09-08 | 1998-10-27 | International Business Machines Corporation | Precision time interval division with digital phase delay lines |
-
2000
- 2000-05-10 WO PCT/US2000/012690 patent/WO2001001266A1/en not_active Application Discontinuation
- 2000-05-10 JP JP2001507208A patent/JP2003503797A/en active Pending
- 2000-05-10 EP EP00932225A patent/EP1105808A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP1105808A1 (en) | 2001-06-13 |
WO2001001266A9 (en) | 2001-07-05 |
WO2001001266A1 (en) | 2001-01-04 |
JP2003503797A (en) | 2003-01-28 |
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