WO2001000508A1 - Materiau plaque pour ensemble semi-conducteur et ensemble semi-conducteur comportant ledit materiau plaque - Google Patents

Materiau plaque pour ensemble semi-conducteur et ensemble semi-conducteur comportant ledit materiau plaque Download PDF

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Publication number
WO2001000508A1
WO2001000508A1 PCT/JP2000/004156 JP0004156W WO0100508A1 WO 2001000508 A1 WO2001000508 A1 WO 2001000508A1 JP 0004156 W JP0004156 W JP 0004156W WO 0100508 A1 WO0100508 A1 WO 0100508A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
frame
semiconductor package
base substrate
semiconductor
Prior art date
Application number
PCT/JP2000/004156
Other languages
English (en)
Japanese (ja)
Inventor
Kinji Saijo
Kazuo Yoshida
Hiroaki Okamoto
Sinji Ohsawa
Original Assignee
Toyo Kohan Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Kohan Co., Ltd. filed Critical Toyo Kohan Co., Ltd.
Priority to JP2001506930A priority Critical patent/JP4623622B2/ja
Priority to AU54300/00A priority patent/AU5430000A/en
Publication of WO2001000508A1 publication Critical patent/WO2001000508A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits

Definitions

  • the present invention relates to a cladding material for a semiconductor package and a semiconductor package using the same.
  • Japanese Patent Application Laid-Open No. 5-219425 discloses a base substrate having ⁇ 11 1 ⁇ 0 / ⁇ .
  • One using the clad material of No. 1 has been proposed.
  • the Cu / Mo / Cu clad material is compatible with the coefficient of thermal expansion of the semiconductor chip and has good thermal conductivity, so that it can be used as a heat sink of a semiconductor package.
  • f plate and the window frame formed in a frame shape surrounding the semiconductor chip are manufactured in a separate manufacturing process and are bonded using glass or adhesive, so their bonding strength is weak.
  • Cu ZMo Cu clad material which has excellent heat dissipation properties, there is a problem that it may be peeled off from the bonded part due to repeated heating and cooling.
  • An object of the present invention is to solve the above problems, and to provide a clad plate for a semiconductor package which can be manufactured at low cost and has good characteristics, and a semiconductor package using the same. And Disclosure of the invention
  • the cladding material for a semiconductor package according to the present invention comprises a base substrate for bonding a semiconductor chip, and a wind frame formed in a frame shape so as to surround the semiconductor chip.
  • a clad plate comprising a Cii layer characterized in that a base substrate and a frame plate are integrated.
  • the next feature of the clad material of the present invention is that a clad material for manufacturing a semiconductor package composed of a base substrate for bonding a semiconductor chip and a window frame formed in a frame shape so as to surround the semiconductor chip.
  • the base substrate is a Cu foil material
  • the frame plate forming the wind frame is a clad plate composed of a Ni layer and a ZCu layer, and the base substrate and the frame plate are integrated. 10
  • the semiconductor package of the present invention is a semiconductor package comprising a base substrate for joining a semiconductor chip and a window frame formed in a frame shape so as to surround the semiconductor chip, wherein the base substrate has a Cu layer ZMo.
  • the wind frame is composed of a Ni layer and a Cu layer.
  • the next feature of the semiconductor package of the present invention is that in a semiconductor package constituted by a base substrate for bonding a semiconductor chip and a wind frame formed in a frame shape so as to surround the semiconductor chip, the base substrate is made of Cu foil. And the wind frame is made of a Ni layer / Cu layer.
  • the next feature of the semiconductor package of the present invention is a clad material for manufacturing a semiconductor package composed of a base substrate for bonding a semiconductor chip and a window frame formed in a frame shape so as to surround the semiconductor chip.
  • the heat radiating plate constituting the base substrate is a clad material composed of a Cu layer and a ZMo layer / Cu layer
  • the frame plate constituting the wind frame is a clad material composed of a Ni layer and a ZCu layer.
  • the next feature of the semiconductor package of the present invention is a clad material for manufacturing a semiconductor package constituted by a base substrate for bonding a semiconductor chip and a frame-shaped wind frame surrounding the semiconductor chip.
  • a radiator plate forming the base substrate is a Cu foil material;
  • a frame plate forming the wind frame is a clad plate formed of a Ni layer and a ZCu layer; and the radiator plate and the frame This is the result of etching the Cu surface of the frame plate of the cladding material for semiconductor package, which has become a body, to form a recess for inserting the semiconductor.
  • FIG. 1 is a cross-sectional view of a cladding material for a semiconductor package according to one embodiment of the present invention.
  • FIG. 2 is a sectional view of a cladding material for a semiconductor package according to another embodiment of the present invention.
  • FIG. 3 is a process explanatory view of a
  • FIG. 4 is a process explanatory view of a method for manufacturing a semiconductor package according to one embodiment of the present invention.
  • FIG. 5 is a process explanatory view of a method for manufacturing a semiconductor package according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional front view of the clad plate manufacturing apparatus.
  • an etching stopper made of a Ni layer is provided below a base substrate 33 (thickness is preferably 30 to 500 / im) having three layers of a Cu layer, a ZMo layer, and a Cu layer.
  • a layer 12 (0.5-3 is preferred) is formed.
  • This one The thickness ratio of each layer of the substrate may be determined so as to be close to the coefficient of thermal expansion of the material used for the semiconductor chip. For example, if S i is used in the semiconductor chip, C u: Mo: thickness ratio of Cu is 1: 1: 1, then the thermal expansion coefficient of 9. 9 (XI 0 one B Z ° C :, 3 0-1 0 0 :) next, S i of a thermal expansion coefficient of 9.
  • a Cu foil material 24 is formed below the Ni layer 12.
  • CI The thickness of the foil material is preferably 30 to 500 zm.
  • a nickel material serving as an etching stop layer 12 is formed on one side of a clad material 33 (preferably having a thickness of 30 to 500 m) composed of a Cu layer ZMo layer / Cu layer serving as a base substrate of a semiconductor package.
  • a clad material consisting of a Cu layer, a ZMo layer and a ZCu layer plated with nickel by plating 21 is produced (see Fig. 1).
  • a clad material 19 composed of a Cu layer / Mo layer and a ZCu layer with nickel plating is wound around a rewind reel 23 in the clad plate manufacturing apparatus shown in FIG. Further, the copper foil material 24 to be the wind frame 17 is wound around the rewind reel 25. From the rewind reels 23 and 25, the clad material 19 made of nickel-coated Cu layer ZMo layer and ZCu layer 0 and the copper foil material 24 are simultaneously rewound, and a part of them is etched into the etching chamber 26. It is wound around the protruding electrode rolls 27, 28, and is activated by a sputter etching process in the etching chamber 26.
  • the activation processing as the applicant has disclosed in JP-1 one 2 24 1 84 JP above, 1 1 X 1 0 ' ⁇ 1 X 1 0- 2 P a of extremely low pressure inert
  • the clad material 22 consisting of a Cu layer / Mo layer and a ZCu layer with a nickel-bonded surface with a ⁇ joint surface and a copper foil material 24 were each used as one electrode A, which was grounded, and was insulated and supported.
  • the clad material 31 is cold-welded at a low reduction rate of 0.1 to 3% by a rolling unit 30 provided in a vacuum chamber 29, and the clad material 31 is wound around a winding roll 32. Since cold welding is performed at a low reduction rate of 0.1 to 3%, the flatness of the bonding interface can be maintained by keeping the stress at the bonding interface low. Also, since heat treatment for recovering workability is not required, an alloy layer is not formed at the joint interface, so that the selective etching property is excellent. Thus, a cladding plate 1034 for a semiconductor package having a five-layer structure is manufactured as shown in FIG.
  • a Cu foil composed of the Cu layer 22 alone may be used as shown in FIG.
  • a clad material composed of a Cu layer, a ZMo layer, and a ZCu layer As the base substrate, an example was described in which a clad material composed of a Cu layer, a ZMo layer, and a ZCu layer, which had been previously plated with nickel, was pressed.
  • the above equipment may be used in which a nickel foil is pressed against a clad material comprising a Cu layer, a ZMo layer, and a Cu layer at a low reduction rate of 0.1 to 3%.
  • a copper foil material pre-plated with nickel may be pressed against a clad material comprising a Cu layer / Mo layer and a ZCu layer.
  • a clad material made of copper foil and nickel foil using the above-mentioned yo facility and a clad material composed of this clad material and a clad material composed of a Cu layer, a Mo layer, and a ZCu layer can also be applied.
  • the nickel layer serving as the etching stopper layer may be provided by nickel plating on a Cu foil or a copper foil material serving as a window frame. Furthermore, it is also applicable that the nickel foil was pressed against a copper foil material is a Cu foil or a window frame> beam under low pressure ratio of 0.1 to 3%.
  • Copper / molybdenum Z copper z A multilayer clad plate made of gel Z copper or copper Z nickel Z copper can be manufactured.
  • a multilayer clad plate can be manufactured with a single pressure welding.
  • a semiconductor package is manufactured through the following steps described with reference to FIGS. First, as shown in FIG. 3, after forming a photoresist j ir film 35 on the surface of the Dohakuzai 2 4, exposed and developed.
  • the copper foil material 24 is selectively etched, and the copper foil material 24 is removed while leaving the window frame 17.
  • an etching solution it is desirable to use a sulfuric acid + hydrogen peroxide solution or an ammonium persulfate solution.
  • the nickel layer exposed in the concave portion of the semiconductor package and the ⁇ 0 semiconductor chip 1 are bonded with an adhesive.
  • the printed board 10 is bonded to the copper foil material 24, and the printed board 10 and the semiconductor chip 1 are wired by wiring 3.
  • the semiconductor chip 1 is covered with the resin mold 39, and the wiring in the printed board is wired with the solder bump 2.
  • the clad plate for a semiconductor package of the present invention has a Cu layer A ZMo layer / / Cu layer / N i layer ZC u layer or clad material consisting of C u layer ZN i layer ZCu layer, since the pressure in the low pressure ratio of 0.1 to 3%, of the bonding interface Stress can be kept low. As a result, the flatness of the bonding interface can be maintained, and no heat treatment for recovering the workability is required, so that no intermetallics are generated at the interface. Therefore, a cladding plate for a semiconductor package having excellent selective etching properties is provided. be able to. Since the semiconductor package of the present invention has one etching stopper made of a nickel layer, the etched surface becomes flat after etching the Cu foil, and the bonding property of the semiconductor chip is improved.
  • the semiconductor package of the present invention is characterized in that the clad material composed of the Cu layer, the ZMo layer, and the ZCu layer used for the base substrate has an appropriate thickness ratio, so that the material used for the semiconductor chip and the heat The coefficient of expansion is close and the thermal expansion matching is excellent. Further, the clad material or Cu composed of the Cu layer, the ZMo layer, and the ZCu layer used in the semiconductor package of the present invention has excellent heat conductivity, and thus has excellent heat dissipation characteristics.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Metallurgy (AREA)
  • Manufacturing & Machinery (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Laminated Bodies (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Cette invention concerne un plaquage pour ensemble semi-conducteur et un ensemble semi-conducteur qui peuvent être produits à bas prix et qui possèdent de bonnes caractéristiques. Le matériau de plaquage (33) se caractérise en ce qu'il comprend une couche Cu/une couche Mo/une couche Cu avec interposition d'une couche de nickel (21) faisant office de couche d'arrêt (12) pendant l'attaque. Par ailleurs, l'ensemble semi-conducteur est réalisé de telle sorte qu'une couche Cu (22) et une feuille de cuivre rouge (24) sont laminés sur le matériau de plaquage (33) et comprimées de manière à former un plaquage (34) pour ensemble semi-conducteur dont l'attaque sélective permet d'obtenir une fenêtre (17) dans laquelle viennent se monter une puce de semi-conducteur (1) et un circuit imprimé (10).
PCT/JP2000/004156 1999-06-25 2000-06-23 Materiau plaque pour ensemble semi-conducteur et ensemble semi-conducteur comportant ledit materiau plaque WO2001000508A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001506930A JP4623622B2 (ja) 1999-06-25 2000-06-23 半導体パッケージ用クラッド材の製造方法および半導体パッケージの製造方法
AU54300/00A AU5430000A (en) 1999-06-25 2000-06-23 Semiconductor package clad material and semiconductor package using the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11/180715 1999-06-25
JP18071599 1999-06-25

Publications (1)

Publication Number Publication Date
WO2001000508A1 true WO2001000508A1 (fr) 2001-01-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/004156 WO2001000508A1 (fr) 1999-06-25 2000-06-23 Materiau plaque pour ensemble semi-conducteur et ensemble semi-conducteur comportant ledit materiau plaque

Country Status (3)

Country Link
JP (1) JP4623622B2 (fr)
AU (1) AU5430000A (fr)
WO (1) WO2001000508A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6884530B2 (en) 2001-05-31 2005-04-26 Sfc, Smart Fuel Cell Ag Method of improving the performance of a direct feed fuel cell
JP2008084687A (ja) * 2006-09-27 2008-04-10 Matsushita Electric Ind Co Ltd 半導体装置用気密端子
KR20090089267A (ko) * 2008-02-18 2009-08-21 신코 덴키 코교 가부시키가이샤 반도체 장치의 제조 방법, 반도체 장치 및 배선 기판
JP2012146963A (ja) * 2010-12-20 2012-08-02 Shinko Electric Ind Co Ltd 半導体パッケージの製造方法及び半導体パッケージ
JP2019208045A (ja) * 2019-07-17 2019-12-05 太陽誘電株式会社 回路基板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06151642A (ja) * 1992-10-29 1994-05-31 Sumitomo Kinzoku Ceramics:Kk Ｉｃパッケージ
JPH09266267A (ja) * 1996-03-28 1997-10-07 Hitachi Chem Co Ltd 転写配線支持部材及びそれを使用した半導体パッケージの製造法
US5773879A (en) * 1992-02-13 1998-06-30 Mitsubishi Denki Kabushiki Kaisha Cu/Mo/Cu clad mounting for high frequency devices
JPH11284111A (ja) * 1998-03-30 1999-10-15 Sumitomo Special Metals Co Ltd ヒートシンク部材及びその製造方法、並びにヒートシンク部材を用いた半導体パッケージ

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6318647A (ja) * 1986-07-11 1988-01-26 Hitachi Cable Ltd 半導体装置用セラミツク基板の製造方法およびその方法に使用するクラツド材
JPH03241859A (ja) * 1990-02-20 1991-10-29 Fujitsu Ltd 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5773879A (en) * 1992-02-13 1998-06-30 Mitsubishi Denki Kabushiki Kaisha Cu/Mo/Cu clad mounting for high frequency devices
JPH06151642A (ja) * 1992-10-29 1994-05-31 Sumitomo Kinzoku Ceramics:Kk Ｉｃパッケージ
JPH09266267A (ja) * 1996-03-28 1997-10-07 Hitachi Chem Co Ltd 転写配線支持部材及びそれを使用した半導体パッケージの製造法
JPH11284111A (ja) * 1998-03-30 1999-10-15 Sumitomo Special Metals Co Ltd ヒートシンク部材及びその製造方法、並びにヒートシンク部材を用いた半導体パッケージ

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6884530B2 (en) 2001-05-31 2005-04-26 Sfc, Smart Fuel Cell Ag Method of improving the performance of a direct feed fuel cell
JP2008084687A (ja) * 2006-09-27 2008-04-10 Matsushita Electric Ind Co Ltd 半導体装置用気密端子
KR20090089267A (ko) * 2008-02-18 2009-08-21 신코 덴키 코교 가부시키가이샤 반도체 장치의 제조 방법, 반도체 장치 및 배선 기판
JP2009194322A (ja) * 2008-02-18 2009-08-27 Shinko Electric Ind Co Ltd 半導体装置の製造方法、半導体装置及び配線基板
US8217509B2 (en) 2008-02-18 2012-07-10 Shinko Electric Industries Co., Ltd. Semiconductor device
US9048242B2 (en) 2008-02-18 2015-06-02 Shinko Electric Industries Co., Ltd. Semiconductor device manufacturing method, semiconductor device, and wiring board
KR101602958B1 (ko) * 2008-02-18 2016-03-11 신코 덴키 코교 가부시키가이샤 반도체 장치의 제조 방법, 반도체 장치 및 배선 기판
JP2012146963A (ja) * 2010-12-20 2012-08-02 Shinko Electric Ind Co Ltd 半導体パッケージの製造方法及び半導体パッケージ
JP2019208045A (ja) * 2019-07-17 2019-12-05 太陽誘電株式会社 回路基板

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Publication number Publication date
AU5430000A (en) 2001-01-31
JP4623622B2 (ja) 2011-02-02

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