WO2001000508A1 - Semiconductor package clad material and semiconductor package using the same - Google Patents

Semiconductor package clad material and semiconductor package using the same Download PDF

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Publication number
WO2001000508A1
WO2001000508A1 PCT/JP2000/004156 JP0004156W WO0100508A1 WO 2001000508 A1 WO2001000508 A1 WO 2001000508A1 JP 0004156 W JP0004156 W JP 0004156W WO 0100508 A1 WO0100508 A1 WO 0100508A1
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WO
WIPO (PCT)
Prior art keywords
layer
frame
semiconductor package
base substrate
semiconductor
Prior art date
Application number
PCT/JP2000/004156
Other languages
French (fr)
Japanese (ja)
Inventor
Kinji Saijo
Kazuo Yoshida
Hiroaki Okamoto
Sinji Ohsawa
Original Assignee
Toyo Kohan Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Kohan Co., Ltd. filed Critical Toyo Kohan Co., Ltd.
Priority to JP2001506930A priority Critical patent/JP4623622B2/en
Priority to AU54300/00A priority patent/AU5430000A/en
Publication of WO2001000508A1 publication Critical patent/WO2001000508A1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits

Definitions

  • the present invention relates to a cladding material for a semiconductor package and a semiconductor package using the same.
  • Japanese Patent Application Laid-Open No. 5-219425 discloses a base substrate having ⁇ 11 1 ⁇ 0 / ⁇ .
  • One using the clad material of No. 1 has been proposed.
  • the Cu / Mo / Cu clad material is compatible with the coefficient of thermal expansion of the semiconductor chip and has good thermal conductivity, so that it can be used as a heat sink of a semiconductor package.
  • f plate and the window frame formed in a frame shape surrounding the semiconductor chip are manufactured in a separate manufacturing process and are bonded using glass or adhesive, so their bonding strength is weak.
  • Cu ZMo Cu clad material which has excellent heat dissipation properties, there is a problem that it may be peeled off from the bonded part due to repeated heating and cooling.
  • An object of the present invention is to solve the above problems, and to provide a clad plate for a semiconductor package which can be manufactured at low cost and has good characteristics, and a semiconductor package using the same. And Disclosure of the invention
  • the cladding material for a semiconductor package according to the present invention comprises a base substrate for bonding a semiconductor chip, and a wind frame formed in a frame shape so as to surround the semiconductor chip.
  • a clad plate comprising a Cii layer characterized in that a base substrate and a frame plate are integrated.
  • the next feature of the clad material of the present invention is that a clad material for manufacturing a semiconductor package composed of a base substrate for bonding a semiconductor chip and a window frame formed in a frame shape so as to surround the semiconductor chip.
  • the base substrate is a Cu foil material
  • the frame plate forming the wind frame is a clad plate composed of a Ni layer and a ZCu layer, and the base substrate and the frame plate are integrated. 10
  • the semiconductor package of the present invention is a semiconductor package comprising a base substrate for joining a semiconductor chip and a window frame formed in a frame shape so as to surround the semiconductor chip, wherein the base substrate has a Cu layer ZMo.
  • the wind frame is composed of a Ni layer and a Cu layer.
  • the next feature of the semiconductor package of the present invention is that in a semiconductor package constituted by a base substrate for bonding a semiconductor chip and a wind frame formed in a frame shape so as to surround the semiconductor chip, the base substrate is made of Cu foil. And the wind frame is made of a Ni layer / Cu layer.
  • the next feature of the semiconductor package of the present invention is a clad material for manufacturing a semiconductor package composed of a base substrate for bonding a semiconductor chip and a window frame formed in a frame shape so as to surround the semiconductor chip.
  • the heat radiating plate constituting the base substrate is a clad material composed of a Cu layer and a ZMo layer / Cu layer
  • the frame plate constituting the wind frame is a clad material composed of a Ni layer and a ZCu layer.
  • the next feature of the semiconductor package of the present invention is a clad material for manufacturing a semiconductor package constituted by a base substrate for bonding a semiconductor chip and a frame-shaped wind frame surrounding the semiconductor chip.
  • a radiator plate forming the base substrate is a Cu foil material;
  • a frame plate forming the wind frame is a clad plate formed of a Ni layer and a ZCu layer; and the radiator plate and the frame This is the result of etching the Cu surface of the frame plate of the cladding material for semiconductor package, which has become a body, to form a recess for inserting the semiconductor.
  • FIG. 1 is a cross-sectional view of a cladding material for a semiconductor package according to one embodiment of the present invention.
  • FIG. 2 is a sectional view of a cladding material for a semiconductor package according to another embodiment of the present invention.
  • FIG. 3 is a process explanatory view of a
  • FIG. 4 is a process explanatory view of a method for manufacturing a semiconductor package according to one embodiment of the present invention.
  • FIG. 5 is a process explanatory view of a method for manufacturing a semiconductor package according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional front view of the clad plate manufacturing apparatus.
  • an etching stopper made of a Ni layer is provided below a base substrate 33 (thickness is preferably 30 to 500 / im) having three layers of a Cu layer, a ZMo layer, and a Cu layer.
  • a layer 12 (0.5-3 is preferred) is formed.
  • This one The thickness ratio of each layer of the substrate may be determined so as to be close to the coefficient of thermal expansion of the material used for the semiconductor chip. For example, if S i is used in the semiconductor chip, C u: Mo: thickness ratio of Cu is 1: 1: 1, then the thermal expansion coefficient of 9. 9 (XI 0 one B Z ° C :, 3 0-1 0 0 :) next, S i of a thermal expansion coefficient of 9.
  • a Cu foil material 24 is formed below the Ni layer 12.
  • CI The thickness of the foil material is preferably 30 to 500 zm.
  • a nickel material serving as an etching stop layer 12 is formed on one side of a clad material 33 (preferably having a thickness of 30 to 500 m) composed of a Cu layer ZMo layer / Cu layer serving as a base substrate of a semiconductor package.
  • a clad material consisting of a Cu layer, a ZMo layer and a ZCu layer plated with nickel by plating 21 is produced (see Fig. 1).
  • a clad material 19 composed of a Cu layer / Mo layer and a ZCu layer with nickel plating is wound around a rewind reel 23 in the clad plate manufacturing apparatus shown in FIG. Further, the copper foil material 24 to be the wind frame 17 is wound around the rewind reel 25. From the rewind reels 23 and 25, the clad material 19 made of nickel-coated Cu layer ZMo layer and ZCu layer 0 and the copper foil material 24 are simultaneously rewound, and a part of them is etched into the etching chamber 26. It is wound around the protruding electrode rolls 27, 28, and is activated by a sputter etching process in the etching chamber 26.
  • the activation processing as the applicant has disclosed in JP-1 one 2 24 1 84 JP above, 1 1 X 1 0 ' ⁇ 1 X 1 0- 2 P a of extremely low pressure inert
  • the clad material 22 consisting of a Cu layer / Mo layer and a ZCu layer with a nickel-bonded surface with a ⁇ joint surface and a copper foil material 24 were each used as one electrode A, which was grounded, and was insulated and supported.
  • the clad material 31 is cold-welded at a low reduction rate of 0.1 to 3% by a rolling unit 30 provided in a vacuum chamber 29, and the clad material 31 is wound around a winding roll 32. Since cold welding is performed at a low reduction rate of 0.1 to 3%, the flatness of the bonding interface can be maintained by keeping the stress at the bonding interface low. Also, since heat treatment for recovering workability is not required, an alloy layer is not formed at the joint interface, so that the selective etching property is excellent. Thus, a cladding plate 1034 for a semiconductor package having a five-layer structure is manufactured as shown in FIG.
  • a Cu foil composed of the Cu layer 22 alone may be used as shown in FIG.
  • a clad material composed of a Cu layer, a ZMo layer, and a ZCu layer As the base substrate, an example was described in which a clad material composed of a Cu layer, a ZMo layer, and a ZCu layer, which had been previously plated with nickel, was pressed.
  • the above equipment may be used in which a nickel foil is pressed against a clad material comprising a Cu layer, a ZMo layer, and a Cu layer at a low reduction rate of 0.1 to 3%.
  • a copper foil material pre-plated with nickel may be pressed against a clad material comprising a Cu layer / Mo layer and a ZCu layer.
  • a clad material made of copper foil and nickel foil using the above-mentioned yo facility and a clad material composed of this clad material and a clad material composed of a Cu layer, a Mo layer, and a ZCu layer can also be applied.
  • the nickel layer serving as the etching stopper layer may be provided by nickel plating on a Cu foil or a copper foil material serving as a window frame. Furthermore, it is also applicable that the nickel foil was pressed against a copper foil material is a Cu foil or a window frame> beam under low pressure ratio of 0.1 to 3%.
  • Copper / molybdenum Z copper z A multilayer clad plate made of gel Z copper or copper Z nickel Z copper can be manufactured.
  • a multilayer clad plate can be manufactured with a single pressure welding.
  • a semiconductor package is manufactured through the following steps described with reference to FIGS. First, as shown in FIG. 3, after forming a photoresist j ir film 35 on the surface of the Dohakuzai 2 4, exposed and developed.
  • the copper foil material 24 is selectively etched, and the copper foil material 24 is removed while leaving the window frame 17.
  • an etching solution it is desirable to use a sulfuric acid + hydrogen peroxide solution or an ammonium persulfate solution.
  • the nickel layer exposed in the concave portion of the semiconductor package and the ⁇ 0 semiconductor chip 1 are bonded with an adhesive.
  • the printed board 10 is bonded to the copper foil material 24, and the printed board 10 and the semiconductor chip 1 are wired by wiring 3.
  • the semiconductor chip 1 is covered with the resin mold 39, and the wiring in the printed board is wired with the solder bump 2.
  • the clad plate for a semiconductor package of the present invention has a Cu layer A ZMo layer / / Cu layer / N i layer ZC u layer or clad material consisting of C u layer ZN i layer ZCu layer, since the pressure in the low pressure ratio of 0.1 to 3%, of the bonding interface Stress can be kept low. As a result, the flatness of the bonding interface can be maintained, and no heat treatment for recovering the workability is required, so that no intermetallics are generated at the interface. Therefore, a cladding plate for a semiconductor package having excellent selective etching properties is provided. be able to. Since the semiconductor package of the present invention has one etching stopper made of a nickel layer, the etched surface becomes flat after etching the Cu foil, and the bonding property of the semiconductor chip is improved.
  • the semiconductor package of the present invention is characterized in that the clad material composed of the Cu layer, the ZMo layer, and the ZCu layer used for the base substrate has an appropriate thickness ratio, so that the material used for the semiconductor chip and the heat The coefficient of expansion is close and the thermal expansion matching is excellent. Further, the clad material or Cu composed of the Cu layer, the ZMo layer, and the ZCu layer used in the semiconductor package of the present invention has excellent heat conductivity, and thus has excellent heat dissipation characteristics.

Abstract

A semiconductor package clad plate and a semiconductor package that can be produced at low cost and that have good characteristics. To this end, the clad material (33) is characterized by comprising Cu layer / Mo layer / Cu layer with a nickel layer (21) interposed to serve as an etching stopper layer (12). Further, the semiconductor package is produced such that a Cu layer (22) and a copper foil (24) are laminated on the clad material (33) and pressed to form a semiconductor package clad plate (34), which is selectively etched to form a window frame (17), to which a semiconductor chip (1) and a printed board (10) are attached.

Description

明 細 書 半導体パッケージ用クラッド材およびそれを用いた半導体パッケージ ί, 技術分野  Description Cladding material for semiconductor package and semiconductor package using the same ί, Technical field
本発明は、 半導体パッケージ用クラッド材およびそれを用いた半導体パッケ一 ジに関する。 背景技術  The present invention relates to a cladding material for a semiconductor package and a semiconductor package using the same. Background art
i O 放熱性を改良した半導体パッケージとして、 特開平 5— 2 9 1 4 2 5号公報に は、 べース基板に〇11 1^ 0 /。 1のクラッド材を用いたものが提案されている 。 このC u /M o / C uのクラッド材は、 半導体チップの熱膨張率と整合性がと れ、 熱伝導率がよいので、 半導体パッケージの放熱板として用いることができる 。 しかし、 半導体パッケージを構成するための半導体チップを接合するベース基As a semiconductor package having improved i.sub.O heat dissipation, Japanese Patent Application Laid-Open No. 5-219425 discloses a base substrate having {11 1 ^ 0 /}. One using the clad material of No. 1 has been proposed. The Cu / Mo / Cu clad material is compatible with the coefficient of thermal expansion of the semiconductor chip and has good thermal conductivity, so that it can be used as a heat sink of a semiconductor package. However, the base substrate for joining semiconductor chips to form a semiconductor package
||f 板と、 半導体チップを取り囲むように枠状に形成したウィンドフレームとは、 別 の製造プロセスで製造され、 ガラスや接着剤などを用いて接着されているので、 その接合強度は弱く、 放熱性が優れている C u ZM oノ C uクラッド材を用いて いるにもかかわらず、 加熱冷却の繰り返しによって、 接着部分から剥離してしま うおそれがあるという問題点がある。 The || f plate and the window frame formed in a frame shape surrounding the semiconductor chip are manufactured in a separate manufacturing process and are bonded using glass or adhesive, so their bonding strength is weak. Despite the use of Cu ZMo Cu clad material, which has excellent heat dissipation properties, there is a problem that it may be peeled off from the bonded part due to repeated heating and cooling.
^ 本発明は、 上記の問題を解決しょうとするものであり、 安価に製造することが できかつ良好な特性を有する半導体パッケ一ジ用クラッド板およびそれを用いた 半導体パッケージを提供することを課題とする。 発明の開示  ^ An object of the present invention is to solve the above problems, and to provide a clad plate for a semiconductor package which can be manufactured at low cost and has good characteristics, and a semiconductor package using the same. And Disclosure of the invention
^ 本発明の半導体パッケージ用クラッド材は、 半導体チップを接合するベース基 板と、 半導体チップを取り囲むように枠状に形成したウィンドフレームとによつ て構成された半導体パッケージを製造するためのクラッド材であって、 ベース基 板が、 C u層 ZM o層 Z C u層からなるクラッド板であり、 ウィンドフレームを 形成するフレーム板が、 N i層/ C ii層からなるクラッド板であり、 ベース基板 とフレーム板とがー体となったものであることを特徴とする。 ^ The cladding material for a semiconductor package according to the present invention comprises a base substrate for bonding a semiconductor chip, and a wind frame formed in a frame shape so as to surround the semiconductor chip. A clad material for manufacturing a semiconductor package configured by the method described above, wherein the base substrate is a clad plate composed of a Cu layer, a ZMo layer, and a ZCu layer, and the frame plate forming the wind frame is an Ni layer. / A clad plate comprising a Cii layer, characterized in that a base substrate and a frame plate are integrated.
If 本発明のクラッド材の次の特徴は、 半導体チップを接合するベース基板と、 半 導体チップを取り囲むように枠状に形成したウインドフレームとによって構成さ れた半導体パッケージを製造するためのクラッド材であって、 ベース基板が、 C u箔材であり、 ウィンドフレームを形成するフレーム板が、 N i層Z C u層から なるクラッド板であり、 ベース基板とフレーム板とがー体となったものであるこ 10 とである。  The next feature of the clad material of the present invention is that a clad material for manufacturing a semiconductor package composed of a base substrate for bonding a semiconductor chip and a window frame formed in a frame shape so as to surround the semiconductor chip. Wherein the base substrate is a Cu foil material, the frame plate forming the wind frame is a clad plate composed of a Ni layer and a ZCu layer, and the base substrate and the frame plate are integrated. 10
本発明の半導体パッケージは、 半導体チップを接合するベース基板と、 半導体 チップを取り囲むように枠状に形成したウインドフレームとによつて構成された 半導体パッケージにおいて、 前記ベース基板が、 C u層 ZM o層 Z C u層からな り、 前記ウィンドフレームが、 N i層ノ C u層からなるものであることを特徴と iir する。  The semiconductor package of the present invention is a semiconductor package comprising a base substrate for joining a semiconductor chip and a window frame formed in a frame shape so as to surround the semiconductor chip, wherein the base substrate has a Cu layer ZMo. The wind frame is composed of a Ni layer and a Cu layer.
本発明の半導体パッケージの次の特徴は、 半導体チップを接合するベース基板 と、 半導体チップを取り囲むように枠状に形成したウィンドフレームとによって 構成された半導体パッケージにおいて、 前記ベース基板が、 C u箔材からなり、 前記ウインドフレームが、 N i層/ C u層からなるものであることである。 The next feature of the semiconductor package of the present invention is that in a semiconductor package constituted by a base substrate for bonding a semiconductor chip and a wind frame formed in a frame shape so as to surround the semiconductor chip, the base substrate is made of Cu foil. And the wind frame is made of a Ni layer / Cu layer.
X) 本発明の半導体パッケージの次の特徴は、 半導体チップを接合するベース基板 と、 半導体チップを取り囲むように枠状に形成したウインドフレームとによって 構成された半導体パッケージを製造するためのクラッド材であって、 前記ベース 基板を構成する放熱板が、 C u層 ZM o層/ C u層からなるクラッド材であり、 前記ウィンドフレームを構成するフレーム板が、 N i層 Z C u層からなるクラッX) The next feature of the semiconductor package of the present invention is a clad material for manufacturing a semiconductor package composed of a base substrate for bonding a semiconductor chip and a window frame formed in a frame shape so as to surround the semiconductor chip. The heat radiating plate constituting the base substrate is a clad material composed of a Cu layer and a ZMo layer / Cu layer, and the frame plate constituting the wind frame is a clad material composed of a Ni layer and a ZCu layer.
^ ド板であり、 前記放熱板と前記フレーム板とがー体となった、 半導体パッケージ 用クラッド材の、 フレーム板の C u面をエッチングして、 半導体を挿入する窪み を形成させたものであることを特徴とする。 A concave plate into which a semiconductor is inserted by etching a Cu surface of a frame plate of a cladding material for a semiconductor package, in which the heat sink and the frame plate are integrated. Is formed.
本発明の半導体パッケージの次の特徴は、 半導体チップを接合するベース基板 と、 半導体チップを取り囲むように枠状に形成したウィンドフレームとによって 構成された半導体パッケージを製造するためのクラッド材であって、 前記ベース 基板を構成する放熱板が、 C u箔材であり、 前記ウィンドフレームを構成するフ レーム板が、 N i層 Z C u層からなるクラッド板であり、 前記放熱板と前記フレ ーム板とがー体となった、 半導体パッケージ用クラッド材の、 フレーム板の C u 面をエッチングして、 半導体を挿入する窪みを形成させたものであることである  The next feature of the semiconductor package of the present invention is a clad material for manufacturing a semiconductor package constituted by a base substrate for bonding a semiconductor chip and a frame-shaped wind frame surrounding the semiconductor chip. A radiator plate forming the base substrate is a Cu foil material; a frame plate forming the wind frame is a clad plate formed of a Ni layer and a ZCu layer; and the radiator plate and the frame This is the result of etching the Cu surface of the frame plate of the cladding material for semiconductor package, which has become a body, to form a recess for inserting the semiconductor.
10 Ten
図面の簡単な説明  BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の一実施の形態に係る半導体パッケージ用クラッド材の断面図 である。 図 2は、 本発明の他の一実施の形態に係る半導体パッケージ用クラッド 材断面図である。 図 3は、 本発明の一実施の形態に係る半導体パッケージの製造 ,|f 方法の工程説明図である。 図 4は、 本発明の一実施の形態に係る半導体パッケ一 ジの製造方法の工程説明図である。 図 5は、 本発明の一実施の形態に係る半導体 パッケージの製造方法の工程説明図である。 図 6は、 クラッド板の製造装置の断 面正面図である。  FIG. 1 is a cross-sectional view of a cladding material for a semiconductor package according to one embodiment of the present invention. FIG. 2 is a sectional view of a cladding material for a semiconductor package according to another embodiment of the present invention. FIG. 3 is a process explanatory view of a | f method of manufacturing a semiconductor package according to an embodiment of the present invention. FIG. 4 is a process explanatory view of a method for manufacturing a semiconductor package according to one embodiment of the present invention. FIG. 5 is a process explanatory view of a method for manufacturing a semiconductor package according to one embodiment of the present invention. FIG. 6 is a cross-sectional front view of the clad plate manufacturing apparatus.
^ 発明を実施するための最良の形態 ^ BEST MODE FOR CARRYING OUT THE INVENTION
以下、 図 1〜図 6に示す一実施の形態を参照して、 本発明を具体的に説明する 。 まず、 本発明の一実施の形態に係る半導体パッケージ用クラッド板の構造につ いて、 図 1を参照して説明する。  Hereinafter, the present invention will be described in detail with reference to an embodiment shown in FIGS. First, a structure of a clad plate for a semiconductor package according to an embodiment of the present invention will be described with reference to FIG.
図 1において、 C u層 ZM o層/ C u層の 3層からなるベース基板 3 3 (厚み 3 0〜 5 0 0 /i mが好適である） の下部には N i層からなるエッチングストツ パー層 1 2 (厚み 0 . 5〜 3 が好適である） が形成されている。 このべ一 ス基板の各層の厚み比率は、 半導体チップに使われている材料の熱膨張係数に近 くなるように決めればよい。 例えば、 半導体チップに S iが使われている場合、 C u ： Mo ： Cuの厚み比率が 1 ： 1 ： 1であれば、 熱膨張係数は 9. 9 (X I 0一 BZ°C：、 3 0〜 1 0 0 :) となり、 S iの熱膨張係数である 9. 6 (X 1 0一 6 if 〃C、 0〜 1 0 0 ） に近い値となる。 さらに、 N i層 1 2の下部には C u箔材 24が形成されている。 C I：箔材の厚みは 3 0〜5 0 0 zmが好適である。 In FIG. 1, an etching stopper made of a Ni layer is provided below a base substrate 33 (thickness is preferably 30 to 500 / im) having three layers of a Cu layer, a ZMo layer, and a Cu layer. A layer 12 (0.5-3 is preferred) is formed. This one The thickness ratio of each layer of the substrate may be determined so as to be close to the coefficient of thermal expansion of the material used for the semiconductor chip. For example, if S i is used in the semiconductor chip, C u: Mo: thickness ratio of Cu is 1: 1: 1, then the thermal expansion coefficient of 9. 9 (XI 0 one B Z ° C :, 3 0-1 0 0 :) next, S i of a thermal expansion coefficient of 9. 6 (X 1 0 one 6 an if 〃C from 0 1 0 0) becomes a value close to. Further, a Cu foil material 24 is formed below the Ni layer 12. CI: The thickness of the foil material is preferably 30 to 500 zm.
二ッケル層からなるエッチングストッパー層があるため、 C u箔材をエツチン グした後、 エッチング表面は平坦となり、 半導体チップの接合性は良好となる。 これらのベース基板 3 3と、 N i層 1 2と、 Cu箔材 24とで本発明の半導体 j0 パッケージ用クラッド板 34を形成する。 Since there is an etching stopper layer consisting of a nickel layer, the etched surface becomes flat after etching the Cu foil material, and the bonding property of the semiconductor chip becomes good. These base substrates 3 3, and N i layer 1 2, the semiconductor j 0 package clad plate 34 of the present invention with the Cu foil member 24.
次に、 上記した半導体パッケージ用クラッド材の製造方法について説明する。 まず、 半導体パッケージのベース基板となる C u層 ZMo層/ C u層からなるク ラッド材 3 3 (厚み 3 0〜5 0 0 m好適である） の片面にエッチングストツ パー層 1 2となるニッケルめっき 2 1を施してニッケルめつきした C u層 ZMo 層 ZC u層からなるクラッド材を製造する （図 1参照） 。  Next, a method for manufacturing the clad material for a semiconductor package described above will be described. First, a nickel material serving as an etching stop layer 12 is formed on one side of a clad material 33 (preferably having a thickness of 30 to 500 m) composed of a Cu layer ZMo layer / Cu layer serving as a base substrate of a semiconductor package. A clad material consisting of a Cu layer, a ZMo layer and a ZCu layer plated with nickel by plating 21 is produced (see Fig. 1).
次に、 ニッケルめつきした C u層/ Mo層 ZCu層からなるクラッド材 1 9を 、 図 6に示すクラッド板製造装置における巻き戻しリール 2 3に巻き付ける。 ま た、 ウィンドフレーム 1 7となる銅箔材 24を卷き戻しリール 2 5に巻き付ける 。 巻き戻しリール 2 3、 2 5からニッケルめつきした C u層 ZMo層 ZC u層か 0 らなるクラッド材 1 9と銅箔材 24を同時に巻き戻し、 その一部をエッチングチ ヤンバ 2 6内に突出した電極ロール 2 7、 2 8に巻き付け、 エッチングチャンバ 2 6内において、 スパッ夕エッチング処理して活性化する。  Next, a clad material 19 composed of a Cu layer / Mo layer and a ZCu layer with nickel plating is wound around a rewind reel 23 in the clad plate manufacturing apparatus shown in FIG. Further, the copper foil material 24 to be the wind frame 17 is wound around the rewind reel 25. From the rewind reels 23 and 25, the clad material 19 made of nickel-coated Cu layer ZMo layer and ZCu layer 0 and the copper foil material 24 are simultaneously rewound, and a part of them is etched into the etching chamber 26. It is wound around the protruding electrode rolls 27, 28, and is activated by a sputter etching process in the etching chamber 26.
この際、 活性化処理は、 本出願人が先に特開平 1一 2 24 1 84号公報で開示 したように、 ① 1 X 1 0 '〜 1 X 1 0— 2 P a の極低圧不活性ガス雰囲気中で、 ② ^ 接合面を有するニッケルめつきした C u層/ Mo層 ZC u層からなるクラッド材 2 2と銅箔材 24をそれぞれアース接地した一方の電極 Aとし、 絶縁支持された 他の電極 Bとの間に 1〜 50 MHzの交流を印加してグロ一放電を行わせ、 ③か つ、 前記グロ一放電によって生じたプラズマ中に露出される電極の面積が、 電極 Bの面積の 1 / 3以下で、 ④スパッ夕エッチング処理することによって行う。 その後、 真空槽 29内に設けた圧延ユニット 30によって 0. 1〜3%の低圧 下率で冷間圧接し、 クラッド材 31を巻き取りロール 32に巻き取る。 0. 1〜 3 %の低圧下率で冷間圧接するため、 接合界面のストレスを低く抑えることによ つて接合界面の平坦度を保持できる。 また、 加工性回復のための熱処理も不要で あるため、 接合界面に合金層は生成しないので、 選択エッチング性にも優れる。 このように、 図 1に示すように 5層構造を有する半導体パッケージ用クラッド板 10 34を製造する。 In this case, the activation processing, as the applicant has disclosed in JP-1 one 2 24 1 84 JP above, ① 1 X 1 0 '~ 1 X 1 0- 2 P a of extremely low pressure inert In a gas atmosphere, the clad material 22 consisting of a Cu layer / Mo layer and a ZCu layer with a nickel-bonded surface with a ^^ joint surface and a copper foil material 24 were each used as one electrode A, which was grounded, and was insulated and supported. Applying an AC of 1 to 50 MHz to another electrode B to cause a glow discharge, and ③ and the area of the electrode exposed in the plasma generated by the glow discharge is This is performed by etching the surface with less than 1/3 of the area. Thereafter, the clad material 31 is cold-welded at a low reduction rate of 0.1 to 3% by a rolling unit 30 provided in a vacuum chamber 29, and the clad material 31 is wound around a winding roll 32. Since cold welding is performed at a low reduction rate of 0.1 to 3%, the flatness of the bonding interface can be maintained by keeping the stress at the bonding interface low. Also, since heat treatment for recovering workability is not required, an alloy layer is not formed at the joint interface, so that the selective etching property is excellent. Thus, a cladding plate 1034 for a semiconductor package having a five-layer structure is manufactured as shown in FIG.
ベース基板として、 C u層/ Mo層ノ C u層からなるクラッド材を使う例を図 1で説明したが、 図 2に示すように、 Cu層 22単独からなる Cu箔を使っても 良い。  Although an example in which a clad material composed of a Cu layer / Mo layer and a Cu layer is used as the base substrate has been described with reference to FIG. 1, a Cu foil composed of the Cu layer 22 alone may be used as shown in FIG.
なお、 ベース基板として、 C u層 ZMo層 ZC u層からなるクラッド材を使う i 場合、 C u層 ZMo層 ZC u層からなるクラッド材に予めニッケルめっきをした ものを圧接する例を説明したが、 ニッケルめっきに代えて上記設備を用いて Cu 層 ZMo層/ Cu層からなるクラッド材にニッケル箔を、 0. 1〜3%の低圧下 率で圧接したものも適用できる。 また、 銅箔材に予めニッケルめっきをしたもの を、 C u層/ Mo層 ZC u層からなるクラッド材に圧接しても良い。 更に、 上記 yo 設備を用いて、 銅箔とニッケル箔のクラッド材を作製し、 このクラッド材と Cu 層ノ M o層 Z C u層からなるクラッド材を圧接したものも適用できる。  In the case of using a clad material composed of a Cu layer, a ZMo layer, and a ZCu layer as the base substrate, an example was described in which a clad material composed of a Cu layer, a ZMo layer, and a ZCu layer, which had been previously plated with nickel, was pressed. Instead of nickel plating, the above equipment may be used in which a nickel foil is pressed against a clad material comprising a Cu layer, a ZMo layer, and a Cu layer at a low reduction rate of 0.1 to 3%. Alternatively, a copper foil material pre-plated with nickel may be pressed against a clad material comprising a Cu layer / Mo layer and a ZCu layer. Further, a clad material made of copper foil and nickel foil using the above-mentioned yo facility, and a clad material composed of this clad material and a clad material composed of a Cu layer, a Mo layer, and a ZCu layer can also be applied.
また、 ベース基板として、 Cu箔を使う場合、 エッチングストッパー層である ニッケル層付与は、 C u箔あるいはウインドフレームである銅箔材へのニッケル めっきによる方法で良い。 さらに、 ニッケル箔を Cu箔あるいはウィンドフレー > ムである銅箔材とを 0. 1〜 3%の低圧下率で圧接したものも適用できる。 When a Cu foil is used as the base substrate, the nickel layer serving as the etching stopper layer may be provided by nickel plating on a Cu foil or a copper foil material serving as a window frame. Furthermore, it is also applicable that the nickel foil was pressed against a copper foil material is a Cu foil or a window frame> beam under low pressure ratio of 0.1 to 3%.
上記設備を使用して圧接を繰返し行うことにより、 銅/モリブデン Z銅 zニッ ゲル Z銅あるいは銅 Zニッケル Z銅からなる多層のクラッド板を製造することが できる。 Copper / molybdenum Z copper z A multilayer clad plate made of gel Z copper or copper Z nickel Z copper can be manufactured.
さらに、 上記巻き戻しリールを 3台以上設けこれらのリールに C u層 ZM o層 Z C u層からなるクラッド材、 銅箔材ゃニッケル箔材などを設置し、 3台以上の I リールから箔材の供給を同時に受けることにより、 1回の圧接で多層構造のクラ ッド板を製造することができる。  In addition, three or more of the above-mentioned rewind reels are installed, and clad material consisting of Cu layer, ZMo layer, and ZCu layer, copper foil material and nickel foil material are installed on these reels. , A multilayer clad plate can be manufactured with a single pressure welding.
これらの圧接は 0 . 1〜3 %の低圧下率での冷間圧延で行う。 このため、 接合 界面のストレスを低く抑えることによって接合界面の平坦度を保持できる。 また 、 加工性回復のための熱処理も不要であるため、 接合界面に合金層が生成しない jO のでエッチング後のエッチング表面は平坦になりやすい。  These pressure weldings are performed by cold rolling at a low reduction rate of 0.1 to 3%. Therefore, the flatness of the bonding interface can be maintained by suppressing the stress at the bonding interface. In addition, since heat treatment for recovering workability is not necessary, an alloy surface is not formed at the joint interface, and the etched surface after etching is likely to be flat.
C u層 i層 Z C u層からなる半導体パッケージ用クラッド板を使った工程 について図 3〜 5で説明する。 半導体パッケージ用クラッド板 3 4を所望の大き さに切断した後、 図 3〜図 5を参照して説明する以下の工程を経て半導体パッケ ージを製造する。 まず、 図 3に示すように、 銅箔材 2 4の表面にフォトレジスト j ir 膜 3 5を形成した後、 露光，現像する。 The process using a clad plate for semiconductor package consisting of Cu layer, i layer, and ZCu layer will be described with reference to Figs. After the semiconductor package cladding plate 34 is cut into a desired size, a semiconductor package is manufactured through the following steps described with reference to FIGS. First, as shown in FIG. 3, after forming a photoresist j ir film 35 on the surface of the Dohakuzai 2 4, exposed and developed.
次に、 図 4に示すように、 銅箔材 2 4の選択エッチングを行い、 銅箔材 2 4を 、 ウィンドフレーム 1 7を残して除去する。 エッチング液としては、 硫酸 +過酸 化水素水液または過硫酸アンモニゥム液等を用いることが望ましい。  Next, as shown in FIG. 4, the copper foil material 24 is selectively etched, and the copper foil material 24 is removed while leaving the window frame 17. As an etching solution, it is desirable to use a sulfuric acid + hydrogen peroxide solution or an ammonium persulfate solution.
そして、 図 5に示すように、 半導体パッケージの凹部で露出したニッケル層と ^0 半導体チップ 1を接着剤で接着する。 更に、 プリント基板 1 0を銅箔材 2 4に接 着し、 プリント基板 1 0と半導体チップ 1をワイヤリング 3で配線する。 配線後 、 樹脂モールド 3 9で半導体チップ 1を覆い、 プリント基板内の配線を半田バン プ 2で配線する。  Then, as shown in FIG. 5, the nickel layer exposed in the concave portion of the semiconductor package and the ^ 0 semiconductor chip 1 are bonded with an adhesive. Further, the printed board 10 is bonded to the copper foil material 24, and the printed board 10 and the semiconductor chip 1 are wired by wiring 3. After the wiring, the semiconductor chip 1 is covered with the resin mold 39, and the wiring in the printed board is wired with the solder bump 2.
^ 産業上の利用可能性 ^ Industrial applicability
以上説明してきたように、 本発明の半導体パッケージ用クラッド板は、 C u層 ZMo層//Cu層/N i層 ZC u層あるいは C u層 ZN i層 ZCu層からなるク ラッド材であり、 0. 1〜3 %の低圧下率で圧接しているので、 接合界面のスト レスを低く抑えられる。 このため、 接合界面の平坦度を保持でき、 かつ、 加工性 回復のための熱処理も不要であるため界面に合金属は生成しないので、 選択エツ チング性に優れた半導体パッケージ用クラッド板を提供することができる。 本発明の半導体用パッケージは、 ニッケル層からなるエッチングストッパ一層 があるため、 C u箔をエッチングした後、 エッチング面が平らになり、 半導体チ ップの接合性が良好となる。 As described above, the clad plate for a semiconductor package of the present invention has a Cu layer A ZMo layer / / Cu layer / N i layer ZC u layer or clad material consisting of C u layer ZN i layer ZCu layer, since the pressure in the low pressure ratio of 0.1 to 3%, of the bonding interface Stress can be kept low. As a result, the flatness of the bonding interface can be maintained, and no heat treatment for recovering the workability is required, so that no intermetallics are generated at the interface. Therefore, a cladding plate for a semiconductor package having excellent selective etching properties is provided. be able to. Since the semiconductor package of the present invention has one etching stopper made of a nickel layer, the etched surface becomes flat after etching the Cu foil, and the bonding property of the semiconductor chip is improved.
また、 本発明の半導体パッケージは、 ベース基板に使われている C u層 ZMo 層 ZC u層からなるクラッド材において、 その厚み比率を適切な値とすることで 、 半導体チップに使われる材料と熱膨張率が近くなり、 熱膨張整合性に優れる。 更に、 本発明の半導体パッケージに使われている C u層 ZMo層 ZC u層からな るクラッド材あるいは Cuは熱伝導性に優れるため、 放熱特性にも優れる。  In addition, the semiconductor package of the present invention is characterized in that the clad material composed of the Cu layer, the ZMo layer, and the ZCu layer used for the base substrate has an appropriate thickness ratio, so that the material used for the semiconductor chip and the heat The coefficient of expansion is close and the thermal expansion matching is excellent. Further, the clad material or Cu composed of the Cu layer, the ZMo layer, and the ZCu layer used in the semiconductor package of the present invention has excellent heat conductivity, and thus has excellent heat dissipation characteristics.

Claims

請 求 の 範 囲 The scope of the claims
1. 半導体チップを接合するべ一ス基板と、 半導体チップを取り囲むように枠 状に形成したウィンドフレームとによって構成された半導体パッケージを製造す1. Manufacture a semiconductor package composed of a base substrate for joining semiconductor chips and a frame-shaped window frame surrounding the semiconductor chips.
If るためのクラッド材であって、 前記ベース基板が、 C u層 ZMo層/ Cu層から なるクラッド板であり、 前記ウィンドフレームを形成するフレーム板が、 N i層 ZC u層からなるクラッド板であり、 前記ベース基板と前記フレーム板とが一体 となった、 半導体パッケージ用クラッド材。 The base substrate is a clad plate comprising a Cu layer, a ZMo layer / Cu layer, and the frame plate forming the wind frame is a clad plate comprising a Ni layer, a ZCu layer. A cladding material for a semiconductor package, wherein the base substrate and the frame plate are integrated.
2. 半導体チップを接合するベース基板と、 半導体チップを取り囲むように枠 jD 状に形成したウィンドフレームとによって構成された半導体パッケージを製造す るためのクラッド材であって、 前記ベース基板が、 C u箔材であり、 前記ウィン ドフレームを形成するフレーム板が、 N i層ノ Cu層からなるクラッド板であり 、 前記ベース基板と前記フレーム板とがー体となった、 半導体パッケージ用クラ ッ卜^。  2. A clad material for manufacturing a semiconductor package composed of a base substrate for bonding a semiconductor chip and a wind frame formed in a frame jD shape so as to surround the semiconductor chip, wherein the base substrate is C u a foil material, wherein the frame plate forming the window frame is a clad plate comprising a Ni layer and a Cu layer, and wherein the base substrate and the frame plate are formed into a body. ^^.
^ 3. 半導体チップを接合するベース基板と、 半導体チップを取り囲むように枠 状に形成したウィンドフレームとによつて構成された半導体パッケージにおいて 、 前記ベース基板が、 C u層 Mo層 ZC u層からなり、 前記ウィンドフレーム が、 N i層/ Cu層からなる、 半導体パッケージ。  ^ 3. In a semiconductor package composed of a base substrate for joining a semiconductor chip and a frame-shaped wind frame surrounding the semiconductor chip, the base substrate is formed of a Cu layer, a Mo layer, and a ZCu layer. A semiconductor package, wherein the wind frame comprises a Ni layer / Cu layer.
4. 半導体チップを接合するベース基板と、 半導体チップを取り囲むように枠 状に形成したウィンドフレームとによって構成された半導体パッケージにおいて 4. In a semiconductor package composed of a base substrate that joins semiconductor chips and a frame-shaped wind frame that surrounds the semiconductor chips
、 前記ベース基板が、 Cu箔材からなり、 前記ウィンドフレームが、 N i層ノC u層からなる、 半導体パッケージ。 A semiconductor package, wherein the base substrate is made of a Cu foil material, and the wind frame is made of a Ni layer and a Cu layer.
5. 半導体チップを接合するベース基板と、 半導体チップを取り囲むように枠 状に形成したウィンドフレームとによって構成された半導体パッケージを製造す るためのクラッド材であって、 前記ベース基板を構成する放熱板が、 C u層ノ M o層 ZCu層からなるクラッド材であり、 前記ウィンドフレームを構成するフレ ーム板が、 N i層 ZCu層からなるクラッド板であり、 前記放熱板と前記フレー ム板とが一体となった、 半導体パッケージ用クラッド材の、 フレーム板の Cu面 をエッチングして、 半導体を挿入する窪みを形成させた半導体パッケージ。 5. A cladding material for manufacturing a semiconductor package composed of a base substrate for bonding a semiconductor chip and a frame-shaped wind frame surrounding the semiconductor chip, the heat radiation constituting the base substrate The plate is a clad material comprising a Cu layer, a Mo layer, and a ZCu layer, and the frame constituting the wind frame is The frame plate is a clad plate composed of a Ni layer and a ZCu layer, and the Cu surface of the frame plate of the cladding material for a semiconductor package, in which the heat sink and the frame plate are integrated, is etched. Semiconductor package in which a recess for inserting a hole is formed.
6. 半導体チップを接合するベース基板と、 半導体チップを取り囲むように枠6. Base substrate for bonding semiconductor chips and frame to surround semiconductor chips
If 状に形成したウィンドフレームとによって構成された半導体パッケ一ジを製造す るためのクラッド材であって、 前記べ一ス基板を構成する放熱板が、 Cu箔材で あり、 前記ウィンドフレームを構成するフレーム板が、 N i層 ZCu層からなる クラッド板であり、 前記放熱板と前記フレーム板とがー体となった、 半導体パッ ケージ用クラッド材の、 フレーム板の Cu面をエッチングして、 半導体を挿入すA cladding material for manufacturing a semiconductor package constituted by an if-shaped wind frame, wherein the heat sink forming the base substrate is a Cu foil material; and The constituting frame plate is a clad plate composed of a Ni layer and a ZCu layer, and the Cu surface of the frame plate of the cladding material for a semiconductor package, in which the heat sink and the frame plate are integrated, is etched. Insert semiconductor
|0 る窪みを形成させた半導体パッケージ。 | 0 A semiconductor package with a hollow.
PCT/JP2000/004156 1999-06-25 2000-06-23 Semiconductor package clad material and semiconductor package using the same WO2001000508A1 (en)

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JP2012146963A (en) * 2010-12-20 2012-08-02 Shinko Electric Ind Co Ltd Manufacturing method of semiconductor package and the semiconductor package
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US6884530B2 (en) 2001-05-31 2005-04-26 Sfc, Smart Fuel Cell Ag Method of improving the performance of a direct feed fuel cell
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JP2019208045A (en) * 2019-07-17 2019-12-05 太陽誘電株式会社 Circuit board

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