WO2000065661A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur Download PDF

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Publication number
WO2000065661A1
WO2000065661A1 PCT/JP1999/002129 JP9902129W WO0065661A1 WO 2000065661 A1 WO2000065661 A1 WO 2000065661A1 JP 9902129 W JP9902129 W JP 9902129W WO 0065661 A1 WO0065661 A1 WO 0065661A1
Authority
WO
WIPO (PCT)
Prior art keywords
base layer
bevel
semiconductor device
type base
layer
Prior art date
Application number
PCT/JP1999/002129
Other languages
English (en)
Japanese (ja)
Inventor
Kenji Oota
Katsumi Satoh
Original Assignee
Mitsubishi Denki Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Denki Kabushiki Kaisha filed Critical Mitsubishi Denki Kabushiki Kaisha
Priority to PCT/JP1999/002129 priority Critical patent/WO2000065661A1/fr
Publication of WO2000065661A1 publication Critical patent/WO2000065661A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching

Definitions

  • the present invention relates to a semiconductor device such as a thyristor, and more particularly to stabilization of a voltage blocking characteristic.
  • a bevel structure with a pn-junction surface inclined to reduce the electric field strength on the pn-junction surface and improve the withstand voltage performance of the surface is used as a method of obtaining a predetermined voltage blocking capability.
  • Many structures have been applied.
  • This bevel structure is an attempt to address the problem that the surface where the pn junction is exposed is affected by a special surface state, causing local electric field concentration and lowering the breakdown voltage of the junction.
  • the surface electric field is made weaker than the internal electric field to avoid breakdown at the surface of the junction.
  • the semiconductor substrate 1 has a p-type emitter layer 2 forming the main surface 1a, an n-type base layer 3 adjacent to the p-type emitter layer 2, and an n-type base layer 3 adjacent to the n-type base layer 3. And a p-type base layer 4 forming part of the main surface 1 b, a mold emitter layer 5 adjacent to the p-type base layer 4 and forming a part of the main surface 1 b, and main surfaces 1 a and 1 and an end face 1c formed substantially perpendicular to b.
  • the formed joint J3 has bevel surface portions 8a and 8b having a bevel angle of 0.
  • the semiconductor device 9 is composed of 1 to 8.
  • a depletion layer is formed on both sides of the junction J2.
  • This depletion layer has a voltage blocking capability by actively extending toward the n-type base layer 3 having a low impurity concentration. Since the conventional semiconductor device 9 is configured as described above, if the bevel angle 0 is too large, the electric field is locally concentrated on the central portion A of the bevel surface portions 8a and 8b, and If the bevel angle 0 is too small, there is a problem that a predetermined voltage blocking ability cannot be secured.
  • the present invention does not have the problems of the conventional semiconductor device having a bevel structure, that is, suppresses the occurrence of local electric field concentration at the center of the bevel surface, and achieves a predetermined voltage blocking capability.
  • the purpose is to provide a semiconductor device that can be obtained. Disclosure of the invention
  • An end face formed substantially perpendicular to both main surfaces of the semiconductor substrate has a depth D which becomes deeper as the distance from each main surface increases, and the depth D and the semiconductor substrate A concave portion whose relationship with the thickness T satisfies the relationship of D> T / 2 is formed. This makes it possible to reduce the electric field strength and to obtain a predetermined voltage blocking capability.
  • a central surface portion in which the concave portion is formed substantially perpendicular to both main surfaces a bevel surface portion in which one is in phosphor contact with one of the central surface portions, and the other is in phosphor contact with the end surface portion, and one is in phosphoric contact with the other of the central surface portions.
  • each bevel surface is formed by a connecting bevel surface, local electric field concentration at the center of the bevel surface can be suppressed.
  • the concave portion is formed in a substantially semicircular or semielliptical shape, it is possible to suppress the occurrence of local electric field concentration at the center of the bevel surface.
  • FIG. 1 is a sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view showing a cross-sectional structure of a semiconductor device when a simulation is performed to demonstrate the effect of the present invention (simulation 1).
  • FIG. 3 is a cross-sectional view showing a cross-sectional structure of a semiconductor device when a simulation is performed to demonstrate the effect of the present invention (simulation 2).
  • FIG. 4 is a cross-sectional view showing a cross-sectional structure of a semiconductor device when a simulation is performed to demonstrate the effect of the present invention (simulation). 3).
  • FIG. 5 is a cross-sectional view showing a cross-sectional structure of a semiconductor device when a simulation is performed to demonstrate the effect of the present invention (simulation 4).
  • FIG. 6 is an explanatory diagram showing the results of simulation for demonstrating the effect of the present invention, and shows the relationship between the figures used for each simulation and the maximum electric field strength.
  • FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 8 is a cross-sectional view showing a configuration of a conventional semiconductor device. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention, for example, a thyristor.
  • a semiconductor substrate 11 includes a p-type emitter layer 12 forming a main surface 11 a, an n-type base layer 13 adjacent to the p-type emitter layer 12, and an n-type base layer.
  • anode electrode 16 formed on the surface of the p-type emitter layer 12 and the cathode formed on the partial surface of the p-type base layer 14 and the n-type emitter layer 15 are formed.
  • a gate electrode (not shown).
  • the end face portion 11c has a depth D that becomes deeper as the distance from the main surfaces 11a and 11b increases, and the depth D and the thickness of the semiconductor substrate 11 are different from each other.
  • the recess 18 satisfies the relationship of D> T / 2.
  • the concave portion 18 has a central surface portion 18 e formed substantially perpendicular to the main surfaces 11 a and 11 b, one of which is in phosphor contact with one of the central surface portions 18 e, and the other has an end surface portion 1 1 c
  • the beveled surfaces 18a, 18b, 18c, and 18d that are in contact with each other are in contact with the other of the central surface 18e, and the other is in contact with the end surface 11c.
  • Bevel surfaces 18 f, 18 g, 18 h, and 18 i that are in contact with each other are formed.
  • junction J 11 formed of p-type emitter layer 12 and n-type base layer 13, junction formed of n- type base layer 13 and p-type base layer 14 J 1 2 , And a junction J 13 formed by the p-type base layer 14 and the n-type emitter layer 15.
  • the semiconductor device 19 is composed of 11 to 18.
  • FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device when employed in the simulation 1, and has a configuration similar to that of a conventional semiconductor device.
  • a semiconductor substrate 21 includes a p-type emitter layer 22 forming a main surface 21a, an n-type base layer 23 adjacent to a p-type emitter layer 22, and an n-type base layer.
  • a cathode electrode 26 formed on the surface of the p-type emitter layer 22 and a cathode electrode 27 formed on a part of the surface of the p-type base layer 24 and the n-type emitter layer 25 are formed.
  • a gate electrode (not shown).
  • the end face 2 1 c has a depth that increases with distance from the main surface 2 la, 2 1 b.
  • Bevel surface portions 28a and 28b having Junction J21 formed by p-type emitter layer 22 and n-type base layer 23, junction J22 formed by n-type base layer 23 and p-type base layer 24, and p-type base layer 24 And a junction J23 formed by the n-type emitter layer 25.
  • the semiconductor device 29 is composed of 21 to 28.
  • FIG. 3 is a cross-sectional view showing a cross-sectional structure of the semiconductor device when adopted in Simulation 2.
  • the semiconductor substrate 31 includes a p-type emitter layer 32 forming the main surface 31a, an n-type base layer 33 adjacent to the p-type emitter layer 32, and an n-type base layer 33.
  • a cathode electrode 36 formed on the surface of the p-type emitter layer 32 and a cathode electrode 37 formed on a partial surface of the p-type base layer 34 and the n-type emitter layer 35 are not shown.
  • a gate electrode is not shown.
  • the end face portion 31c has a depth D that becomes deeper as the distance from the main surfaces 31a and 31b increases, and the relationship between the depth D and the thickness of the semiconductor substrate 31 is D ⁇ T.
  • a concave portion 38 that satisfies the relationship of / 2 is formed.
  • the recess 38 has a central surface 38 e formed substantially perpendicular to the main surfaces 3 la and 3 1 b, one of which is in phosphor contact with one of the central surfaces 38 e, and the other is in phosphor contact with the end surface 31 c.
  • junction J 31 formed by p-type emitter layer 32 and n-type base layer 33, junction J 32 formed by n-type base layer 33 and p-type base layer 34, and p A junction J33 formed by the mold base layer 34 and the n-type emitter layer 35 is provided.
  • the semiconductor device 39 is constituted by 31 to 38.
  • FIG. 4 is a cross-sectional view showing a cross-sectional structure of the semiconductor device when employed in the simulation 3, and has a configuration similar to that of the first embodiment of the present invention.
  • the same reference numerals as those used in FIG. 3 indicate the same or equivalent products. 4 is different from FIG. 3 only in that the relationship between the depth D of the recess 38 and the thickness T of the semiconductor substrate 31 is changed. That is, the end face 31 c has a depth D that is formed deeper away from the main surfaces 3 la, 31 b, and the depth D and the thickness T of the semiconductor substrate 31. Form a recess 38 that satisfies the relationship D> T72.
  • FIG. 5 is a cross-sectional view showing a cross-sectional structure of the semiconductor device when adopted in Simulation 4.
  • the semiconductor substrate 41 includes a p-type emitter layer 42 forming the main surface 41 a, an n-type base layer 43 adjacent to the p-type emitter layer 42, and an n-type base layer.
  • P-type base layer 44 adjacent to the base layer 43 and forming part of the main surface 41 b, and part of the main surface 41 b adjacent to the p-type base layer 44 It has a shaped emissive layer 45 and an end face 41 c formed substantially perpendicular to the main surfaces 4 la and 41 b.
  • anode electrode 46 formed on the surface of the p-type emitter layer 42 and a force electrode 47 formed on a part of the surface of the p-type base layer 44 and the n-type emitter layer 45 And a gate electrode not shown.
  • the semiconductor device 49 is composed of 41 to 48.
  • anode electrodes 26, 36, and 46 are connected to GND (0 V—constant) on the semiconductor devices 29, 39, and 49 having four types of bevel structures as shown in Simulations 1 to 4.
  • a voltage of 400 V was applied to force source electrodes 27, 37, and 47, and the maximum electric field strength in each bevel structure was simulated.
  • Fig. 6 is an explanatory diagram showing the results of this simulation, showing the relationship between the diagram corresponding to each bevel structure used in each simulation and the maximum electric field strength (relative value).
  • the maximum electric field strength in the bevel structure is set to 1
  • the maximum electric field strengths in the other bevel structures shown in FIGS. 3 to 5 are represented by relative values.
  • the maximum electric field intensity has the relationship of FIG. 2> FIG. 3> FIG. 4> FIG.
  • the bevel structure in FIG. 3 can disperse the electric field concentration portion by increasing the number of steps of the bevel surface, as compared with the bevel structure in FIG. 2, so that the bevel structure is about 10 times smaller than the conventional bevel structure.
  • % Electric field intensity can be reduced.
  • the electric field intensity can be further reduced by forming a concave portion that satisfies the relationship of D> T / 2 as shown in Fig. 4, and therefore, the electric field intensity is reduced by about 25% compared to the conventional bevel structure. It becomes possible.
  • bevel structure shown in Fig. 5 is a structure that blocks voltage only in the forward direction, and is not directly applied to high-withstand-voltage thyristors. No conventional electric field concentration. The electric field strength is reduced by about 35%.
  • a pair of main surfaces 11a, 11b and a main surface 11a are formed.
  • P-type emitter layer 12, n-type base layer 13 adjacent to p-type emitter layer 12, and P adjacent to n-type base layer 13 and forming part of main surface 11 b A semiconductor base 11 having a mold base layer 14; and an end face 11c formed substantially perpendicular to both main surfaces 11a and 11b of the semiconductor base 11;
  • a concave portion 1 having a depth D that becomes deeper as it moves away from 11a and 11b, and wherein the relationship between the depth D and the thickness T of the semiconductor substrate 11 satisfies the relationship of D> T / 2.
  • a concave portion 18 is formed so as to be substantially perpendicular to both main surfaces 11a and 11b, a central surface portion 18e, one of which is in phosphorous contact with one of the central surface portions 18e, and the other is an end surface portion.
  • 18f, 18g, 18h, 18i which are connected to each other and are connected to the bevel surface, cause local electric field concentration at the center of the bevel surface. Can be suppressed.
  • FIG. 7 is a sectional view showing a configuration according to Embodiment 2 of the present invention.
  • a semiconductor substrate 51 includes a p-type emitter layer 52 forming a main surface 51 a, an n-type base layer 53 adjacent to the p-type emitter layer 52, and an n-type base layer 53.
  • a p-type base layer 54 that forms part of the main surface 51 b and a p-type base layer 54 that forms part of the main surface 51 b adjacent to the p-type pace layer 54. It has an evening layer 55 and an end face 51c formed substantially perpendicular to the main surfaces 51a and 51b.
  • anode electrode 56 formed on the surface of the p-type emitter layer 52, a cathode electrode 57 formed on a partial surface of the p-type base layer 54 and the n-type emitter layer 55, and Gate electrode that is not provided.
  • the end face 51c has a depth D that is formed deeper away from the main surfaces 51a and 51b, and the relationship between the depth D and the thickness T of the semiconductor substrate 51 is different.
  • a semi-circular or semi-elliptical recess 58 that satisfies the relationship D> T / 2 is provided.
  • the semiconductor device according to the present invention is suitable for stabilizing the voltage element characteristics.
  • DC transmission electric or iron-making thyristor Leonard power supply, AC motor speed control power supply, power control switch It is suitable for inverters.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur, tel qu'un thyristor, doté de caractéristiques de blocage des tensions stabilisées. Ce dispositif comporte un substrat semi-conducteur ayant une paire de surfaces principales, une première couche semi-conductrice d'un premier type de conductivité constituant l'une desdites surfaces principales, une deuxième couche semi-conductrice du premier type de conductivité, adjacente à ladite première couche semi-conductrice, et une troisième couche semi-conductrice d'un second type de conductivité constituant l'autre surface principale et étant adjacente à la deuxième couche semi-conductrice. Un évidement est formé dans une face latérale généralement perpendiculaire aux deux surfaces principales. La profondeur D de cet évidement croit progressivement en direction de son centre à partir de chacune des surfaces principales, et la formule représentant sa relation avec l'épaisseur T du substrat semi-conducteur est D⊃T/2. Cet évidement permet de réduire l'intensité du champ et d'obtenir une capacité prédéterminée de blocage de la tension.
PCT/JP1999/002129 1999-04-22 1999-04-22 Dispositif semi-conducteur WO2000065661A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1999/002129 WO2000065661A1 (fr) 1999-04-22 1999-04-22 Dispositif semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1999/002129 WO2000065661A1 (fr) 1999-04-22 1999-04-22 Dispositif semi-conducteur

Publications (1)

Publication Number Publication Date
WO2000065661A1 true WO2000065661A1 (fr) 2000-11-02

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Application Number Title Priority Date Filing Date
PCT/JP1999/002129 WO2000065661A1 (fr) 1999-04-22 1999-04-22 Dispositif semi-conducteur

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WO (1) WO2000065661A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196502A (ja) * 2005-01-11 2006-07-27 Mitsubishi Electric Corp 電力用半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039883A (fr) * 1973-07-06 1975-04-12
JPS552740B1 (fr) * 1970-12-26 1980-01-22

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS552740B1 (fr) * 1970-12-26 1980-01-22
JPS5039883A (fr) * 1973-07-06 1975-04-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196502A (ja) * 2005-01-11 2006-07-27 Mitsubishi Electric Corp 電力用半導体装置

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