WO2000046704A3 - Automated processor generation system and method for designing a configurable processor - Google Patents

Automated processor generation system and method for designing a configurable processor Download PDF

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Publication number
WO2000046704A3
WO2000046704A3 PCT/US2000/003091 US0003091W WO0046704A3 WO 2000046704 A3 WO2000046704 A3 WO 2000046704A3 US 0003091 W US0003091 W US 0003091W WO 0046704 A3 WO0046704 A3 WO 0046704A3
Authority
WO
WIPO (PCT)
Prior art keywords
configurable
processor
designing
sets
user
Prior art date
Application number
PCT/US2000/003091
Other languages
French (fr)
Other versions
WO2000046704A2 (en
Inventor
Earl A Killian
Ricardo E Gonzalez
Ashish B Dixit
Monica Lam
Walter D Lichtenstein
Christopher Rowen
John Ruttenberg
Robert P Wilson
Albert Ren-Rui Wang
Dror Eliezer Maydan
Weng Kiang Tjiang
Richard Rudell
Original Assignee
Tensilica Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/246,047 external-priority patent/US6477683B1/en
Priority claimed from US09/323,161 external-priority patent/US6701515B1/en
Priority claimed from US09/322,735 external-priority patent/US6477697B1/en
Application filed by Tensilica Inc filed Critical Tensilica Inc
Priority to EP00913380A priority Critical patent/EP1159693A2/en
Priority to AU34841/00A priority patent/AU3484100A/en
Priority to JP2000597714A priority patent/JP2003518280A/en
Priority to KR1020077017999A priority patent/KR100874738B1/en
Publication of WO2000046704A2 publication Critical patent/WO2000046704A2/en
Publication of WO2000046704A3 publication Critical patent/WO2000046704A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3006—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/37—Compiler construction; Parser generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Abstract

A configurable RISC processor implements a user-definable instruction set with high performance fixed and variable length encoding. The process of defining new instruction sets is supported by tools that allow the user to add new instructions and rapidly evaluate them, to maintain multiple instruction sets and to easily switch between them. A standardized language is used to develop configurable definitions of target instructions sets, HDL descriptions of hardware needed to implement the instruction set, and development tools for verification and application development, thus enabling a high degree of automation in the design process.
PCT/US2000/003091 1999-02-05 2000-02-04 Automated processor generation system and method for designing a configurable processor WO2000046704A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP00913380A EP1159693A2 (en) 1999-02-05 2000-02-04 Automated processor generation system & method for designing a configurable processor
AU34841/00A AU3484100A (en) 1999-02-05 2000-02-04 Automated processor generation system for designing a configurable processor andmethod for the same
JP2000597714A JP2003518280A (en) 1999-02-05 2000-02-04 Automatic processor generation system and method for designing a configurable processor
KR1020077017999A KR100874738B1 (en) 1999-02-05 2000-02-04 Automated processor generation system for designing a configurable processor and method for the same

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US09/246,047 US6477683B1 (en) 1999-02-05 1999-02-05 Automated processor generation system for designing a configurable processor and method for the same
US09/246,047 1999-02-05
US09/323,161 1999-05-27
US09/323,161 US6701515B1 (en) 1999-05-27 1999-05-27 System and method for dynamically designing and evaluating configurable processor instructions
US09/322,735 1999-05-28
US09/322,735 US6477697B1 (en) 1999-02-05 1999-05-28 Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set

Publications (2)

Publication Number Publication Date
WO2000046704A2 WO2000046704A2 (en) 2000-08-10
WO2000046704A3 true WO2000046704A3 (en) 2000-12-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/003091 WO2000046704A2 (en) 1999-02-05 2000-02-04 Automated processor generation system and method for designing a configurable processor

Country Status (6)

Country Link
EP (1) EP1159693A2 (en)
JP (2) JP2003518280A (en)
KR (2) KR100775547B1 (en)
AU (1) AU3484100A (en)
TW (1) TW539965B (en)
WO (1) WO2000046704A2 (en)

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DE10128339A1 (en) * 2001-06-12 2003-01-02 Systemonic Ag Development of the circuit arrangements used in digital signal processing technology especially using the HDL development language to generate a development circuit arrangement for comparison with a reference model
US6941548B2 (en) * 2001-10-16 2005-09-06 Tensilica, Inc. Automatic instruction set architecture generation
DE10205523A1 (en) * 2002-02-08 2003-08-28 Systemonic Ag Method for providing a design, test and development environment and a system for executing the method
US7200735B2 (en) 2002-04-10 2007-04-03 Tensilica, Inc. High-performance hybrid processor with configurable execution units
JP2003316838A (en) 2002-04-19 2003-11-07 Nec Electronics Corp Design method for system lsi and storage medium with the method stored therein
JP4202673B2 (en) * 2002-04-26 2008-12-24 株式会社東芝 System LSI development environment generation method and program thereof
US7937559B1 (en) 2002-05-13 2011-05-03 Tensilica, Inc. System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
US7346881B2 (en) 2002-05-13 2008-03-18 Tensilica, Inc. Method and apparatus for adding advanced instructions in an extensible processor architecture
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
KR100799183B1 (en) 2003-08-20 2008-01-29 니뽄 다바코 산교 가부시키가이샤 Program generation system, record medium for recording program generation program, and program generation module
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WO2009084570A1 (en) * 2007-12-28 2009-07-09 Nec Corporation Compiler embedded function adding device
JP5217431B2 (en) 2007-12-28 2013-06-19 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device
JP2010181942A (en) * 2009-02-03 2010-08-19 Renesas Electronics Corp System and method for providing information on estimation of replacement from pld/cpld to microcomputer
US8775125B1 (en) 2009-09-10 2014-07-08 Jpmorgan Chase Bank, N.A. System and method for improved processing performance
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KR101635397B1 (en) * 2010-03-03 2016-07-04 삼성전자주식회사 Method and apparatus for simulation of multi core system using reconfigurable processor core
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KR102122455B1 (en) * 2013-10-08 2020-06-12 삼성전자주식회사 Method and apparatus for generating test bench for verification of a processor decoder
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CN111400986B (en) * 2020-02-19 2024-03-19 西安智多晶微电子有限公司 Integrated circuit computing equipment and computing processing system
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Also Published As

Publication number Publication date
TW539965B (en) 2003-07-01
KR20020021081A (en) 2002-03-18
KR100775547B1 (en) 2007-11-09
JP2003518280A (en) 2003-06-03
KR100874738B1 (en) 2008-12-22
AU3484100A (en) 2000-08-25
KR20070088818A (en) 2007-08-29
EP1159693A2 (en) 2001-12-05
WO2000046704A2 (en) 2000-08-10
JP2007250010A (en) 2007-09-27
CN1382280A (en) 2002-11-27

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