CN111400986B - Integrated circuit computing equipment and computing processing system - Google Patents
Integrated circuit computing equipment and computing processing system Download PDFInfo
- Publication number
- CN111400986B CN111400986B CN202010103240.XA CN202010103240A CN111400986B CN 111400986 B CN111400986 B CN 111400986B CN 202010103240 A CN202010103240 A CN 202010103240A CN 111400986 B CN111400986 B CN 111400986B
- Authority
- CN
- China
- Prior art keywords
- processing module
- risc
- instruction set
- core
- soft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012545 processing Methods 0.000 title claims abstract description 65
- 238000012360 testing method Methods 0.000 claims description 20
- 230000004044 response Effects 0.000 claims description 13
- 230000002093 peripheral effect Effects 0.000 claims description 9
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 238000004590 computer program Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000003190 augmentative effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013135 deep learning Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Advance Control (AREA)
Abstract
The invention discloses an integrated circuit computing device, comprising: the first processing module is used for receiving and processing RISC-V instruction set instructions, wherein the RISC-V instruction set instructions comprise basic instructions, extension instructions and custom instructions; the second processing module comprises a soft-core coprocessor which is connected with the first processing module through a first interface and is used for processing the custom instruction sent by the first processing module; a first bus connecting the first processing module and the second processing module; and a first port connected to the first processing module and a second port connected to the second processing module. According to the invention, the RISC-V architecture hard core processor is embedded in the FPGA chip, and the soft core coprocessor is designed in the programmable part of the FPGA chip, so that the processor core can be flexibly adjusted by an FPGA chip developer according to the needs, the computing capacity of the FPGA chip is enhanced, the equipment area is ensured to be small, the power consumption is low, and the manufacturing cost is low.
Description
Technical Field
The invention belongs to the field of system-on-chip design, and particularly relates to integrated circuit computing equipment and a computing processing system.
Background
Currently, in FPGA (Field Programmable Gate Array ) designs, a processor hard core or soft core is typically embedded, i.e. an ASIC (Application Specific Integrated Circuit ) circuit of the processor is embedded inside the FPGA chip or a processor is implemented on the programmable logic of the FPGA in the form of HDL (Hardware Description Language ) program code.
However, the FPGAs with embedded processor hard cores are all commercial IP cores such as ARM (Advanced RISC Machine, advanced simplified instruction set machine) and PowerPC, and the use of commercial IP can greatly increase the use cost of the FPGA user, on the one hand, the cost of the FPGA is increased, and on the other hand, when the user needs to change the design on the FPGA into the design of ASIC (Application Specific Integrated Circuit ), additional use cost of IP is still required; secondly, the internal design details of most commercial IP cores (Intellectual Property core) are invisible, which is unsatisfactory for application scenes (such as security scenes of national defense and military industry) which partially require the chip to be completely safe and controllable; thirdly, the commercial IP has poor design flexibility, on one hand, the instruction set of the processor is fixed, and a user cannot add a custom instruction to optimize the product performance; on the other hand, once a certain IP core is selected, the subsequent product is limited by IP capability when being upgraded. And because the FPGA using the soft core needs to occupy logic resources on the FPGA in the soft core verification process, and compared with the hard core, the FPGA using the soft core has large power consumption, large area and lower computing capacity, thus the FPGA using the soft core cannot meet the application requirements of high precision and high real-time performance, and has poor practicability.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an integrated circuit computing device and a computing processing system. The technical problems to be solved by the invention are realized by the following technical scheme:
an embodiment of the present invention provides an integrated circuit computing device, comprising:
the first processing module is used for receiving and processing RISC-V instruction set instructions, wherein the RISC-V instruction set instructions comprise basic instructions, extension instructions and custom instructions;
the second processing module comprises a soft-core coprocessor which is connected with the first processing module through a first interface and is used for processing the custom instruction sent by the first processing module;
a first bus connecting the first processing module and the second processing module; and
a first port connected to the first processing module and a second port connected to the second processing module.
In one embodiment, the first processing module includes: RISC-V instruction set processor, memory unit, peripheral extension unit;
the RISC-V instruction set processor interconnects the memory unit and the peripheral expansion unit through a first bus, and is also connected with the soft core coprocessor through the first interface.
In one specific embodiment, the first interface includes:
a core control group signal comprising control signals or status signals sent and received by the RISC-V instruction set processor to the soft-core coprocessor;
an instruction register set signal comprising an instruction signal sent by the RISC-V instruction set processor to the soft-core coprocessor and a received response signal;
a memory bank signal comprising data signals sent and received by a cache of the RISC-V instruction set processor to the soft-core coprocessor;
the custom set signal comprises a custom instruction signal and a received response signal which are sent to the soft-core coprocessor by the RISC-V instruction set processor.
In one embodiment, the apparatus further comprises:
a first debug port coupled to the first processing module and a second debug port coupled to the second processing module.
In one embodiment, the first processing module further includes: a first test access interface connecting said RISC-V instruction set processor and said first debug port.
In a specific embodiment, the first test access interface is a JTAG interface.
In one embodiment, the second processing module includes:
the system comprises a programmable logic gate array, a configuration block and a second test access interface, wherein the programmable logic gate array is connected with the configuration block, the configuration block is connected with the second test access interface, and the second test access interface is connected with the second debug port.
In a specific embodiment, the second test access interface is a JTAG interface.
In a specific embodiment, the first bus interface protocol includes AMBA protocol or TileLink protocol.
In one embodiment, the RISC-V instruction set processor comprises CPU, GPU, DSP or a hardware accelerator.
Embodiments of the present invention also provide a computing processing system comprising a host, and further comprising the above-described integrated circuit computing device coupled to the host.
Compared with the prior art, the invention has the beneficial effects that:
according to the embodiment of the invention, the RISC-V architecture hard core processor is embedded in the FPGA chip, and the soft core coprocessor is designed in the programmable part of the FPGA chip, so that the RISC-V hard core processor can be helped to realize the standard expansion instruction set and the custom expansion instruction of the RISC-V instruction set, and the processor core can be flexibly adjusted by an FPGA chip developer according to the requirement, thereby enhancing the computing capacity of the FPGA chip, and ensuring small equipment area, low power consumption and low manufacturing cost.
Drawings
FIG. 1 is a block diagram of an integrated circuit computing device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an integrated circuit computing device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a first interface design of an integrated circuit computing device according to an embodiment of the present invention;
fig. 4 is a diagram showing a specific example of a first interface signal of an integrated circuit computing device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a block diagram of an integrated circuit computing device according to an embodiment of the present invention, including:
a first processing module 1, configured to receive and process RISC-V instruction set instructions, where the RISC-V instruction set instructions include a basic instruction, an extended instruction, and a custom instruction;
the second processing module 2 comprises a soft-core coprocessor 21, wherein the soft-core coprocessor 21 is connected with the first processing module 1 through a first interface 31 and is used for processing the custom instruction sent by the first processing module 1;
a first bus 3 connecting the first processing module 1 and the second processing module 2; and
a first port 4 connected to the first processing module 1 and a second port 5 connected to the second processing module 2.
RISC-V is an open source instruction set architecture which has been developed in recent years, RISC-V is completely open source, the architecture is simple, the performance is excellent, the lifting space is large and the RISC-V processor has a complete tool chain, the architecture of the RISC-V processor can be flexibly adjusted according to different applications, for example, a multiplication instruction set (RV 32M), a single-precision floating point operation instruction set (RV 32F), a double-precision floating point operation instruction set (RV 32D) and the like can be added on an RV32I basic instruction set of RISC-V. The hardware may or may not contain these extensions, as desired by the user software program. After knowing which extensions the current hardware contains, the RISC-V compiler can generate the best code under the current hardware conditions. In addition to the standard extended instruction set, custom instructions are added to the instruction set.
The first processing module is a system on a chip (SOC) with a RISC-V instruction set used by a core processor, which can be a CPU Block, and a hard core of the RISC-V instruction set processor is integrated inside the CPU Block. The second processing module is an FPGA Block and realizes a coprocessor in the form of an FPGA soft core.
The invention utilizes the flexibility characteristic of RISC-V instruction set, and proposes the structure of RISC-V hard core main processor and FPGA programmable soft core coprocessor: the RISC-V hard core main processor is responsible for the operation related to a basic instruction set and a part of standard expansion instruction sets, and the coprocessor realized in the form of an FPGA soft core is responsible for the operation related to the standard expansion instruction sets or custom instructions required by other users. The architecture allows for both the improved processor core performance in the form of a hard core implementation and the compatibility of the processor for hardware acceleration in different fields (e.g., deep learning, augmented reality, combinatorial optimization, graphics, etc.). Meanwhile, the invention also provides an interface between the RISC-V hard core processor and the soft core coprocessor in the FPGA.
Of course, in other embodiments, the processor in the first processing module may also be a GPU, DSP, or hardware accelerator, etc. that employs a RISC-V architecture.
Firstly, the reduced and flexible characteristic of RISC-V instruction set in cost can obviously reduce the area of a single chip, thereby reducing the material cost. And secondly, RISC-V is an instruction set with a completely open source, so that not only can the cost (authorized fee) be saved for an FPGA manufacturer, but also the cost can be saved for an FPGA user (when the product of the user is converted from the FPGA to the ASIC flow, the authorized fee for using the processor architecture is not required to be paid).
In a specific implementation manner, please continue to refer to fig. 2, fig. 2 is a schematic diagram of an integrated circuit computing device design provided in an embodiment of the present invention, and the first processing module includes: a RISC-V instruction set processor 11, a memory unit 12, a peripheral extension unit 13;
the RISC-V instruction set processor 11 interconnects the memory unit 12 and the peripheral extension unit 13 via the first bus 3, the RISC-V instruction set processor 11 being further connected to the soft-core coprocessor 21 via the first interface 31.
The RISC-V instruction set processor 11 is a processor adopting a RISC-V architecture, and is used for receiving and executing a RISC-V instruction set, the storage unit 12 is used for storing execution data, and the peripheral extension unit 13 may be, for example, adding some man-machine interaction peripherals, etc.
In a specific implementation manner, please refer to fig. 3, fig. 3 is a schematic diagram of a first interface design of an integrated circuit computing device according to an embodiment of the present invention, where the first interface 31 includes:
a core control group signal 311 comprising control signals or status signals sent and received by the RISC-V instruction set processor 11 to the soft-core coprocessor 21;
instruction register set signals 312, including instruction signals and received response signals sent by the RISC-V instruction set processor 11 to the soft-core coprocessor 21; the method comprises the steps of carrying out a first treatment on the surface of the
A memory bank signal 313 comprising data signals sent and received by the cache of the RISC-V instruction set processor 11 to the soft-core coprocessor 21;
custom group signal 314 includes custom instruction signals and received response signals sent by the RISC-V instruction set processor 11 to the soft-core coprocessor 21.
Specifically, the present embodiment divides the coprocessor interface into four sets of signals: the kernel control group (Core Control Group) is responsible for transferring control and status signals of the processor core, coordinating the operation between the main processor and the coprocessor, for example, if the RISC-V instruction set processor wants to send an operation status, the kernel status information may be sent to the coprocessor through the kernel control group signal interface unit 311, and similarly, the coprocessor may also send a co-kernel_status signal to the RISC-V instruction set processor.
The instruction register set (Command Register Group) is responsible for transferring instruction information from the main processor to the coprocessor and response information from the coprocessor to the main processor, such as the value of the source register, instruction content, etc.; a Memory Group (Memory Group) is responsible for transferring data between the coprocessor and the Cache (main processor); custom groups (Custom groups) are responsible for passing information needed by other coprocessors. For different coprocessors, there may be different signal lines in the custom set, which may include, for example, a TileLink bus, a floating point arithmetic unit (FPU) signal line, a Control Status Register (CSR) signal line, a page table translator (Page Table Walker) signal line, and so forth.
Specifically, referring to fig. 4, fig. 4 is a specific example diagram of a first interface signal of an integrated circuit computing device provided by an embodiment of the present invention, where a kernel control group (Core Control Group) includes a core_status signal reflecting a state of a main kernel, a core_id signal reflecting an ID of a sub-core when the main kernel is a multi-core processor, a core_exceptions signal reflecting an exception request of the main kernel, a co-core_status signal reflecting a state of a coprocessor, and a co-core_resp signal reflecting an interrupt request of the coprocessor. The instruction register set (Command Register Group) includes a request signal cmd_req and a response signal cmd_resp. The Memory Group (Memory Group) includes a request signal mem_req and a response signal mem_resp. The signals shown by the dashed lines in the figure are Custom groups (Custom groups) including CSR request signals csr_req and response signals csr_resp, FPU request signals FPU_req and response signals FPU_resp, PTW request signals PTW_req and response signals PTW_resp, tile Link bus request signals TL_req and response signals TL_resp. Of course, the present embodiment is not limited to the specific control signals described above, and the art can set the corresponding custom signals according to the specific implementation scenario under the condition of knowing the architecture of the present application.
In one embodiment, the apparatus further comprises:
a first debug port 14 connected to the first processing module 1 and a second debug port 25 connected to the second processing module 2.
In a specific embodiment, the first processing module 1 further includes: a first test access interface 15 connects said RISC-V instruction set processor 11 and said first debug port 14.
In a specific embodiment, the first test access interface 15 is a JTAG interface.
In one embodiment, the second processing module 2 includes:
the device comprises a programmable logic gate array 22, a configuration block 23 and a second test access interface 24, wherein the programmable logic gate array 22 is connected with the configuration block 23, the configuration block 23 is connected with the second test access interface 24, and the second test access interface 24 is connected with the second debug port 25.
In a specific embodiment, the second test access interface 24 is a JTAG interface.
In a specific embodiment, the first bus interface protocol includes AMBA protocol or TileLink protocol.
In one embodiment, RISC-V instruction set processor 11 includes CPU, GPU, DSP or a hardware accelerator.
Embodiments of the present invention also provide a computing processing system comprising a host, and further comprising the above-described integrated circuit computing device coupled to the host.
In one application scenario, the host is coupled to the debug port 23 of the FPGA chip via a wire. After the FPGA is powered on, the host computer uses FPGA development software to write configuration data of the FPGA into the configuration block 23 through the test access interface 24, and the configuration block 23 rewrites the programmable logic of the FPGA into a state specified by the user using the configuration data. In addition, the host writes programs (instructions) to be executed by the RISC-V instruction set processor 11 to the memory unit 12 through the test access interface 15. The program to be executed here may be a complex program such as floating point operation and signal processing, or may be a simple program for controlling the peripheral expansion unit 13. The RISC-V instruction set processor 11 can be a special processor which is designed, optimized and adjusted for a specific program, and can ensure lower power consumption and cost while efficiently completing various control or calculation functions required by a user.
After the configuration of the configuration block 23 and the writing to the memory unit 12 are completed, the RISC-V instruction set processor 11 will read the instruction stored in the memory unit 12 and execute the instruction, and when the instruction is a custom instruction, the instruction is sent to the soft-core coprocessor 21 through the first interface 31 for execution, so as to improve the computing efficiency. The various control or computing functions required by the user will be implemented by the RISC-V instruction set processor 11 alone, or by the RISC-V instruction set processor 11 in conjunction with the programmable logic gate array 22, depending on the actual situation.
In summary, the embodiment of the invention designs the soft core coprocessor in the programmable part of the FPGA chip by embedding the RISC-V architecture hard core processor in the FPGA chip, and the coprocessor can help the RISC-V processor hard core to realize the standard expansion instruction set and the custom expansion instruction of the RISC-V instruction set, so that the FPGA chip developer can flexibly adjust the processor core according to the needs, thereby enhancing the computing capability of the FPGA chip, ensuring small equipment area, low power consumption and low manufacturing cost.
Embodiments of the present invention also provide a computing processing system comprising a host, and further comprising the above-described integrated circuit computing device coupled to the host.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus (device), or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects all generally referred to herein as a "module" or "system. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. A computer program may be stored/distributed on a suitable medium supplied together with or as part of other hardware, but may also take other forms, such as via the Internet or other wired or wireless telecommunication systems.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (8)
1. An integrated circuit computing device, comprising:
the first processing module is used for receiving and processing RISC-V instruction set instructions, wherein the RISC-V instruction set instructions comprise basic instructions, extension instructions and custom instructions;
a first debug port connected to the first processing module and a second debug port connected to the second processing module;
the second processing module comprises a soft-core coprocessor, a programmable logic gate array, a configuration block and a second test access interface, wherein the programmable logic gate array is connected with the configuration block, the configuration block is connected with the second test access interface, the second test access interface is connected with the second debugging port, the programmable logic gate array comprises the soft-core coprocessor, and the soft-core coprocessor is realized in the form of an FPGA soft core; the soft core coprocessor is connected with the first processing module through a first interface and is used for processing the custom instruction sent by the first processing module; the second debug port is used for writing configuration data into the configuration block through the second test access interface; the configuration block is used for rewriting the programmable logic of the programmable logic gate array into a state designated by a user by using the configuration data;
a first bus connecting the first processing module and the second processing module; and
a first port connected to the first processing module and a second port connected to the second processing module.
2. The integrated circuit computing device of claim 1, wherein the first processing module comprises: RISC-V instruction set processor, memory unit, peripheral extension unit;
the RISC-V instruction set processor interconnects the memory unit and the peripheral expansion unit through a first bus, and is also connected with the soft core coprocessor through the first interface.
3. The integrated circuit computing device of claim 2, wherein the first interface comprises: a core control group signal comprising control signals or status signals sent and received by the RISC-V instruction set processor to the soft-core coprocessor;
an instruction register set signal comprising an instruction signal sent by the RISC-V instruction set processor to the soft-core coprocessor and a received response signal;
a memory bank signal comprising data signals sent and received by a cache of the RISC-V instruction set processor to the soft-core coprocessor;
the custom set signal comprises a custom instruction signal and a received response signal which are sent to the soft-core coprocessor by the RISC-V instruction set processor.
4. The integrated circuit computing device of claim 2, wherein the first processing module further comprises:
a first test access interface connecting said RISC-V instruction set processor and said first debug port.
5. The integrated circuit computing device of claim 1, wherein the second test access interface is a JTAG interface.
6. The integrated circuit computing device of claim 3, wherein the first bus interface protocol comprises an AMBA protocol or a TileLink protocol.
7. The integrated circuit computing device of claim 1, wherein the RISC-V instruction set processor comprises CPU, GPU, DSP or a hardware accelerator.
8. A computing processing system comprising a host, further comprising an integrated circuit computing device as recited in any of claims 1-7 coupled to the host.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010103240.XA CN111400986B (en) | 2020-02-19 | 2020-02-19 | Integrated circuit computing equipment and computing processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010103240.XA CN111400986B (en) | 2020-02-19 | 2020-02-19 | Integrated circuit computing equipment and computing processing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111400986A CN111400986A (en) | 2020-07-10 |
| CN111400986B true CN111400986B (en) | 2024-03-19 |
Family
ID=71430326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010103240.XA Active CN111400986B (en) | 2020-02-19 | 2020-02-19 | Integrated circuit computing equipment and computing processing system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111400986B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112015522B (en) * | 2020-11-02 | 2021-02-05 | 鹏城实验室 | System function expansion method, device and computer readable storage medium |
| CN112256330B (en) * | 2020-11-03 | 2021-11-09 | 中国人民解放军军事科学院国防科技创新研究院 | RISC-V instruction set extension method for accelerating digital signal processing |
| CN113467610A (en) * | 2021-05-28 | 2021-10-01 | 北京脑陆科技有限公司 | Architecture method, device, terminal and medium of brain-computer interface BCI (brain computer interface) equipment |
| CN113676164A (en) * | 2021-07-15 | 2021-11-19 | 深圳供电局有限公司 | Pulse modulation control system, device and method |
| CN114328370A (en) * | 2021-12-30 | 2022-04-12 | 苏州洪芯集成电路有限公司 | RISC-V based vision control heterogeneous soc chip architecture |
| CN114579288B (en) * | 2022-05-09 | 2022-09-02 | 成都登临科技有限公司 | Task processing method and device and computer equipment |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000046704A2 (en) * | 1999-02-05 | 2000-08-10 | Tensilica, Inc. | Automated processor generation system and method for designing a configurable processor |
| EP1443418A1 (en) * | 2003-01-31 | 2004-08-04 | STMicroelectronics S.r.l. | Architecture for reconfigurable digital signal processor |
| CN102831572A (en) * | 2011-06-17 | 2012-12-19 | 上海微电子装备有限公司 | System for collecting and processing image |
| CN103235717A (en) * | 2013-04-19 | 2013-08-07 | 中国科学院自动化研究所 | Processor with polymorphic instruction set architecture |
| CN104698941A (en) * | 2015-03-11 | 2015-06-10 | 南京大全自动化科技有限公司 | FPGA-based (field programmable gate array-based) embedded dual-core relay protecting system |
| CN109144573A (en) * | 2018-08-16 | 2019-01-04 | 胡振波 | Two-level pipeline framework based on RISC-V instruction set |
| CN109857460A (en) * | 2019-02-20 | 2019-06-07 | 南京华捷艾米软件科技有限公司 | Matrix convolution calculation method, interface, coprocessor and system based on RISC-V framework |
| KR101996842B1 (en) * | 2018-12-26 | 2019-07-08 | (주)자람테크놀로지 | RISC-V implemented processor with hardware acceleration supporting user defined instruction set and method therof |
| CN110490311A (en) * | 2019-07-08 | 2019-11-22 | 华南理工大学 | Convolutional neural networks accelerator and its control method based on RISC-V framework |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060179273A1 (en) * | 2005-02-09 | 2006-08-10 | Advanced Micro Devices, Inc. | Data processor adapted for efficient digital signal processing and method therefor |
-
2020
- 2020-02-19 CN CN202010103240.XA patent/CN111400986B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000046704A2 (en) * | 1999-02-05 | 2000-08-10 | Tensilica, Inc. | Automated processor generation system and method for designing a configurable processor |
| EP1443418A1 (en) * | 2003-01-31 | 2004-08-04 | STMicroelectronics S.r.l. | Architecture for reconfigurable digital signal processor |
| CN102831572A (en) * | 2011-06-17 | 2012-12-19 | 上海微电子装备有限公司 | System for collecting and processing image |
| CN103235717A (en) * | 2013-04-19 | 2013-08-07 | 中国科学院自动化研究所 | Processor with polymorphic instruction set architecture |
| CN104698941A (en) * | 2015-03-11 | 2015-06-10 | 南京大全自动化科技有限公司 | FPGA-based (field programmable gate array-based) embedded dual-core relay protecting system |
| CN109144573A (en) * | 2018-08-16 | 2019-01-04 | 胡振波 | Two-level pipeline framework based on RISC-V instruction set |
| KR101996842B1 (en) * | 2018-12-26 | 2019-07-08 | (주)자람테크놀로지 | RISC-V implemented processor with hardware acceleration supporting user defined instruction set and method therof |
| CN109857460A (en) * | 2019-02-20 | 2019-06-07 | 南京华捷艾米软件科技有限公司 | Matrix convolution calculation method, interface, coprocessor and system based on RISC-V framework |
| CN110490311A (en) * | 2019-07-08 | 2019-11-22 | 华南理工大学 | Convolutional neural networks accelerator and its control method based on RISC-V framework |
Non-Patent Citations (4)
| Title |
|---|
| RISC-V架构的开源处理器及SoC研究综述;雷思磊;;单片机与嵌入式***应用;20170201(第02期);全文 * |
| 基于FPGA的嵌入式ASIP软核设计与实现;李庆诚;任健;刘嘉欣;黄宝贞;;微计算机信息;20080515(第14期);全文 * |
| 基于Nios软核处理器的以太网接口设计;左震;邓黠;唐贵林;黄芝平;;计算机测量与控制;20090425(第04期);全文 * |
| 基于RISC结构的自定义接入网协议处理单元;刘付娥;葛宁;周祖成;;清华大学学报(自然科学版);20071015(第10期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111400986A (en) | 2020-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111400986B (en) | Integrated circuit computing equipment and computing processing system | |
| Cota et al. | An analysis of accelerator coupling in heterogeneous architectures | |
| US10037228B2 (en) | Efficient memory virtualization in multi-threaded processing units | |
| US10310973B2 (en) | Efficient memory virtualization in multi-threaded processing units | |
| TWI567646B (en) | Inter-architecture compatability module to allow code module of one architecture to use library module of another architecture | |
| US7827390B2 (en) | Microprocessor with private microcode RAM | |
| US8423682B2 (en) | Address space emulation | |
| US10169091B2 (en) | Efficient memory virtualization in multi-threaded processing units | |
| US10901492B1 (en) | Power reduction in processor pipeline by detecting zeros | |
| KR102611813B1 (en) | Coprocessors with bypass optimization, variable grid architecture, and fused vector operations | |
| CN108845826B (en) | Multi-register memory access instruction, processor, method and system | |
| EP2480985B1 (en) | Unified addressing and instructions for accessing parallel memory spaces | |
| CN113553209A (en) | Hardware apparatus and method for memory corruption detection | |
| CN109508206B (en) | Processor, method and system for mode dependent partial width loading of wider registers | |
| Yeh et al. | A fast cycle-accurate instruction set simulator based on QEMU and SystemC for SoC development | |
| CN104583959A (en) | Enabling virtualization of processor resource | |
| CN104603761A (en) | Concurrent control for a page miss handler | |
| KR20170066681A (en) | Handling of binary translated self modifying code and cross modifying code | |
| CN111209247A (en) | Integrated circuit computing device and computing processing system | |
| US8578387B1 (en) | Dynamic load balancing of instructions for execution by heterogeneous processing engines | |
| US11810618B2 (en) | Extended memory communication | |
| CN114610394A (en) | Instruction scheduling method, processing circuit and electronic equipment | |
| US20090063881A1 (en) | Low-overhead/power-saving processor synchronization mechanism, and applications thereof | |
| JP2024523339A (en) | Providing atomicity for composite operations using near-memory computing | |
| CN112559037B (en) | Instruction execution method, unit, device and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |