WO2000039893A1 - Antenne en reseau a elements en phase et procede de fabrication - Google Patents

Antenne en reseau a elements en phase et procede de fabrication Download PDF

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Publication number
WO2000039893A1
WO2000039893A1 PCT/JP1999/006516 JP9906516W WO0039893A1 WO 2000039893 A1 WO2000039893 A1 WO 2000039893A1 JP 9906516 W JP9906516 W JP 9906516W WO 0039893 A1 WO0039893 A1 WO 0039893A1
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WO
WIPO (PCT)
Prior art keywords
array antenna
phased array
layer
phase
phase control
Prior art date
Application number
PCT/JP1999/006516
Other languages
English (en)
Japanese (ja)
Inventor
Tsunehisa Marumoto
Ryuichi Iwata
Youichi Ara
Hideki Kusamitu
Kenichiro Suzuki
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Publication of WO2000039893A1 publication Critical patent/WO2000039893A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/0006—Particular feeding systems
    • H01Q21/0025—Modular arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/0087—Apparatus or processes specially adapted for manufacturing antenna arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H01Q21/065—Patch antenna array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
    • H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture

Definitions

  • the present invention relates to a phased array antenna used for transmitting and receiving high-frequency signals such as microwaves and millimeter waves, and adjusting a beam radiation direction by controlling a phase supplied to each radiating element.
  • phased array antenna consisting of a large number of radiating elements arranged in an array has been proposed as an on-board satellite tracking antenna or a satellite-mounted antenna.
  • This type of phased array antenna has the function of arbitrarily changing the beam direction by electronically changing the phase fed to each radiating element.
  • phase shifter is used as a means for changing the feeding phase of each radiating element.
  • a phase shifter a digital phase shifter composed of a plurality of phase shift circuits each having a fixed different phase shift amount (hereinafter, the digital phase shifter is simply referred to as a phase shifter) is used. You.
  • Each phase shift circuit is on / off controlled by a 1-bit digital control signal, and the phase shift amount of each phase shift circuit is combined to provide a power supply phase of 0 ° to 360 ° for the entire phase shifter. Is obtained.
  • phased array antennas use a large number of semiconductor devices such as PIN diodes and GaAs FETs as switching elements in each phase shift circuit, and many drive circuit components for driving these devices. .
  • the Ka band (approximately 20 GHz or higher) It is necessary to realize an antenna applicable in a high frequency band.
  • an antenna for a low-Earth orbit satellite tracking terminal (ground station) for example, frequency: 30 GHz,
  • Beam scanning range 50 ° beam tilt angle from the front
  • Opening area about 0.13 m 2 (36 O mm X 36 O mm)
  • the phase shift circuit used for each phase shifter must be 4 bits (minimum bit).
  • the phase shifter is preferably 22.5 °) or more.
  • the total number of radiating elements and the number of phase shift circuit bits used for the phased array antenna satisfying the above conditions are:
  • the spacing between the radiating elements must be around 5 mm, but in the conventional technology, the width of the wiring bundle is large. Too physical to be physically located.
  • the present invention has been made to solve such a problem, and an object of the present invention is to provide a phased array antenna having a high gain and applicable to a high frequency band. Disclosure of the invention
  • a phased array antenna comprises a radiating element and a phase control means formed in separate radiating element layers and a phase control layer, respectively, to form a multilayer structure.
  • a micro machine switch is used as a switching element used in the phase shift circuit.
  • the area occupied by the switching element Can be reduced as compared with the conventional case.
  • one phase shift unit can be configured with a relatively small area, a large number of radiating elements can be arranged in units of thousands in optimal intervals (about 5 mm) for high-frequency signals of about 30 GHz, resulting in high gain.
  • a fused array antenna applicable to a high frequency band can be realized.
  • each phase shift means which is repeatedly formed is mounted on a first substrate, and this is mounted on a second substrate on which a phase control layer is formed.
  • FIG. 1 is a block diagram of a phased array antenna according to one embodiment of the present invention.
  • FIG. 2 is an explanatory diagram showing a configuration example of a multilayer substrate.
  • FIG. 3 is a block diagram showing a phase shift unit.
  • FIG. 4 is a timing chart showing the operation of the phase control unit.
  • FIG. 5 is a diagram illustrating a configuration example of the present invention using a radial waveguide.
  • FIG. 6 is a diagram illustrating a configuration example of the present invention using a reflection-type space-fed phased array antenna.
  • FIG. 7 is a timing chart showing another operation of the phase control unit.
  • FIG. 8 is a perspective view showing a configuration example of the switch.
  • FIG. 9 is an explanatory diagram showing a bare chip mounting example.
  • FIG. 10 is an explanatory diagram showing an example of chip formation.
  • FIG. 11 is a circuit layout diagram showing the first embodiment.
  • FIG. 12 is a circuit layout diagram showing a configuration example inside the chip.
  • FIG. 13 is an explanatory diagram showing a configuration example of a pseudo coaxial line.
  • FIG. 14 is a circuit layout diagram showing the second embodiment.
  • FIG. 15 is a circuit layout diagram showing the third embodiment.
  • FIG. 16 is an explanatory diagram showing a configuration example of a pseudo slot.
  • FIG. 17 is a circuit layout diagram showing the fourth embodiment.
  • FIG. 18 is a diagram for explaining a configuration example of a conventional fused array antenna. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a block diagram of a phased array antenna 1 according to one embodiment of the present invention.
  • phased array antenna is used as a transmitting antenna for a high-frequency signal
  • the present invention is not limited to this. It is also possible to use. Further, when the entire antenna is composed of a plurality of subarrays, the present invention may be applied to the phased array antenna of each subarray.
  • FIG. 1 is a diagram for explaining the configuration of the phased array antenna 1.
  • a phased array antenna 1 is composed of a multilayer substrate 2 on which a radiating element and a phase control circuit are mounted on a multilayer substrate, a power supply 13 for supplying high-frequency power to the multilayer substrate 2, and a multilayer substrate 2 comprises a control device 11 for controlling the phase of each radiating element.
  • m X n (m and n are integers equal to or greater than 2) radiating elements 15 are arranged in an array, and the feed section 13 to the splitting / combining section 14 and the strip line 16 A ( The high-frequency signal is supplied via the (bold line in the figure).
  • the arrangement of the radiating elements 15 may be arranged in a rectangular lattice array or in another array such as a triangular array.
  • Each radiating element 15 is provided with a phase shifter 17.
  • phase shifter 17 provided for each radiating element 15 and a part of the strip line connected to the phase shifter 17 are collectively referred to as a phase shift unit 16.
  • a phase shift unit 16 a circuit portion repeatedly formed between the phase shift units 16 or within the same phase shift unit 16 is integrated and formed on another substrate to form a chip. And implemented in a phase control layer 35 described later.
  • FIG. 1 shows a case where the entire phase shift unit 16 is formed into chips.
  • a small piece (first substrate) that is formed by forming a large number of identical or similar unit circuits on a substrate by a semiconductor process or the like and then cutting out each unit is referred to as a base.
  • Devices that have been processed on the base for mounting and mounting on the second substrate) are called chips.
  • a chip is formed by cutting out a large number of circuits formed in a single unit or processing it for mounting and mounting it on another substrate (second substrate). Call.
  • the control device 11 is a device that calculates a feed phase shift amount of each radiation element 15 based on a desired beam radiation direction.
  • control signals 11 1 to 11 p one of these signals may be referred to as a control signal 11 i). It is distributed to drive units 1 and 2.
  • phase shift amount of q radiating elements is serially input to one drive unit 12.
  • pXq is basically the same as the total number of radiating elements mXn, but is a slightly larger number depending on the number of output terminals of the drive unit 12.
  • FIG. 2 is a block diagram of the drive unit 12.
  • Each drive unit 12 is composed of a data distribution unit 53 and q phase control units 54 provided for each phase shifter 17.
  • phase shift amount of q radiating elements is serially input to one driving unit 12.
  • the data distribution unit 53 distributes the phase shift amount of the q radiating elements 15 included in the control signal 11 i to the q phase control units 54 connected to the phase shifters 17 respectively. . Thereby, the phase shift amount of the corresponding radiating element 15 is set for each phase control unit 54.
  • the control device 11 outputs a trigger signal Trg, to each drive unit 12.
  • This trigger signal Trg is input to the phase control unit 54 of each drive unit 12 as shown in FIG.
  • the trigger signal T rg ′ is a signal that determines the timing for instructing and outputting the phase shift amount set in each phase control unit 54 to each phase shifter 17.
  • the controller 11 After setting the amount of phase shift for each phase control unit 54, the controller 11 outputs a pulse-like trigger signal T rg 'from the output of the controller 11 so that the amount of phase shift for power supply to each radiating element 15 Can be updated all at once, and the beam emission direction can be changed instantaneously.
  • phase shifter 17 provided for each radiating element 15 and the phase control unit 54 of the drive unit 12 will be described with reference to FIG.
  • FIG. 3 is a block diagram of the phase shifter 17 and the phase control unit 54.
  • phase shifter 17 is composed of four phase shift circuits 17A17D each having a different phase shift amount of 22.5 ° 45 ° 90 ° 180 °.
  • Each of the phase shift circuits 17A and 17D is connected to a strip line 16A for transmitting a radiating element 15 high-frequency signal from the distribution / combination unit 14.
  • each of the phase shift circuits 17A and 17D is provided with a switch 17S.
  • the phase control unit 54 for individually controlling the switches 17S of the phase shift circuits 17A 17D is composed of latches 55A 55D provided for each phase shift circuit 17A17D. .
  • the data distribution unit 53 of the drive unit 12 outputs a control signal 53A 53D to each of the latches 55A 55D constituting the phase control unit 54, thereby transferring the radiating element 15 to the phase control unit 54. Give phase amount.
  • control signal 53 A 53 D is input to the input D of each latch 55 A 55 D.
  • each latch 55A 55D is output from the controller 11 Trigger signal T rg ′ is input.
  • Each of the latches 55A to 55D latches the control signal 53A to 53D at the rising (or falling) edge of the pulse-like trigger signal Trg ', and the latches and the respective phase shifts.
  • the output Q (C nt) is output to the corresponding switch 17S of each of the phase shift circuits 17A to 17D via a drive line 19 for individually connecting the circuits.
  • phase shift amount of each of the phase shift circuits 17 A to 17 D is set, thereby setting the phase shift amount of the entire phase shifter 17, so that the high frequency signal propagating through the strip line 16 A is set. Is given a predetermined amount of phase shift.
  • the switch 17S may be sequentially switched by always outputting the trigger signal Trg ', that is, by always maintaining the H level (or the L level). In this case, since the phase shifters 17 are partially switched without being switched at the same time, instantaneous interruption of the radiation beam can be avoided.
  • a voltage amplifier or current amplifier should be provided on the output side of the latches 55A to 55D. You may.
  • FIG. 4 is an explanatory diagram showing the multilayer substrate unit 2, which shows a perspective view and a schematic cross-sectional view of each layer.
  • each of these layers is patterned by photolithography, etching, and printing techniques, and then laminated and integrated into multiple layers (first multilayer structure). Note that the stacking order of each layer is not necessarily limited to the form shown in Fig. 4.If the layers are deleted or added or the stacking order is partially changed according to the conditions of electrical and mechanical requirements The present invention is also effective.
  • a branch strip line 23 that distributes a high-frequency signal from the power supply unit 13 (not shown in FIG. 4) is formed.
  • the strip line 23 may be a tournament system that repeats two branches or a comb-shaped A series distribution method that gradually branches from the main line can be used.
  • a dielectric layer 38 A and a grounding layer 39 A made of a conductor are further provided outside the distribution / combination layer 39. Is added.
  • a bonding layer 37 (second bonding layer) is provided via a dielectric layer 38.
  • the coupling layer 37 is formed of a conductor pattern in which a hole, that is, a coupling slot 22 is formed in the ground plane.
  • phase control layer 35 is provided via a dielectric layer 36.
  • the phase control layer 35 is used to connect each phase shifter 17, a drive unit 12 for individually controlling the phase shifters 17, and each phase shifter 17 to the drive unit 12.
  • Drive lines 19 are provided.
  • the phase control layer 35 is connected to a plurality of wires.
  • a large number of drive lines 19 are provided in a layer different from the layer on which the phase shift unit 16 is mounted, that is, a wiring layer (internal wiring layer) inside the phase control layer 35. (Second multilayer structure).
  • phase control layer 35 a coupling layer 33 (first coupling layer) having a coupling slot 21 similar to the coupling layer 37 is provided via a dielectric layer 34. ing. Above it, a radiating element layer 31 on which a radiating element 15 is formed via a dielectric layer 32 is provided.
  • a parasitic element layer 31A on which a parasitic element 15A is formed via a dielectric layer 31B is provided.
  • the parasitic element 15 A is added for widening the band, and may be configured as necessary.
  • the dielectric layers 31 B, 32, 38, 38 A are made of a low dielectric constant substrate having a relative dielectric constant of about 1 to 4, such as a printed circuit board, a glass substrate, or a foam material. Can be Further, these dielectric layers may be spaces (air layers).
  • a substrate having a relative dielectric constant of about 1 to 11 such as a printed board, a ceramic substrate, a glass substrate, or a foam material is used.
  • a space may be formed as the dielectric layer 34.
  • the layers constituting the multilayer substrate 2 are separately disassembled for the sake of simplicity, but the layers are adjacent to the dielectric layers 31B, 32, 34, 36, 38, 38A.
  • the layers to be formed, for example, the radiating element layer 31 and the coupling layer 33 can be realized by forming a pattern on one or both surfaces of the dielectric layer.
  • the dielectric layer does not necessarily need to be formed of a single material, and may have a configuration in which a plurality of materials are stacked.
  • the high-frequency signal from the power feeding section 13 (not shown in FIG. 2) , And propagates to the strip line of the phase control layer 35.
  • a predetermined feed phase shift amount is given by the phase shifter 17, and propagates to the radiating element 15 of the radiating element layer 31 via the coupling slot 21 of the coupling layer 33, and It is radiated from 15 to a predetermined beam direction.
  • each phase shift unit 16 that is, the phase shifter 17 provided for each radiation element 15, and the strip line connected to the phase shifter 17
  • the circuit section that is repeated between each phase shift unit 16 or within the same phase shift unit 16 is integrated and formed into a chip on another substrate, and then phased as chip 67. Implemented in control layer 35.
  • the phase control layer 35 is composed of a plurality of wiring layers (second multilayer structure), and the phase shift unit 16 is formed therein.
  • a drive line 19 for individually connecting the drive unit 12 and each phase shift controller 18 is arranged on a wiring layer different from the wiring layer.
  • the number of drive lines 19 for controlling each phase shifter 17 can be reduced from the layer on which the phase shift unit 16 is formed, and the area required for these wirings can be greatly reduced.
  • the radiating element 15 and the phase shift unit 16 are formed on separate radiating element layers 31 and phase control layers 35, respectively.
  • a multilayer structure (first multilayer structure) was adopted.
  • the distributing / combining unit 14 is formed in a separate distributing / combining layer 39, and the phase control layer 35 and the distributing / combining layer 39 are connected by a connecting layer 37, so that the whole has a multilayer structure.
  • the area occupied by the radiating element 15 and the distributing / combining section 14 on the phase control layer 35 can be reduced, and the occupied area per radiating element can be reduced.
  • one phase shift unit 16 can be configured with a relatively small area in this manner, for example, for a high-frequency signal of about 3 OGHz, each radiating element In this case, a phased array antenna having a high gain and applicable to a high frequency band can be realized.
  • the beam scanning angle at which the grating lobe occurs is widened, so that the beam can be scanned over a wide range centering on the front of the antenna.
  • a distributed constant line such as a triplate type, a coplanar waveguide type, or a slot type can be used in addition to the microstrip type.
  • a printed dipole antenna, a slot antenna, an aperture element, and the like can be used as the radiating element 15. Particularly, by increasing the opening of the slot 21 in the coupling layer 33, the slot antenna can be used.
  • the radiating element layer 31 is also used as the coupling layer 33, and the radiating element layer 31 and the parasitic element layer 31A become unnecessary.
  • the strip line 16 A of the phase control layer 35 is used instead of the coupling slot 21, the strip line 16 A of the phase control layer 35 is used.
  • a high-frequency signal may be coupled using a conductive feed pin connecting the radiating element 15 and the radiating element 15.
  • a conductive feed pin provided to project from the strip line of the phase control layer 35 into the dielectric layer 38 via a hole provided in the coupling layer 37 is used. High frequency signals may be combined.
  • the same function as that of the distribution / combination layer 39 can also be realized by using a radial waveguide.
  • FIG. 5 is an explanatory diagram showing a configuration example of the present invention when a radial waveguide is used.
  • the distribution / synthesis function is realized by the dielectric layer 38, the ground layer 39A, and the probe 25 of the multilayer substrate unit 2 shown in FIG. Layer 39 is not required.
  • the dielectric layer 38 is composed of a printed circuit board, a foaming agent, or a space (air layer).
  • ground layer 39A a copper foil on a printed circuit board may be used as it is, or a metal plate or a metal housing surrounding the entire side surface of the dielectric 38 may be separately provided.
  • the present invention is applicable to a space-fed phased array antenna.
  • Fig. 6 shows a configuration example of a reflection-type space-fed phased array antenna.
  • the phased array antenna 1 shown in FIG. 6 is composed of a radiation feed section 27 composed of a feed section 13 and a primary radiating section 26, a multilayer board section 2, and a control device 11 (not shown).
  • the multilayer substrate 2 is different from the embodiment shown in FIG. 4, and is composed of a radiating element layer 31, a dielectric layer 32, a coupling layer 33, a dielectric layer 34, and a phase control layer 35. ing. Further, since the function of the distribution / combination unit 14 shown in FIG. 1 is realized by the primary radiation unit 26, the distribution / combination layer 39 is excluded from the multilayer substrate unit 2.
  • phased array antenna 1 the high-frequency signal radiated from the radiation feeder 27 is received once by each radiating element 15 on the radiating element layer 31, and Each is coupled to a phase shift unit 16 on a phase control layer 35 via 3.
  • the high-frequency signal is phase-controlled by each phase shift unit 16, propagates again to each radiating element 15 via the coupling layer 33, and has a predetermined beam direction from each radiating element 15. Is radiated.
  • the present invention is also effective in a form in which the multilayer distribution board 39 does not include the combined distribution layer 39 as in the space-fed phased array antenna described above.
  • phase control layer 35 Next, a configuration example of the phase control layer 35 will be described with reference to FIG.
  • FIG. 7 is an explanatory diagram schematically showing the arrangement of the phase control layer 35. As shown in FIG.
  • phase control layer 35 In the multilayer structure region of the phase control layer 35, a number of phase shifters 17 are arranged in an array, and further, a wiring pattern of the drive line 19 is formed.
  • a plurality of drive units 12 each composed of a flip chip 51 are arranged outside the multilayer structure region of the phase control layer 35.
  • the flip chip 51 is a chip that is bonded (that is, face-down bonded) using connection terminals provided on a chip or a substrate without using a lead wire such as a wire lead or a beam lead.
  • bumps 52 are formed as connection terminals on each of the chip electrodes, and the bumps 52 and the wiring of the phase control layer 35 are directly or differently connected.
  • the connection is made via an isotropic conductive sheet or the like.
  • the drive unit 12 is composed of the flip chip 51, the input electrode of the control signal 1 1 i to be input to the data distribution unit 53, and each latch constituting each phase control unit 54
  • the bumps 52 serving as the outputs Q of the latches 55 are connected to the phase shift circuits 17 A to 170 forming the phase shifter 17 by the drive lines 19 formed on the phase control layer 35. Connected individually to one.
  • the bumps 52 are formed not only on the periphery of the chip but also on the entire surface of the chip, the size of the chip does not necessarily increase even if the number of electrodes increases, and the mounting density of IC can be increased.
  • the number of radiating elements 15 must be increased in order to improve antenna gain. Therefore, even if the total number of bits of the phase shifter 17 to be controlled increases, the drive unit 12 for driving the phase shifter 17 is constituted by the flip chip 51, so that the phased array antenna can be formed. Can be prevented from becoming larger.
  • the number of chips mounted on the phase control layer 35 can be reduced, the time required for disposing the chips at predetermined positions can be reduced, and the production lead time can be suppressed from being lengthened.
  • the number of radiating elements 15 was set to 50,000 to obtain a gain of 36 dBi, and each phase shift was performed to increase the beam scanning step. Assuming that four bits are provided for the phase shift circuit used in the shifter 17, the total number of phase shift circuit bits is 20000 bits.
  • each flip chip 51 is arranged on both sides of the phase control layer 35 in the column direction.
  • the flip chip 51 arranged on the left side controls the left half of each of the phase shifters 17 arranged in the row direction, and the flip chip 51 arranged on the right side The right half of each phase shifter 17 arranged in the direction is controlled.
  • the phase control layer 35 has a multilayer structure composed of a plurality of internal wiring layers, and each bump 52 of the flip chip 51 and each phase shift circuit 17 A to 1 A Each of the drive lines 19 for connecting to 7D is separately wired to each layer of the phase control layer 35.
  • the drive wire 19 formed on a different layer from the flip chip 51 or the phase shift circuit 17 A to 17 D is connected to the flip chip 51 or the phase shift circuit 17 A via a via hole formed in the substrate. Needless to say, it is connected to ⁇ 17D.
  • the maximum width of the bundle of the drive lines 19 is reduced, so that the area prepared for the drive lines 19 in the phase control layer 35 can be reduced.
  • the size of the phased array antenna can be reduced, and the spacing between the radiating elements 15 can be reduced, so that the range of the radiated beam can be expanded.
  • the number of the drive lines 19 is small or when the width of the drive lines 19 is reduced, all the drive lines 19 are formed into one layer without having to multiply the phase control layer 35. It can also be wired.
  • the bump type flip chip 51 has been described. Instead of forming the bump 52 on the chip, a bump is formed on the substrate (here, the phase control layer 35) on which the flip chip 51 is mounted.
  • the flip chip 51 is mounted in the same manner as described above.
  • a multi-layered board build-up is formed by laminating a plurality of sheet-shaped boards on which a predetermined wiring pattern is formed. You can apply the method of making the substrate).
  • FIG. 8 is a perspective view showing a configuration example of the switch.
  • This switch is composed of a micromachine switch that short-circuits and opens the strip lines 62 and 63 with a contact (small contact portion) 64.
  • the micromachine switch mentioned here is a microswitch suitable for being integrated by a semiconductor device manufacturing process.
  • Strip lines 6 2 and 6 3 (having a height of about 1 ⁇ ) are formed on substrate 61 with a small gap, and contact 64 (height of about 2 ⁇ ) is formed above the gap. ) Are supported by a support member 65 so as to be able to freely contact and separate from the strip lines 62 and 63.
  • the distance between the lower surface of the contact 64 and the upper surfaces of the strip lines 62 and 63 is about 4 / m, and the height of the upper surface of the contact 64 with respect to the upper surface of the substrate 61, that is, The height of the entire micromachine switch is about 7 ⁇ .
  • a conductor electrode 66 (having a height of about 0.2 ⁇ ) is formed in the gap between the strip lines 62 and 63 on the substrate 61, and the height of the electrode 66 is It is lower than the height of the tracks 62, 63.
  • the electrode 66 has an output voltage of the drive circuit 19 ⁇ to 19 D (for example, 10 to 100 V Are supplied separately.
  • the contact 64 contacts both the strip lines 62 and 63 and the strip line 62 and 63 become conductive at a high frequency via the contact 64.
  • the output voltage of the drive circuit may be applied to the contact 64 via the support member 65 made of a conductor without applying a voltage to the electrode 66. can get.
  • the contact 64 has at least a lower surface formed of a conductor and makes ohmic contact with the strip lines 62 and 63, an insulator thin film is formed on the lower surface of the conductor member and the strip lines 62 and 63 are formed. 3, which may be capacitively coupled to 3.
  • the micromachine switch can freely move the contact 64 when the phase control layer 35 is provided in the multilayer substrate as in this phased array antenna. Space must be provided.
  • the micromachine switch is used as the switching element for controlling the power supply phase, so that power consumption at the semiconductor junction surface is reduced compared to when a semiconductor device such as a PIN diode is used, and power consumption is reduced. Can be reduced to about 1 / 10th.
  • FIGS. 9A and 9B are explanatory diagrams showing a configuration example in which the base chip 68 is flip-chip mounted.
  • FIG. 9A is a cross-sectional view of the chip 67 A
  • FIG. 9B is a top view of the chip 67 A
  • a cross-sectional view of a 7A face-down mounting example (adhesion method) is shown.
  • the range of the circuit included in the chip 67A can be various as described later with reference to FIG. 11, but in the following, the circuit portion shown in FIG. 11 (b), that is, the drive circuit and the switch The case of chip formation will be described as an example.
  • the bare chip 68 has a glass substrate 81 on which a switch 82A composed of a micromachine switch and a drive circuit 82B composed of a thin film transistor (TFT) are formed.
  • a switch 82A composed of a micromachine switch
  • a drive circuit 82B composed of a thin film transistor (TFT) are formed.
  • bumps 83 made of solder, gold, or the like are formed on signal connection pads to obtain a chip 67A.
  • FIG. 9 (c) shows a case where chip 67A is mounted face down on another substrate 84 by a soldering method or the like, and the signal connection whose periphery is covered with an insulating protective film 85A on the substrate 84 is shown. Pads 85 are formed.
  • the pad 85 and the bump 83 are fixed by solder or the like via the bump 85B and are electrically connected.
  • the height after the formation of the pad 85, the bump 85B, and the bump 83 is set to, for example, 10 // m, 20 ⁇ m, and 20 ⁇ m, the vicinity of the switch 82A where the movable portion exists is provided. After the final mounting, a space 87 with a height of 40 ⁇ is formed, and the micromachine switch operates stably.
  • the entire periphery or a part of the substrate 81 is fixed to the substrate 84 by the resin 86.
  • FIG. 9 (d) shows a case where the chip 67A is mounted face down on another substrate 84 by the bonding method, and the signal whose periphery is covered with the insulating protective film 85A on the substrate 84 is shown. A connection pad 85 is formed.
  • the glass substrate 81 and the substrate 84 are bonded via the adhesive 88, and the pad
  • the adhesive 88 is placed outside the mounting area of the switch 82A, The substrate 81 and the substrate 84 are bonded to each other.
  • the glass substrate 81 and the substrate 84 are bonded to each other over a relatively wide area by the adhesive 88, even if mechanical stress occurs on the substrate 84, the bonding portion of the bump 83 is protected. Is done.
  • the predetermined circuit portion including the switching element in the phase shift unit 16 is chipped and mounted on the phase control layer 35, so that the switching element can be mounted with a relatively simple configuration. it can.
  • a defect inspection can be performed on a single chip, and the yield of the entire device can be improved.
  • the bare chip is flip-chip mounted, the height required for the phase control layer 35 can be suppressed, and the coupling efficiency with the radiating element 15 coupled via the slot 21 can be improved.
  • an SMD Surface Mount Device
  • the number of assembly steps can be greatly reduced.
  • the phase shift unit 16 provided for each radiating element 15 includes a circuit portion that is used repeatedly. Exists.
  • the drive circuits 19A to 19D have the same circuit configuration.
  • the phase shift circuit 17A has a common circuit configuration for the phase shifters 17 provided for the respective radiating elements 15, and the same applies to the other phase shift circuits 17B to 17D.
  • FIG. 10 (a) shows an example in which two switches 17S used in each phase shift circuit are chipped.
  • two switches 73 constituting the switch 17S, a strip line 74 for supplying a high-frequency signal to the switch 73, and a pad 72 are provided.
  • FIG. 10 (b) shows an example in which chip shifting is performed in units of the phase shift circuits 17A to 17D.
  • the portion surrounded by the broken line in the figure corresponds to FIG. 10 (a).
  • the strip line 75 for connecting the switch 17S to the strip line 16A, and the strip line 75 A distributed constant line 76 and a main line 70 which are connected to the opposite side of the line and have lengths corresponding to the respective phase shift amounts are provided.
  • phase shift circuits 17 A to 17 D of each phase shift unit 16 can be shared by the individual phase shift circuits 17 A to 17 D of each phase shift unit 16.
  • FIG. 10 (c) shows an example in which all the phase shift circuits 17A to 17D in each phase shift unit 16 are chipped.
  • FIG. 10 (d) shows an example in which each phase shift unit 16 is formed into a chip.
  • each chip can be shared by each phase shift unit 16.
  • the predetermined circuit portion including the switching element in the phase shift unit 16 is formed into a chip and mounted on the phase control layer 35, so that a relatively simple configuration is used.
  • a switching element can be mounted.
  • a predetermined distributed constant line is branched and connected to the strip line 16A via a switch 17S, so that a rotated line type phase shift circuit for controlling the feed phase is provided.
  • the present invention is not limited to this, and other phase shift circuits such as a line switching type and a reflection type may be used.
  • each of the 22.5 °, 45 °, and 90 ° phase shift circuits 17 A to 17 C is configured as a loaded line type
  • the 180 ° phase shift circuit 1 7D is configured as a line switching type.
  • the micromachine switch is formed on the glass substrate as the switch 17S has been described above as an example with reference to FIGS. 9 and 10, but the substrate is not necessarily a glass substrate. Printed circuit boards and ceramic substrates are also acceptable.
  • a transistor circuit or a diode on a semiconductor substrate may be used instead of a micromachine switch.
  • first to fourth embodiments (configuration examples per radiating element) when the present invention is applied to a 3 OGHz phased array antenna. Will be described.
  • the phase shifter 17 is composed of four phase shift circuits 17 A to 17 D having different phase shift amounts of 22.5 °, 45 °, 90 °, and 180 °, respectively.
  • An example is described below.
  • phase shift circuit a micromachine switch is used as a switching element of the phase shift circuit.
  • FIG. 11 is a circuit layout diagram showing the first embodiment, (a) is a circuit layout diagram of a phase control layer showing the entire phase shift unit, and (b) is a schematic diagram showing a multilayer structure.
  • the phase shift unit 16 is provided corresponding to each of the radiation elements 15 arranged in an array, and has a substantially square (5 mm X 5 mm) area. (See the dashed square in the figure).
  • phase shift circuits of 22.5 °, 45 °, 90 °, and 180 ° are arranged, respectively.
  • phase shift circuits A part of these phase shift circuits is mounted on a chip 67 as a chip.
  • a circular radiating element 15 (2.5 mm to 4 mm in diameter) (thin broken line in the figure) is arranged.
  • FIGS. 12A and 12B are circuit layout diagrams showing respective chips used in the first and second embodiments.
  • FIG. 12A shows a chip used in a 22.5 °, 45 °, and 90 ° phase shift circuit
  • FIG. Indicates a chip used in a 180 ° phase shift circuit.
  • Fig. 12 (a) can be shared for a rotated line type phase shift circuit
  • Fig. 12 (b) can be shared for a line switching type phase shift circuit
  • FIG. 11 (b) shows a multilayer structure according to the first embodiment, and the same parts as those in FIG. 2 are denoted by the same reference numerals.
  • FIG. 11 This figure schematically shows the multilayer structure, and does not show the specific cross section of FIG. 11 (a).
  • the multilayer structure in this embodiment is composed of a ground layer 39A, a dielectric layer 38 (thickness l mm) forming a radial waveguide, a coupling layer 37, and a dielectric layer in order from the bottom to the top in FIG. 36 (0.2 mm thickness), phase control layer 35 (1 mm thickness), dielectric layer 34 (0.2 mm thickness), coupling layer 3 3 with coupling slot 21 formed,
  • the dielectric layer 32 (thickness 0.3 mm), the radiating element layer 31, the dielectric layer 31B (thickness lmm), and the parasitic element layer 31A are laminated.
  • the phase control layer 35 is a multilayer wiring including a plurality of wiring layers and dielectric layers, that is, a wiring layer 45 and a plurality of internal wiring layers 44 A in order from bottom to top. It consists of layer 44, wiring layer 43, dielectric layer 42, and chip mounting layer 41 on which chip 67 is mounted.
  • the wiring layer 43 is formed with a ground conductor for electrically separating the high-frequency circuit on the chip mounting layer 41 from the drive line 19 in the internal wiring layer 44A. ing.
  • the drive line 19 from the drive unit 12 is formed in the internal wiring layer 44A in the multilayer wiring layer 44, and the chip 67 on the chip mounting layer 41 via the via hole 36B, namely The phase shift circuit is connected to 17 A to 17 D.
  • the multilayer wiring layer 44 for example, a build-up substrate in which a sheet-like thin substrate on which a wiring layer is formed may be used.
  • the dielectric layer 34 between the phase control layer 35 and the coupling layer 33 is composed of a space secured by a spacer 34 A having a thickness (height) of 0.2 mm.
  • a chip 67 is mounted on the chip mounting layer 44 on the surface of the phase control layer 35.
  • the spacer 34 A may be arranged at the lower part of the slot 21, so that the lower part of the slot 21, which is usually an empty area, is arranged at the area where the spacer 34 A is arranged.
  • the area occupied by the spacer 34 A can be reduced.
  • the spacer 34 A if a material having a high dielectric constant, such as alumina, having a relative dielectric constant of about 5 to 30 is used as the spacer 34 A, the slot 21 and the strip line 16 A on the phase control layer 35 are formed. Combined efficiently.
  • a material having a high dielectric constant such as alumina, having a relative dielectric constant of about 5 to 30 is used as the spacer 34 A, the slot 21 and the strip line 16 A on the phase control layer 35 are formed. Combined efficiently.
  • a coupling means having the same function as a coaxial line (hereinafter referred to as a coupling means).
  • a pseudo-coaxial line 46 is used as a coupling means.
  • the quasi-coaxial line 46 has a via hole 16 B through which a high-frequency signal flows, and a via hole 1 A plurality of via holes 16D of the ground potential are arranged around them to shield the high-frequency signal flowing through 6B.
  • the via hole 16 D is connected to the ground plane of the coupling layer 37 and the wiring layer 43, respectively.
  • the wiring layer 45, the strip line 1 6 C power s connected to the via hole 1 6 B, are routed to above the coupling slot 22 of the coupling layer 37.
  • FIG. 13 is an explanatory diagram showing a configuration example of a pseudo coaxial line.
  • Fig. 13 (a) shows the wiring pattern on the chip mounting layer 41 on the surface of the phase control layer 35 and the wiring layer 45.
  • the strip line 16A or 16C is connected to the via hole 16B. I have.
  • FIG. 13 (b) schematically showing a cross section A—A ′, six shielding via holes 16D are arranged at approximately equal intervals around a via hole 16B through which a high-frequency signal flows.
  • FIG. 13C shows a pattern on the wiring layer 43.
  • the wiring layer 43 is used as a ground conductor, and the ground plane 43A is formed in this layer.
  • each via hole 16D is connected to the ground plane 43A and also to the ground plane 37A on the coupling layer 37, and The potential is maintained.
  • a pattern 16E may be provided in the internal wiring layer 44A, and the via holes 16D may be connected by the pattern 16E. By doing so, the shielding effect of the via hole 16D is improved.
  • FIGS. 14A and 14B are circuit layout diagrams showing a second embodiment.
  • FIG. 14A is a circuit layout diagram of a phase control layer showing the entire phase shift unit
  • FIG. 14B is a schematic diagram showing a multilayer structure.
  • the dielectric layer 34, the phase control layer 35, and the dielectric layer 36 are configured to be upside down from the first embodiment shown in FIG. 11, and the phase control layer 35
  • the wiring layers 45, the multilayer wiring layer 44, the wiring layer 43, the dielectric layer 42, and the chip mounting layer 41 are also arranged upside down.
  • the chip 67 is mounted from the chip mounting layer 41 on the surface of the phase control layer 35 to the dielectric layer 34 below it.
  • a spacer 34B made of a conductor is used as the spacer for forming the dielectric layer 34, instead of the spacer 34A having a high dielectric constant.
  • the spacer 34B may be disposed below the via hole 42A so as to be electrically connected to a ground pattern, for example, the ground plane 43A of the wiring layer 43.
  • FIG. 15 is a circuit layout diagram showing the third embodiment, (a) is a circuit layout diagram of a phase control layer showing the entire phase shift unit, and (b) is a schematic diagram showing a multilayer structure.
  • the dielectric layer 34 is constituted by a dielectric substrate 34C.
  • a cavity (space) 34 S having a height of 0.2 mm is formed at the position of the chip 67 mounted on the phase control layer 35, and the substrate density is increased.
  • the chip 6 7 during wearing is housed in Kiyabiti 3 4 in S
  • machining by cutting the surface of the substrate 34C with a router or machining by providing a through hole by die cutting may be used.
  • the resin in the cavity 34S portion may be peeled off by exposure and development treatment, and various forming methods can be used.
  • the wiring layers 45 on the surface of the multilayer wiring layer 44 are used as the coupling layers 37 to integrate these layers formed separately in the first embodiment.
  • the necessary dielectric layer 36 and strip line 16 C are deleted.
  • coupling means having the same function as the coupling slot (hereinafter, simply referred to as pseudo slot) 4 7 is used.
  • the pseudo slot 47 is constituted by a plurality of via holes 16F of the ground potential arranged around the coupling slot 22.
  • via holes 16F are stacked one layer below the ground plane 37A of the coupling layer 37 provided with the coupling slot 22 and the chip mounting layer 41 on which the stripline 16A is formed. Connected to the ground plane 43 A of the wiring layer 43.
  • the conductor pattern is excluded from the area surrounded by the via hole 16F.
  • the region surrounded by 6F is formed of the dielectric in the multilayer wiring layer 44.
  • FIG. 16 is an explanatory diagram showing a configuration example of a pseudo-slot.
  • FIG. 16 (a) shows a wiring pattern on the chip mounting layer 41, and a strip line 16 A is arranged above a via hole 16 F terminated by the wiring layer 43.
  • FIG. 16 (b) which schematically shows a cross section ⁇ ⁇ ⁇ ', 12 shield via holes 16 F are almost equal around the coupling slot 22 of the coupling layer 37 (wiring layer 45). They are arranged at intervals.
  • Fig. 16 (c) shows the wiring patterns on the wiring layer 43 and the bonding layer 37 (wiring layer 45) .Each via hole 16F has a ground plane 43A or a ground plane 37A. It is connected.
  • a pattern 16 G may be provided in the internal wiring layer 44 A, and the via holes 16 F may be connected by the pattern 16 G. By doing so, the shielding effect of the via hole 16F is improved.
  • FIG. 17 is a circuit layout diagram showing the fourth embodiment, (a) is a circuit layout diagram of a phase shift control layer showing the entire phase shift unit, and (b) is a schematic diagram showing a multilayer structure.
  • phase shift control layer 35 and the dielectric layer 36 are arranged upside down, and as in the third embodiment, the pseudo-coaxial line Instead, a pseudo slot 47 is used.
  • the present invention can be applied to a different stacking order from the embodiment shown in FIGS. 11 to 17.
  • the order of lamination is from top to bottom, and the phase control layer 35, the dielectric layer 36, the coupling layer 37, the dielectric layer 38, the distribution composite layer 39, the dielectric layer 38A, the coupling layer 33, the dielectric layer 32, and the radiating element layer 31, it is also possible to arrange the distribution / combination layer 39 on the inner layer and the phase control layer 35 on the outer layer.
  • a feed pin or a pseudo coaxial line between the distribution / combination layer 39 and the phase control layer 35 through a hole provided on the coupling layer 37 is used as a means for interlayer coupling of the high-frequency signal.
  • the connection may be made at a high frequency, and the phase control layer 35 and the radiating element 15 may be connected at a high frequency by a feed pin or a pseudo coaxial line penetrating the coupling layer 37 and the coupling layer 33.
  • phase control layer 35 By arranging the phase control layer 35 on the outside in this way, a multilayer structure can be realized regardless of the height of the chip 67.
  • the layer functioning as the distribution combining unit 14 can be omitted from the multilayer substrate portion 2.
  • the phased array antenna according to the present invention is an antenna having a high gain and applicable to a high frequency band, and is particularly useful for a satellite tracking vehicle antenna used for satellite communication, an antenna mounted on a satellite, and the like.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Waveguide Aerials (AREA)
  • Waveguide Switches, Polarizers, And Phase Shifters (AREA)

Abstract

Cette antenne en réseau à éléments en phase, peu coûteuse, est de taille relativement réduite même si le nombre d'éléments rayonnants a été multiplié pour accroître le gain. Elle est constituée d'une structure multicouche dont les couches sont pourvues d'un grand nombre d'éléments rayonnants (15) et de compensateurs de phase (16) déphasant, chacun, la phase d'un signal à haute fréquence émis/reçu par l'élément rayonnant correspondant. Elle comporte également un répartiteur/synthétiseur (14). La couche de commande de phase (35) est constituée d'autant de couches de câblage interne qu'il existe de lignes d'attaque nécessaires (19) et un câblage de signal commandant chaque compensateur de phase (16) est monté sur la couche de câblage interne. De la sorte, la superficie occupée par les câblages est réduite de même que les intervalles existant entre les éléments. Les circuits montés de manière répétitive dans les compensateurs de phase sont constitués de microplaquettes faisant partie intégrante d'une autre carte.
PCT/JP1999/006516 1998-12-24 1999-11-22 Antenne en reseau a elements en phase et procede de fabrication WO2000039893A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10/368194 1998-12-24
JP10368194A JP2000196331A (ja) 1998-12-24 1998-12-24 フェーズドアレイアンテナおよびその製造方法

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WO2000039893A1 true WO2000039893A1 (fr) 2000-07-06

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Cited By (5)

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WO2003049231A1 (fr) * 2001-12-05 2003-06-12 The Boeing Company Systeme d'antenne reseau a commande de phase
NL1026104C2 (nl) * 2004-05-03 2005-11-07 Thales Nederland Bv Meerlaagse PWB stralende schakeling en fasegestuurd antennestelsel waarin deze wordt toegepast.
US7443354B2 (en) 2005-08-09 2008-10-28 The Boeing Company Compliant, internally cooled antenna apparatus and method
DE112009003646T5 (de) 2008-12-08 2012-10-11 Omron Healthcare Co., Ltd. Elektronisches Blutdruckmessgerät
US8503941B2 (en) 2008-02-21 2013-08-06 The Boeing Company System and method for optimized unmanned vehicle communication using telemetry

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KR100523068B1 (ko) * 2002-02-09 2005-10-24 장애인표준사업장비클시스템 주식회사 통합형 능동 안테나
US7038625B1 (en) * 2005-01-14 2006-05-02 Harris Corporation Array antenna including a monolithic antenna feed assembly and related methods
JP4574635B2 (ja) * 2007-03-13 2010-11-04 日立マクセル株式会社 アンテナ及びその製造方法
US8706049B2 (en) 2008-12-31 2014-04-22 Intel Corporation Platform integrated phased array transmit/receive module
JP5417622B2 (ja) * 2009-08-19 2014-02-19 独立行政法人 宇宙航空研究開発機構 アナログ・デジタル積層型可変移相器
JP6712765B2 (ja) * 2016-05-31 2020-06-24 パナソニックＩｐマネジメント株式会社 高周波基板
JPWO2019187758A1 (ja) 2018-03-29 2021-02-12 日本電気株式会社 アレイアンテナ

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JPH01290301A (ja) * 1988-05-18 1989-11-22 Toyo Commun Equip Co Ltd フェーズド・アレイ・アンテナ
JPH0574008U (ja) * 1992-03-06 1993-10-08 日本無線株式会社 移相器のアクティブモジュール
JPH0591016U (ja) * 1992-05-14 1993-12-10 三菱電機株式会社 アンテナ制御用データ転送装置
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JPH1174717A (ja) * 1997-06-23 1999-03-16 Nec Corp フェーズドアレーアンテナ装置

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JPH01290301A (ja) * 1988-05-18 1989-11-22 Toyo Commun Equip Co Ltd フェーズド・アレイ・アンテナ
JPH0574008U (ja) * 1992-03-06 1993-10-08 日本無線株式会社 移相器のアクティブモジュール
JPH0591016U (ja) * 1992-05-14 1993-12-10 三菱電機株式会社 アンテナ制御用データ転送装置
JPH06267926A (ja) * 1993-03-12 1994-09-22 Canon Inc エッチング工程およびこれを用いた静電マイクロスイッチ
JPH1174717A (ja) * 1997-06-23 1999-03-16 Nec Corp フェーズドアレーアンテナ装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003049231A1 (fr) * 2001-12-05 2003-06-12 The Boeing Company Systeme d'antenne reseau a commande de phase
US6670930B2 (en) 2001-12-05 2003-12-30 The Boeing Company Antenna-integrated printed wiring board assembly for a phased array antenna system
NL1026104C2 (nl) * 2004-05-03 2005-11-07 Thales Nederland Bv Meerlaagse PWB stralende schakeling en fasegestuurd antennestelsel waarin deze wordt toegepast.
WO2005107014A1 (fr) * 2004-05-03 2005-11-10 Thales Nederland B.V. Dispositif rayonnant a tableau de connexions imprime multicouche et antenne reseau a commande de phase faisant appel audit dispositif
US7443354B2 (en) 2005-08-09 2008-10-28 The Boeing Company Compliant, internally cooled antenna apparatus and method
US8503941B2 (en) 2008-02-21 2013-08-06 The Boeing Company System and method for optimized unmanned vehicle communication using telemetry
DE112009003646T5 (de) 2008-12-08 2012-10-11 Omron Healthcare Co., Ltd. Elektronisches Blutdruckmessgerät

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