WO1999032924A1 - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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Publication number
WO1999032924A1
WO1999032924A1 PCT/JP1997/004719 JP9704719W WO9932924A1 WO 1999032924 A1 WO1999032924 A1 WO 1999032924A1 JP 9704719 W JP9704719 W JP 9704719W WO 9932924 A1 WO9932924 A1 WO 9932924A1
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WO
WIPO (PCT)
Prior art keywords
liquid crystal
crystal display
pair
film
electrode
Prior art date
Application number
PCT/JP1997/004719
Other languages
French (fr)
Japanese (ja)
Inventor
Masuyuki Ohta
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1997/004719 priority Critical patent/WO1999032924A1/en
Publication of WO1999032924A1 publication Critical patent/WO1999032924A1/en

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]

Definitions

  • the present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device used for a display device of a system that displays a moving image and requires high-quality video.
  • Liquid crystal display devices are widely used as display devices for portable devices typified by notebook computers because of their thin and lightweight characteristics.
  • active matrix type liquid crystal display devices using active elements typified by thin-film transistor elements (TFTs) have recently been used in desktop computers because of their high image quality comparable to a brown tube. It has begun to spread widely as display terminals for monitors and OA equipment.
  • liquid crystal display devices have specific disadvantages such as a narrow viewing angle and a slow response speed.
  • a display mode called an in-plane switching mode has been proposed as a method for improving the viewing angle, and the viewing angle is drastically improved.
  • Methods for improving the response speed include, for example, an optical compensatory bending (OCB) mode and a vertical alignment (VA) mode.
  • OBCB optical compensatory bending
  • VA vertical alignment
  • in-plane switching mode for example, see "R.Kiefer, B.Weber, F.W indcheidand G.Baur, isplay '9 2) pp. 5 4 7-5 5 0 ”, and for optical compensity bending mode (0CB), for example,“ T. U chidaand T. ⁇ i ⁇ as hita, Proceedings of The 2nd International Display Workshop (IDW'95) pp. 39-42, ⁇
  • For vertical alignment mode see, for example, Nikkei Microdevices, 1996. October issue, p 1 4 7 ”.
  • An object of the present invention is to solve the above-described problems.
  • An object of the present invention is to provide a wide viewing angle comparable to that of a Brownian tube, a high-speed response capable of responding to a moving image, and stable image quality for a long time.
  • An object of the present invention is to provide a highly reliable active matrix type liquid crystal display device which can be maintained at a high level.
  • the present invention provides, A pair of substrates, a liquid crystal composition having a positive dielectric anisotropy sandwiched between the pair of substrates, and an optical axis of liquid crystal molecules in the liquid crystal composition layer substantially without a voltage applied to the substrate surface when no voltage is applied.
  • An alignment control film that can be vertically aligned; a pair of electrode structures that generate an electric field in the liquid crystal composition layer that is substantially parallel to the substrate surfaces of the pair of substrates; an electric field component parallel to the substrate surface and one light transmission An angle with respect to the axis is about 45 degrees, and the other light transmission axis has a pair of polarizing plates arranged at one light transmission axis and about 90 degrees, and the liquid crystal composition layer is formed by the electric field. It is characterized by modulating the transmittance of light passing through the light.
  • a large number of scanning wirings, a large number of signal wirings, an active element formed at each intersection of the large number of scanning wirings and the large number of signal latitude lines is employed.
  • the semiconductor device includes the first configuration, a large number of scanning wirings, a large number of signal wirings, a thin film transistor element formed at a substantially intersection of the large number of scanning wirings and the large number of signal latitude lines.
  • the fourth configuration includes a pair of electrodes capable of generating an electric field substantially parallel to the substrate surfaces of the pair of substrates.
  • the fourth configuration includes the first configuration, and shields unnecessary light leakage portions to improve insulation.
  • the configuration has a black matrix.
  • a fifth configuration includes the first configuration, wherein a transparent conductive film is provided on at least one of the substrate surfaces of the pair of substrates opposite to the holding surface of the liquid crystal composition.
  • FIG. 1 is a sectional view showing the principle of the present invention.
  • FIG. 2 is a plan view showing the principle of the present invention.
  • FIG. 3 is a diagram showing the relationship between the direction of the applied electric field and the transmission axis of the polarizing plate according to the present invention.
  • FIG. 4 is a plan view of an essential part showing one pixel of a liquid crystal display portion of the active matrix type color liquid crystal display device according to the first embodiment of the present invention and its periphery.
  • FIG. 5 is a cross-sectional view of a pixel taken along section line 6-6 in FIG.
  • FIG. 6 is a cross-sectional view of the thin-film transistor element T FT along the 7-7 section line of FIG.
  • FIG. 7 is a cross-sectional view of the storage capacitor C stg at section line 8-8 in FIG.
  • FIG. 8 is a plan view for explaining the configuration of the matrix peripheral portion of the display panel.
  • Fig. 9 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.
  • FIG. 10 is a plan and cross-sectional view showing the vicinity of the connection between the gate terminal GTM and the gate wiring GL.
  • FIG. 11 is a plan and cross-sectional view showing the vicinity of the connection between the drain terminal DTM and the video signal line DL.
  • FIG. 12 is a plan and cross-sectional view showing the vicinity of a connection part of the common electrode terminal C TM 1, the common bus line CB 1, and the common voltage signal line CL.
  • FIG. 13 is a plan and cross-sectional view showing the vicinity of a connection portion of the common electrode terminal C TM2, the common bus line CB 2, and the common voltage signal line CL.
  • FIG. 14 is a circuit diagram of the active matrix type color liquid crystal display device of the present invention, including the matrix portion and its periphery.
  • FIG. 15 is the active matrix liquid of the present invention.
  • FIG. 6 is a diagram showing a driving waveform of the crystal display device.
  • FIG. 16 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes A to C on the substrate SUB1.
  • FIG. 17 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes D to E on the substrate SUB1.
  • FIG. 18 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process in a process G on the substrate SUB 1 side.
  • FIG. 19 is a top view showing a state where peripheral driving circuits are mounted on the liquid crystal display panel.
  • FIG. 20 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.
  • FIG. 21 is a cross-sectional view of a principal part showing a state where the tape carrier package TCP is connected to the scanning signal circuit terminal GTM of the liquid crystal display panel PNL.
  • FIG. 22 is an exploded perspective view of the liquid crystal display module.
  • FIG. 23 is a plan view of a principal part showing one pixel of the liquid crystal display section of the active matrix type color liquid crystal display device of the second embodiment of the present invention and the periphery thereof.
  • FIG. 24 is a plan view of a principal part showing one pixel of a liquid crystal display section of an active matrix type color liquid crystal display device according to a third embodiment of the present invention and the periphery thereof.
  • FIG. 1 and Fig. 2 show the principle diagram of the present invention.
  • Figure 1 FIG. 2 is a view of a cross section of a display portion of one pixel of the liquid crystal display device of the present invention as viewed from a direction parallel to the substrate surface, and
  • FIG. 2 is a view as viewed from a direction perpendicular to the substrate surface. 1 and FIG. 2 are not shown for simplicity of description.
  • the long axis (optical axis) of most liquid crystal molecules in the liquid crystal composition layer is perpendicular to the substrate surface when no electric field is applied.
  • the initial state is controlled by the alignment control film (orientation film) so that they are arranged in different directions. In this initial state, there is no birefringence phase difference for the incident light.
  • the transmittance T Z T of light passing through the display of the liquid crystal display device of the present invention is determined by the arrangement of the polarizing plate shown in FIG. Is as follows.
  • T / T. sin 2 (2 ⁇ ) sin 2 ( ⁇ n-d / ⁇ ).
  • T is the output light intensity
  • ⁇ Is the incident light intensity
  • X is the angle between the liquid crystal molecules and the optical axis (the effective optical axis of the liquid crystal layer) and the polarization transmission axis of the polarizer
  • s is the wavelength of the incident light
  • d is the distance between the substrates (the effective thickness of the liquid crystal layer)
  • 7 ⁇ is the pi.
  • ⁇ n of the liquid crystal layer is controlled by applying a voltage. Then, by changing the second term of Expression 1, the transmittance is controlled, and a desired display is obtained.
  • the optical axis of the liquid crystal molecules is parallel to the substrate surface, and exhibits the maximum refractive index anisotropy with respect to the incident light.
  • the product (retardation) of the refractive index anisotropy ⁇ n of the liquid crystal and the thickness d of the liquid crystal layer is defined as the lZ 2 of the wavelength ⁇ of the incident light (approximately 400 1111 to 70011111).
  • the point that the present invention differs from the conventional vertical alignment mode is that, in the present invention, an electrode configuration for applying an electric field substantially parallel to the substrate surfaces of the pair of substrates to the liquid crystal composition layer causes the lines of electric force to flow. Since the liquid crystal molecules are curved in a semicircle, the movements of the liquid crystal molecules are inevitably separated in two directions. This is not necessary, and the alignment stability, which has been a problem, is improved, and high reliability for maintaining high image quality for a long time can be obtained.
  • the second effect is that the liquid crystal molecules at the interface between the alignment film and the liquid crystal are Since the fixing force (anchoring) is small, the liquid crystal molecules are easy to move in the liquid crystal layer, so that the response speed is extremely high.
  • an electric field is applied to move the optical axis of the liquid crystal molecules in a direction parallel to the substrate surface in order to obtain a high transmittance state (white display). It is necessary to use a liquid crystal composition having a negative dielectric anisotropy ( ⁇ ⁇ 0) having a property of aligning the optical axis in a direction perpendicular to the substrate.
  • a liquid crystal composition having a positive dielectric anisotropy ⁇ > 0
  • the liquid crystal having dielectric anisotropy aligns the optical axis in the same direction as the electric field direction).
  • the fourth effect is that the direction of the applied electric field determines the direction of the optical axis of the liquid crystal molecules in a plane parallel to the substrate surface, so that the rubbing treatment or the like performed in the conventional vertical alignment mode is performed. It is not necessary to control the alignment direction at the same time. Thereby, the movement of the liquid crystal molecules due to the alignment regulating force can be improved, and the response speed can be further improved.
  • FIG. 4 is a plan view showing one pixel of the active matrix type color liquid crystal display device of the present invention and its periphery.
  • each pixel consists of a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode wiring), and two adjacent video signals.
  • the line (drain signal line or vertical signal line) is arranged in the intersection area with the DL (in the area surrounded by four signal lines).
  • Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode CT.
  • the scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL are arranged in the vertical direction.
  • the video signal lines DL extend in the up-down direction, and a plurality of video signal lines DL are arranged in the left-right direction.
  • the pixel electrode PX is electrically connected to the thin-film transistor TFT via the source electrode SD1, and the counter electrode CT is also electrically connected to the counter voltage signal line CL.
  • the pixel electrode PX and the counter electrode CT are opposed to each other, and the electric state of the liquid crystal composition LC is controlled by an electric field substantially parallel to the substrate surface generated between each pixel electrode PX and the counter electrode CT, and the display is performed. Control.
  • the pixel electrode PX and the counter electrode CT are formed in a comb-like shape, and each is a thin electrode extending upward and downward in the figure.
  • the counter electrode CT and the pixel electrode PX are alternately arranged, and the counter electrode CT is adjacent to the video signal line DL.
  • the electric field between the counter electrode CT and the pixel electrode PX is affected by the electric field generated from the video signal line DL.
  • unnecessary lines of electric force from the video signal line DL can be shielded by the counter electrode CT.
  • the counter electrode CT is different from the pixel electrode in that the potential is constantly supplied from the outside through the counter voltage signal line CL described later, so that the potential is stable, and the potential fluctuates almost even when adjacent to the video signal line DL. Absent. Therefore, unnecessary electric power lines from the video signal lines DL can be shielded. In addition, since the geometric position of the pixel electrode PX from the video signal line DL is farther away, the parasitic capacitance between the pixel electrode PX and the video signal line DL is greatly reduced, and the video signal of the pixel electrode potential Vs Fluctuation due to voltage can also be suppressed. Thus, it is possible to suppress crosstalk (improper image quality called vertical smear) occurring in the vertical direction.
  • crosstalk improper image quality called vertical smear
  • the electrode widths of the pixel electrode PX and the counter electrode CT are respectively 6 6 ⁇ .
  • the thickness is set to be sufficiently larger than 3.9 m of a liquid crystal composition layer described later. Desirably, the thickness is set to 1.5 times or more of the liquid crystal composition layer.
  • the video signal line DL is also 6 m.
  • the electrode width of the video signal line DL may be slightly wider than the pixel electrode PX and the counter electrode CT in order to prevent disconnection.
  • the electrode width of the video signal line DL is set to be less than twice the electrode width of the adjacent counter electrode CT.
  • the electrode width of the counter electrode CT adjacent to the video signal line DL is set to be equal to or more than 1 to 2 of the electrode width of the video signal line DL.
  • the unnecessary lines of electric force generated from the video signal line DL are absorbed by the counter electrodes CT on both sides, respectively.
  • the lines with the same width or more must be absorbed.
  • Electrode An electrode with a width is required. Therefore, since the lines of electric force generated from half (4 ⁇ m each) of the electrode of the video signal line DL need only be absorbed by the counter electrode CT on each side, the electrode of the counter electrode CT adjacent to the video signal line DL is required.
  • the width should be 1 Z 2 or more. This prevents crosstalk due to the effect of the video signal, and in particular, prevents vertical (vertical) crosstalk.
  • the width of the scanning signal line GL is set so as to satisfy a resistance value enough to transmit a scanning voltage sufficiently to the gate electrode GT of the terminal pixel (opposite to the scanning electrode terminal GTM described later).
  • a sufficient counter voltage is applied to the counter voltage signal line CL to the counter electrode CT of the pixel on the terminal side (the pixel farthest from the common bus lines CB 1 and CB 2 described later, that is, the pixel between CB 1 and CB 2).
  • the electrode spacing between the pixel electrode PX and the counter electrode CT changes depending on the liquid crystal material used. This is because the electric field intensity that achieves the maximum transmittance varies depending on the liquid crystal material, so the electrode spacing is set according to the liquid crystal material, and the signal voltage set by the withstand voltage of the video signal drive circuit (signal driver) used. This is so that the maximum transmittance can be obtained in the maximum amplitude range.
  • the electrode interval is 16 im. ⁇ Cross-sectional configuration of matrix part (pixel part) ⁇
  • FIG. 5 is a cross-sectional view of FIG. 4 taken along the line 6-6
  • FIG. 6 is a cross-sectional view of the thin film transistor TFT taken along the line 7-7 of FIG. 4
  • FIG. 7 is F. 4 is a diagram showing a cross section of the storage capacitor Cstg at the 8-8 cutting line of ig. 4.
  • FIG. 5 to Fig. 7 the lower transparent glass substrate SUB1 has a thin film transistor TFT, a storage capacitor Cstg and an electrode on the SUB1 side with respect to the liquid crystal composition layer LC. A group is formed, and a color filter FIL and a light blocking black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side.
  • alignment films AF 1 and AF 2 for controlling the initial alignment of the liquid crystal are provided on the inner surface (the liquid crystal LC side) of each of the transparent glass substrates SUB 1 and SUB 2.
  • a polarizing plate is provided on the outer surface of each of the sub 2 and the sub 2.
  • the thin-film transistor TFT When a positive bias is applied to the gate electrode GT, the thin-film transistor TFT operates such that the channel resistance between the source and the drain decreases, and when the bias is reduced to zero, the channel resistance increases. .
  • the thin-film transistor TFT has a gate electrode GT, an insulating film GI, an i-type (intrinsic, not doped with intrinsic ⁇ conductivity-type-determining impurities) amorphous silicon (S i), an i-type semiconductor layer AS, a pair of source electrodes SD 1, and a drain electrode SD 2.
  • the source and drain are originally determined by the bias polarity between them, and the polarity of the liquid crystal display device is reversed during operation, so that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.
  • the gate electrode GT is formed continuously with the scanning signal line GL, and is configured so that a part of the scanning signal line GL becomes the gate electrode GT.
  • Gate electrode GT exceeds the active area of thin-film transistor TFT Part.
  • the gate electrode GT is formed of a single conductive film g3.
  • a chromium-molybdenum alloy (Cr-Mo) film formed by using a spark is used, but not limited thereto.
  • the scanning signal line GL is formed of the conductive film g3.
  • the conductive film g3 of the scanning signal line GL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, and is integrally formed.
  • a gate voltage (scanning voltage) Vg is supplied from an external circuit to the gate electrode GT through the scanning signal line GL.
  • the conductive film g3 for example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used as the conductive film g3, for example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used.
  • the scanning signal lines GL and the gate electrodes GT are not limited to the chromium-molybdenum alloy, but may be made of, for example, aluminum or an aluminum alloy to reduce resistance. It may be a two-layer structure wrapped in ribden.
  • the part that intersects with the video signal line DL is made thinner to reduce the probability of a short circuit with the video signal line DL, and even if it is short-circuited, it can be separated by laser trimming. You may be bifurcated.
  • the counter voltage signal line CL is formed of the conductive film g3.
  • the conductive film g3 of the counter voltage signal line CL is formed in the same manufacturing process as the gate electrode GT, the scanning signal line GL, and the conductive film g3 of the counter electrode CT, and is electrically connected to the counter electrode CT. It is configured to be able to do so.
  • the counter voltage Vcom is supplied from an external circuit to the counter electrode CT through the counter voltage signal line CL.
  • the counter voltage signal line CL is not limited to the chromium-molybdenum alloy, but may be, for example, an aluminum alloy to reduce resistance. It may be a two-layer structure in which a chrome or aluminum alloy is wrapped with chromium-molybdenum.
  • the portion that intersects with the video signal line DL is made thinner to reduce the probability of short-circuit with the video signal line DL, and even if it is short-circuited, it can be separated by laser trimming. It may be forked.
  • the insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT.
  • the insulating film GI is formed above the gate electrode GT and the scanning signal line GL.
  • a silicon nitride film formed by plasma CVD is selected, and is formed to a thickness of 2000 to 450 persons (in this embodiment, about 350 A).
  • the insulating film GI also functions as an inter-layer insulating film of the scanning signal line GL, the counter voltage signal line CL, and the video signal line DL, and also contributes to their electrical insulation.
  • the i-type semiconductor layer AS is made of amorphous silicon and has a thickness of 150 to 250 A (in this embodiment, a thickness of about 1200 A).
  • the layer d0 is an N (+) type amorphous silicon semiconductor layer obtained by doping a phosphorus (P) for a common contact, and an i-type semiconductor layer AS exists on the lower side and an upper side on the upper side. It is left only where the conductive layer d3 is present.
  • the i-type semiconductor layer AS and the layer d0 are also provided between the scanning signal line GL and the intersection (crossover portion) between the counter voltage signal line CL and the video signal line DL.
  • the i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL at the intersection.
  • Each of the source electrode SD 1 and the drain electrode SD 2 is formed of a conductive film d3 that is in contact with the N (+) type semiconductor layer d0.
  • the conductive film d3 uses a chromium-molybdenum alloy (Cr—Mo) film formed by sputtering and has a thickness of 500 to 300 OA (in this embodiment, about 2 ⁇ 0 OA). ) Is formed. Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d O.
  • Cr—Mo chromium-molybdenum alloy
  • MoSi2, TiS refractory metal silicide
  • TaSi2, WSi2 refractory metal silicide
  • the video signal line DL is formed of a conductive film d3 of the same layer as the source electrode SD1 and the drain electrode SD2.
  • the video signal line DL is formed integrally with the drain electrode SD2.
  • the conductive film d3 uses a chromium-molybdenum alloy (Cr—Mo) film formed by sputtering, and has a thickness of 500 to 300 OA (in this example, , About 250 OA). Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d 0.
  • Cr—Mo chromium-molybdenum alloy
  • MoSi 2, Ti high melting point metal silicide
  • a film may be used, or a laminated structure with aluminum or the like may be used.
  • the conductive film d 3 is a thin film transistor TFT source electrode SD 2 portion In this case, it is formed so as to overlap the counter voltage signal line CL. As is clear from Fig. 7, this superposition is performed by using a storage capacitor (capacitance element) in which the source electrode SD 2 (d 3) is used as one electrode and the counter voltage signal CL is used as the other electrode.
  • the dielectric film of the storage capacitor C stg is composed of an insulating film GI used as a gate insulating film of the thin-film transistor TFT.
  • the storage capacitance C stg is formed in a part of the counter voltage signal line CL in plan view.
  • a protective film PSV1 is provided on the thin film transistor TFT.
  • the protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance.
  • the protective film PSV1 is formed of, for example, a silicon oxide film / silicon nitride film formed by a plasma CVD device, and has a thickness of about 0.1 to 1 m.
  • the protective film PSV1 is removed so as to expose the external connection terminals DTM and GTM.
  • the former is made thicker in consideration of the protective effect, and the latter is made thinner by the transconductance gm of the transistor.
  • through holes TH 2 and TH 1 are provided for electrical connection between the counter voltage signal line CL and a counter electrode CT described later, and for electrical connection between the source electrode SD 2 and the pixel electrode PX.
  • the protective film PSV1 and the insulating film GI are added together so that a hole up to the g3 layer is formed. A hole is made.
  • the protective film PSV 1 is made of a thick organic film such as polyimide. It may have a laminated structure with the object.
  • the pixel electrode PX is formed of the transparent conductive layer i1.
  • This transparent conductive film i1 is composed of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering, and has a thickness of 100 to 200 mm (in this embodiment, , About 140 people).
  • the pixel electrode ⁇ X is connected to the source electrode SD2 via the through hole ⁇ 1.
  • the transmitted light in that part improves the maximum transmittance when white display is performed, so that a brighter display is displayed than when the pixel electrode is opaque. It can be carried out.
  • the liquid crystal molecules maintain the initial alignment state, and the polarizing plate is arranged so as to display black in that state (normal black mode). Therefore, even if the pixel electrode is transparent, light of that part does not pass through, and high-quality black can be displayed. As a result, the maximum transmittance can be improved, and a sufficient contrast ratio can be achieved.
  • the counter electrode C is formed of the transparent conductive layer i1.
  • the transparent conductive film i1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering, and has a thickness of 100 to 200 A (in this embodiment, , About 140 people).
  • the common electrode CT is connected to the common voltage signal line CL via the through-hole # 2. As in the case of the pixel electrode ⁇ , by making the counter electrode transparent, the maximum transmittance when white display is performed is improved.
  • the counter electrode C ⁇ is configured so that a counter voltage V com is applied. I have.
  • the counter voltage Vcom turns off the thin-film transistor element TFT from an intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL.
  • Fi over Dosuru voltage delta V s min which occurred at the time of, if you want to decrease the power supply voltage of the integrated circuit to be used in the video signal driver circuit to approximately half, by applying an alternating voltage Good.
  • the transmitted light from unnecessary gaps is emitted to the display surface side so as not to lower the contrast ratio etc.
  • a light-shielding film BM (so-called black matrix) is formed on the surface.
  • the light shielding film BM also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched between the upper and lower light shielding films BM and the large gate electrode GT, and is exposed to external natural light or backlight light. It disappears.
  • the light-shielding film BM shown in FIG. 4 has a configuration extending linearly in the left-right direction above the thin-film transistor element TFT.
  • This pattern is an example, and the opening may be formed in a matrix shape with holes.
  • the display of that part corresponds to the video information in the pixel on a one-to-one basis, and is black in black and white in white. Therefore, it can be used as part of the display.
  • the counter electrode CT and the video signal The gap with the signal line DL is shielded from light by a second light-shielding layer SH formed in the same process as the gate electrode GT.
  • the light shielding in the vertical direction in the horizontal direction can be accurately shielded with the alignment accuracy of the TFT process, so that the boundary of the second light shielding layer S ⁇ between the electrodes of the counter electrode C ⁇ adjacent to the video signal line DL is formed. It can be set and the opening can be enlarged more than the light shielding by the light shielding film ⁇ which depends on the alignment accuracy of the upper and lower substrates.
  • the light-shielding film can be formed on the thin-film transistor substrate SUB1.
  • the opening can be further enlarged as compared with the light-shielding by the light-shielding film BM on the substrate SUB2 which depends on the accuracy of the upper and lower substrates.
  • the light-shielding film BM has a light-shielding property and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the counter electrode CT.
  • the organic pigment is mixed with a resist material to form a thickness of about 1.2 im.
  • carbon and titanium oxide (TixOy) can be maintained to improve the light shielding property, and 108 ⁇ cm or more, whose insulating property does not affect the electric field in the liquid crystal composition layer, can be maintained. It may be mixed within the range.
  • the second light-shielding layer SH has conductivity so as to easily absorb electric power from the video signal line.
  • the light-shielding film BM is linearly formed in the pixels in each row in the left-right direction, and the lines partition the effective display area in each row. Therefore, the outline of the pixels in each row is made clear by the light-shielding film BM. That is, the light shielding film BM has two functions of black matrix and light shielding for the i-type semiconductor layer AS.
  • the light-shielding film BM is also formed in a frame shape at the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG.
  • the light-shielding film BM in the peripheral portion is extended outside the seal portion SL to prevent leakage light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion and to prevent the light from leaking. It also prevents light such as light from leaking out of the display area.
  • the light-shielding film BM is retained about 0.3 to 1.0 mm inside the edge of the substrate SUB2, and is formed so as to avoid the cut region of the substrate SUB2.
  • the color filter FIL is formed in a stripe shape by repeating red, green, and blue at a position facing the pixel.
  • the color filter FIL is formed so as to overlap the edge portion of the double light shielding film SH.
  • the color filter FIL can be formed as follows. First, a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed base material is dyed with a red pigment and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process. A dye may be used for dyeing.
  • a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2
  • the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed base material is dyed with a red pigment and subjected to a fixing treatment to form a red filter R.
  • a green filter G and a blue filter B are sequentially formed by performing a similar process.
  • a dye may be used for dyeing.
  • the overcoat film 0C is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal composition layer LC, and to flatten the steps due to the color filter FIL and the light shielding film BM.
  • the overcoat film 0C is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin. Further, as the bar coat film C, an organic film such as polyimide having good fluidity may be used.
  • the liquid crystal layer, the alignment film, the polarizing plate, and the like will be described.
  • the dielectric anisotropy ⁇ £ is positive and its value is 13.2
  • the nematic liquid crystal is used.
  • the thickness (gap) of the liquid crystal composition layer is set to 3.8, and the retardation ⁇ ⁇ d is set to 0.31 m.
  • the value of this retardation ⁇ n ⁇ d (combination of refractive index anisotropy and gap) is between 0.25 ⁇ m and 0.35 ⁇ m, preferably between 0.35 ⁇ m and 0.35 ⁇ m.
  • the maximum transmittance can be obtained when the optical axes of the liquid crystal molecules are arranged in the direction of the electric field.
  • the thickness (gap) of the liquid crystal composition layer is controlled by polymer beads.
  • the liquid crystal material LC is not particularly limited.
  • the specific resistance of the liquid crystal composition 1 0 9 Q cm or more 1 0 1 4 ⁇ cm or less, preferably using the following 1 O ⁇ Q cm or more 1 0 1 3 Q cm.
  • the resistance of the liquid crystal composition is low, it is sufficiently retained child a voltage charged between the pixel electrode and the counter counter electrode, the lower limit 1 0 9 ⁇ cm, the preferred properly 1 O ⁇ Q cm. This is because the pixel electrode and the counter electrode are configured on the same substrate.
  • 1 0 1 4 Q cm or less preferred properly is 1 0 1 3 Q cm or less is good.
  • the alignment film AF for example, polyimide (JALS203) manufactured by Nippon Synthetic Rubber Co., Ltd. is used.
  • This alignment film has a hydrophobic group (eg, CH 3) on the surface, and the major axis (optical axis) of the liquid crystal molecules is arranged in a direction perpendicular to the substrate surface.
  • CH 3 hydrophobic group
  • the major axis (optical axis) of the liquid crystal molecules is arranged in a direction perpendicular to the substrate surface.
  • the polarizer POL a conductive polarizer is used, and the polarization transmission axis MAX1 of the lower polarizer POL1 is set to about the electric field application direction (the direction orthogonal to the longitudinal direction of the comb-teeth electrode). Set the angle to 45 degrees, and make the polarization transmission axis MAX2 of the upper deflector P0L2 perpendicular to it.
  • FIG. 3 shows the relationship. As a result, the display as shown in the operation can be performed, and the normally closed characteristic in which the transmittance increases as the applied voltage (the voltage between the pixel electrode PX and the counter electrode CT) increases. Can be obtained.
  • measures are taken against display failure and EMI caused by static electricity from the outside by imparting conductivity to the polarizing plate.
  • conductivity if only to measure the effects of static electricity, sheet resistance 1 0 8 ⁇ port below Nodea lever to measures against ⁇ ⁇ ⁇ , 1 0 4 ⁇ / mouth below It is desirable that Further, a conductive layer may be provided on the back surface (the surface on which the polarizing plate is adhered) of the sandwiching surface of the liquid crystal composition of the glass substrate. ⁇ Phase difference film ⁇
  • negative retardation films NRF1 and NRF2 were provided between the upper polarizing plate and the upper glass substrate and between the lower polarizing plate and the lower glass substrate, respectively. Further, between the upper polarizing plate and the upper glass substrate, a finer positive retardation film P RF was further provided.
  • either one of the negative retardation films may be used, and when only one is used, the retardation film is almost the same as the retardation of the liquid crystal layer. However, better black level can be obtained in all viewing angle directions by using two sheets.
  • the direction of n x is Ru is orthogonal to the slight inclination direction from the normal direction of the substrate surface of the optical axes of the liquid crystal molecules.
  • the horizontal direction is set. This compensates for birefringence due to a slight inclination of the substrate surface from the normal direction, and furthermore makes it possible to obtain a good black level in all viewing angle directions. Note that this is not necessary when the optical axis of the minute positive retardation film liquid crystal molecules exactly coincides with the normal direction of the substrate surface.
  • FIG. 8 is a diagram showing a plane of a main part around a matrix (AR) of a display panel PNL including upper and lower glass substrates SUB 1 and SUB 2.
  • FIG. 9 is a view showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.
  • the external connection terminal groups T g and T d and the terminal COT exist (the upper and left sides in the figure) are exposed on the upper substrate SUB 2 so that they are exposed.
  • the size is limited inside the lower substrate SUB1.
  • the terminal groups Tg and Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, and their lead-out wiring portions, which will be described later, are tape carrier packages TCP (Fig. 1) on which an integrated circuit chip CHI is mounted. 9, Fig. 20) is a group of multiple units.
  • the lead wiring from the matrix part of each group to the external connection terminal part is inclined as approaching both ends.
  • the counter electrode terminal COT is a terminal for applying a counter voltage to the counter electrode CT from an external circuit. Opposite voltage of matrix part
  • the signal line CL is drawn out to the opposite side (right side in the figure) of the scanning circuit terminal GTM, and the common voltage signal lines are grouped together by a common bus line CB and connected to the common electrode terminal COT.
  • a seal pattern SL is formed between the transparent glass substrates SUB1 and SUB2 along the edges of the transparent glass substrates SUB1 and SUB2 so as to seal the liquid crystal LC except for the liquid crystal inlet INJ.
  • the sealing material is made of, for example, an epoxy resin.
  • the layers of the alignment films ⁇ RI 1 and ⁇ RI 2 are formed inside the seal pattern SL.
  • the polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
  • the liquid crystal LC is sealed in a region partitioned by the seal pattern SL between the lower alignment film 0RI1 and the upper alignment film 0RI2 for setting the direction of the liquid crystal molecules.
  • the lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.
  • liquid crystal display device various layers are separately stacked on the lower transparent glass substrate SUB 1 side and the upper transparent glass substrate SUB 2 side, and a seal pattern SL is formed on the substrate SUB 2 side. It is assembled by superimposing the upper transparent glass substrate SUB2, injecting liquid crystal LC through the opening INJ of the sealing material SL, sealing the inlet INJ with epoxy resin, and cutting the upper and lower substrates.
  • FIG. 10 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, wherein FIG. 10 — A is a plane and FIG. 10 — B shows the cross section of the Fig. 10 — A cut at the B — B section line.
  • the figure corresponds to the vicinity of FIG. 8 below, and the diagonal wiring portion is represented by a straight line for convenience.
  • the Cr-Mo layer g3 is hatched for easy understanding.
  • the gate terminal G TM is a transparent conductive layer i for improving the reliability of the connection between the Cr-Mo layer g 3 and the surface of the Cr-Mo layer g 3 and the TCP (Tape Carrier Package). It consists of one and one.
  • the transparent conductive layer i1 uses a transparent conductive film IT # formed in the same step as the pixel electrode PX.
  • the insulating film GI and the protective film PSV1 are formed on the right side of the boundary line, and the terminal portion GTM located on the left end is exposed therefrom so that it can make electrical contact with an external circuit.
  • the terminal portion GTM located on the left end is exposed therefrom so that it can make electrical contact with an external circuit.
  • FIG. 8 In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, such pairs are arranged in a row at the top and bottom as shown in FIG. 8, and the terminal group T g (FIG. 8) is formed, and the left end of the gate terminal is extended beyond the cut area of the substrate in the manufacturing process and is short-circuited by the wiring SH g (not shown). This is useful for preventing electrostatic breakdown during rubbing of the alignment film ORI1 in the manufacturing process.
  • FIG. 11 is a diagram showing the connection from the video signal line DL to its external connection terminal DTM, FIG. 11 1 —A indicates the plane, and FIG. Ll — B indicates FIG. 1 Shows a cross section of 1 _ A at B-B section line. 8 corresponds to the vicinity of the upper right of FIG. 8 and the direction of the drawing is changed for convenience, but the right end corresponds to the upper end of the substrate SUB1.
  • TST d is a test terminal, which is not connected to an external circuit, but is wider than the wiring part so that probe needles can be contacted.
  • the drain terminal DTM is wider than the wiring part so that it can be connected to external circuits.
  • the external connection drain terminals DTM are arranged in the vertical direction, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and extend beyond the cutting line of the substrate SUB1. Further All of them are wired together to prevent electrostatic breakdown during the manufacturing process.
  • the inspection terminal TSTd is formed on every other video signal line DL as shown in FIG. 11.
  • the drain connection terminal DTM is formed of the transparent conductive layer i1, and is connected to the video signal line DL at a portion where the protective film PSVI is removed.
  • This transparent conductive film # 1 uses a transparent conductive film ITO formed in the same step as the pixel electrode ⁇ ⁇ , as in the case of the gate terminal GTM.
  • the lead-out wiring from the matrix part to the drain terminal part DTM has a layer d3 at the same level as the video signal line DL.
  • Fig. 1 2 is a diagram showing the connection from the counter voltage signal line CL to its external connection terminal CTM, Fig. 1 2 —A indicates the plane, and Fig. 1 2-B is F] '. g. 1 2 — Shows the cross section of A along the line B — B The figure corresponds to the vicinity of the upper left of FIG.
  • the common voltage signal lines CL are collectively connected to a common bus line CB1 and are led to a common electrode terminal CTM.
  • the common bus line CB has a structure in which a conductive layer 3 is laminated on a conductive layer g3 and they are electrically connected by a transparent conductive layer i1. This is to reduce the resistance of the common bus line CB so that the opposing voltage is sufficiently supplied from an external circuit to each opposing voltage signal line CL.
  • the feature of this structure is that the resistance of the common bus line can be reduced without any additional load on the conductive layer.
  • the counter electrode terminal CTM has a structure in which a transparent conductive layer i1 is laminated on a conductive layer g3.
  • This transparent conductive film i 1 uses the transparent conductive film IT 0 formed in the same process as the pixel electrode PX, as in the case of the other terminals.
  • Transparent conductive layer i 1 protects its surface and prevents electrolytic corrosion Therefore, the conductive layer g3 is covered with a transparent conductive layer il having high durability.
  • the connection between the transparent conductive layer i 1 and the conductive layer g 3 and the conductive layer d 3 is formed by forming through holes in the protective film PSV 1 and the insulating film GI to establish conduction.
  • FIG. 13 is a diagram showing the connection from the other end of the counter voltage signal line CL to its external connection terminal CTM 2, and FIG. 13—A shows the plane, and FIG. 1 3 — B shows the cross section of Fig. 1 3 — A taken along section line B-B. The figure corresponds to the vicinity of the upper right in FIG. 5.
  • the common bus line CB2 the other end (gate terminal GTM side) of each counter voltage signal line CL is brought together to be drawn to the counter electrode terminal CTM2.
  • the difference from the common bus line CB1 is that the common bus line CB1 is formed of a conductive layer d3 and a transparent conductive layer i1 so as to be insulated from the scanning signal line GL. Insulation with the scanning signal line GL is performed by the insulating film GI.
  • Fig.14 shows the connection diagram of the equivalent circuit of the display matrix and its peripheral circuits. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement.
  • AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.
  • X represents a video signal line DL
  • suffixes G, B, and R are added corresponding to green, blue, and red pixels, respectively.
  • Y means the scanning signal line GL, and the subscripts 1, 2, 3,..., End are added according to the order of the scanning timing.
  • the scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.
  • SUP provides multiple divided and stabilized voltage sources from one voltage source. It is a circuit that includes a power supply circuit for obtaining the information and a circuit for exchanging information for the cathode ray tube (CRT) from the host (higher-level processing unit) with information for the TFT LCD.
  • CRT cathode ray tube
  • FIG. 15 shows a driving waveform of the liquid crystal display device of this embodiment.
  • the counter voltage Vc is a constant voltage. Scanning signal V g in each scanning period, takes on level, others take off level.
  • the video signal voltage is applied so that the positive and negative poles are inverted every frame and transmitted to one pixel with twice the amplitude of the voltage to be applied to the liquid crystal layer.
  • the polarity of the video signal voltage Vd is inverted every column, and the polarity is also inverted every two rows.
  • the pixels whose polarities are inverted are arranged vertically and horizontally, so that flicker and crosstalk (smear) can be suppressed.
  • the counter voltage Vc is set to a voltage which is a certain amount lower than the center voltage of the polarity inversion of the video signal voltage. This is to correct the feedthrough voltage generated when the thin film transistor element changes from ON to OFF, and is performed to apply an AC voltage having a small DC component to the liquid crystal. When a direct current is applied to a liquid crystal, afterimages, deterioration, and the like become severe.
  • the maximum amplitude of the video signal voltage can be reduced by converting the counter voltage into an alternating current, and a low withstand voltage signal can be used for the video signal drive circuit (signal-side driver).
  • the storage capacitor C stg is provided to store video information (after the thin-film transistor TFT is turned off) written to the pixel for a long time.
  • the method of applying an electric field parallel to the substrate surface used in the present invention unlike the method of applying an electric field perpendicular to the substrate surface, most of the capacitance (so-called liquid crystal capacitance) composed of the pixel electrode and the counter electrode is used.
  • No storage capacity C stg Cannot store video information in pixels. Therefore, in a system in which an electric field is applied in parallel with the substrate surface, the storage capacitance Cstg is an essential component.
  • the storage capacitor Cstg also works to reduce the influence of the gate potential change AVg on the pixel electrode potential Vs when the thin film transistor TFT switches. This situation is represented by the following equation.
  • V s ⁇ C gs / (C gs + C stg + C pix) ⁇ x ⁇ V g
  • C gs is a parasitic capacitance formed between the gate electrode GT of the thin-film transistor TFT and the source electrode SD 1
  • Cpix is a capacitance formed between the pixel electrode PX and the counter electrode CT.
  • AVs represents a so-called feed-through voltage corresponding to a change in pixel electrode potential due to AVg.
  • the change AVs causes a DC component applied to the liquid crystal LC, but the value can be reduced as the storage capacitance C stg is increased.
  • the reduction of the DC component applied to the liquid crystal LC improves the life of the liquid crystal LC, and reduces the so-called burn-in in which the previous image remains when switching the liquid crystal display screen.
  • the gate electrode GT is made large to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance is increased. C gs increases, and the pixel electrode potential Vs has an adverse effect of being easily affected by the gate (scan) signal Vg.
  • this disadvantage can be eliminated by providing the storage capacitor Cstg.
  • FIGS. 16 to 18 a method of manufacturing the above-described liquid crystal display device on the substrate SUB 1 side will be described with reference to FIGS. 16 to 18.
  • the middle letter is the abbreviation of the process name, and the left side is shown in Fig. 6.
  • the thin film transistor TFT part, the right side shows the processing flow viewed from the cross-sectional shape near the gate terminal shown in Fig. 10.
  • Processes A to I were classified according to each photographic process except process B and process D. All cross-sectional views of each process were completed after photographic process and the photo resist was removed. Shows the stages.
  • photographic processing refers to a series of operations from application of a photo resist, through selective exposure using a mask to development of the resist, and a repeated description is omitted. The following is an explanation according to the divided steps.
  • a conductive film g 3 made of Cr—Mo and having a thickness of 2000 is provided by sputtering. After the photographic processing, the conductive film g3 is selectively etched with ceric ammonium nitrate. Accordingly, the gate electrode GT, the scanning signal line GL, the counter voltage signal line C, the gate terminal GTM, the first conductive layer of the common bus line CB1, and the first conductive layer of the counter electrode terminal CTM1.
  • a bus line SH g (not shown) connecting the layer and the gate terminal GTM is formed.
  • Ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD apparatus, and a 350 OA-thick Si nitride film was provided.
  • silane gas and hydrogen gas are introduced into the plasma CVD apparatus, After an i-type amorphous Si film of 200 A is provided, hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus, and an N (+)-type amorphous Si film having a thickness of 30 OA is formed.
  • a membrane Provide a membrane.
  • an island of the i-type semiconductor layer AS is formed by selectively etching the N (+)-type amorphous Si film and the i-type amorphous Si film.
  • a conductive film d3 made of Cr having a thickness of 300 is formed by sputtering. After the photographic processing, the conductive film d3 is etched with the same liquid as in step A, and the first conductive layer of the video signal line DL, the source electrode SD1, the drain electrode SD2, the common bus line CB2, and the drain are formed. Form a bus line SH d (not shown) that shorts the terminal DTM. Next, the N (+)-type semiconductor layer between the source and the drain is etched by introducing CC14 and SF6 into the dry etching apparatus and etching the N (+)-type amorphous Si film. d O is selectively removed.
  • the N (+) type semiconductor layer dO is removed using the conductive film d3 as a mask.
  • the N (+)-type semiconductor layer d0 remaining on the i-type semiconductor layer AS portions other than the conductive film d1 and the conductive film d2 are removed by self-alignment.
  • the i-type semiconductor layer AS is also slightly etched at its surface, but the extent is the etching time. Can be controlled by
  • Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD device to provide a 0.4 // m thick nitrided Si film.
  • the passivation of the protective film PSV1 and the insulating film GI is performed by selectively etching the nitrided Si film using SF6 as a dry etching gas.
  • the protective film PSV1 and the insulating film GI are patterned with the same photomask and are processed collectively.
  • a transparent conductive film i1 composed of an IT0 film having a thickness of 1,400 people is provided by sputtering. After the photographic processing, the transparent conductive film i 1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, so that the top layer of the gate terminal GTM, the drain terminal DTM, and the counter electrode terminals CTM 1 and CTM A second conductive layer is formed.
  • FIG. 19 is a top view showing a state where the video signal drive circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.
  • TCP is the driving IC chip for driving the display panel PNL (the lower five driving IC chips on the vertical scanning circuit side, and each of the left ten driving IC chips on the video signal driving circuit side).
  • TCP is a carrier package in which the driving IC chip CHI is mounted by tape automated bonding (TAB).
  • TAB tape automated bonding
  • This is a drive circuit board on which TCPs, capacitors, etc. are mounted. It is divided into two parts, one for the video signal drive circuit and the other for the scan signal drive circuit.
  • FGP is a frame ground pad, and a spring-like fragment provided by cutting into the shield case SHD is soldered.
  • FC is a flat cable for electrically connecting the lower drive circuit board PCB1 to the left drive circuit board PCB1. As shown in the figure, the flat cable FC is made up of a striped polyethylene layer and a polyvinyl alcohol layer consisting of striped polyethylene (tin bronze material with Sn plating). Use the one that is supported by the switch.
  • FIG. 20 constitutes the scanning signal drive circuit V and the video signal drive circuit H
  • FIG. 21 shows a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI is mounted on a flexible wiring board
  • FIG. 21 shows the cross-sectional structure of a liquid crystal display panel, in this example, a scanning signal circuit terminal GT.
  • FIG. 4 is a cross-sectional view of a main part showing a state connected to M.
  • TTB is an input terminal and a wiring portion of the integrated circuit CHI
  • TTM is an output terminal and a wiring portion of the integrated circuit CHI.
  • the lead pad is connected to the bonding pad PAD of the integrated circuit CHI by the so-called phase-bonding method.
  • the outer ends of the terminals TTB and TTM correspond to the inputs and outputs of the semiconductor integrated circuit chip CHI, respectively.
  • CR TZT FT conversion circuits and power supply circuits Connected to the liquid crystal display panel PNL by ACF.
  • the package TCP is connected to the panel so that its tip covers the protective film PSV 1 exposing the connection terminal GTM on the panel PNL side.
  • the external connection terminal GTM (DTM) is connected to the protective film PSV 1 or the package. At least one side of TCP is covered, making it more resistant to touch.
  • B F 1 is a base film made of polyimide or the like
  • S R S is a solder resist film for masking so that solder does not adhere to unnecessary portions during soldering.
  • the gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by epoxy resin EPX, etc., and the silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 to multiplex protection. .
  • the driving circuit board PCB 2 has electronic components such as ICs, capacitors, and resistors mounted thereon.
  • This drive circuit board PCB 2 has one voltage source A power supply circuit for obtaining a plurality of divided and stabilized voltage sources from a computer, and a circuit for converting information for a CRT (cathode ray tube) from a host (high-level processing unit) to information for a TFT liquid crystal display A circuit SUP that includes is installed.
  • CJ is a connector connection part to which a connector (not shown) connected to the outside is connected.
  • the drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by a flat cable FC.
  • FIG. 22 is an exploded perspective view showing each component of the liquid crystal display module MDL.
  • SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide, RM is a reflection plate, and BL is a back plate.
  • the light fluorescent tube and LCA are backlight cases, and the components are stacked in a vertical arrangement as shown in the figure to assemble the module MDL.
  • the entire module MDL is fixed by claws and hooks provided on the shield case SHD.
  • the knock case LCA is configured to house the backlight fluorescent tube BL, light diffusion plate SPB light diffusion plate, light guide LCB, and reflection plate RM, and the battery case LCA is placed on the side of the light guide LCB.
  • the light from the fluorescent light tube BL is converted into a uniform backlight on the display surface by the light guide LCB, the reflector RM, and the light diffuser SPB, and emitted to the liquid crystal display panel PNL.
  • An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL, and serves as a power source for the backlight fluorescent tube BL.
  • FIG. 23 shows the active matrix type color liquid of this embodiment.
  • FIG. 2 is a plan view of a principal part showing one pixel of a liquid crystal display portion of a liquid crystal display device and its periphery.
  • the counter electrode CT is formed integrally with the counter electrode signal line CL.
  • Other configurations are the same as those of the first embodiment, and the effects of the present invention are also the same.
  • FIG. 24 is a plan view of a principal part showing one pixel of the liquid crystal display portion of the active matrix type color liquid crystal display device of this embodiment and the periphery thereof.
  • the counter electrode CT is formed integrally with the counter electrode signal line CL
  • the pixel electrode PX is formed integrally with the source electrode SD1.
  • Other configurations are the same as those of the first embodiment, and the effects of the present invention are also the same.
  • liquid crystal display device that can achieve a high contrast ratio, a wide viewing angle characteristic, and a high reliability that can maintain high image quality.
  • the present invention is applied to liquid crystal and the like as described above, and has practical application in the liquid crystal manufacturing industry.

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Abstract

A liquid crystal display which can materialize a wide angle of visibility and high-speed response of a cathode-ray tube quality, and has high picture quality and high reliability. This liquid crystal display has a pair of substrates, a liquid crystal composition which has positive anisotropy of dielectric constant, being caught by the pair of substrates, an alignment control film which can align the optical axes of almost all liquid crystal molecules within a liquid crystal composition layer toward the substrate face at the time of non-application of voltage, and a pair of electrodes which can apply an electric field in roughly parallel with the faces of the pair of substrates to the liquid crystal composition layer, and modulates the transmittivity of the light passing through the liquid crystal composition layer. Hereby, this liquid crystal display can provides a high contrast ratio and a wide angle of visibility feature, and maintain a high reliability and high picture quality compatibility. Moreover, at the same time, this liquid crystal display is extremely high in response speed and can be driven even at low voltage.

Description

明 細 書  Specification
液晶表示装置  Liquid crystal display
[技術分野]  [Technical field]
本発明は、 液晶表示装置に関し、 特に動画を表示し高画質の映像 が必要なシステムの表示デバイスに用いる。  The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device used for a display device of a system that displays a moving image and requires high-quality video.
[背景技術] [Background technology]
液晶表示装置は薄い、 軽量という特徴からノー トパソコ ンに代表 される携帯機器の表示装置と して広く普及している。 特に薄膜 トラ ンジス夕素子 （ T F T ) に代表される能動素子を用いたアクティ ブ マ ト リ クス型液晶表示装置は、 ブラウ ン管に匹敵する高画質という 点から、 最近では、 デスク ト ツプパソコ ンのモニタ一および O A機 器等の表示端末と して広く普及し始めている。 しかしながら、 液晶 表示装置には、 視野角が狭い、 応答速度が遅いという特有の欠点が 存在する。 これらを解決す手段と して、 例えば、 視野角を改善する 方法と して提案されているのが、 ィ ンプレーンスィ ツチングモ一 ド と呼ばれる表示モー ドであり、 視野角は抜本的に改善される。 また、 応答速度を改善させる方法としては、 例えば、 オプティ カルコ ンペ ンセーティ ドベンディ ング （ O C B ) モー ド、 垂直配向 （ V A ) モ ― ドがある。 これらに関しては、 ィ ンプレーンスィ ツチングモー ド に関しては、 例えば、 「 R . K i e f e r、 B . W e b e r、 F . W i n d c h e i d a n d G . B a u r、 P r o c e e d i n g s o f t h e T w e l f t h I n t e r n a t i o n a 1 D i s p l a y R e s e a r c h C o n f e r e n c e ( J a p a n D i s p l a y ' 9 2 ) p p . 5 4 7〜 5 5 0」、 オプティ カルコンペンセ一ティ ドベンディ ングモ一 ド （ 0 C B ) に 関しては、 例えば、 「 T . U c h i d a a n d T . Μ i ν a s h i t a、 P r o c e e d i n g s o f T h e 2 n d I n t e r n a t i o n a l D i s p l a y W o r k s h o p s ( I DW ' 9 5 ) p p . 3 9〜 4 2」 、 垂直配向モー ドに関し ては、 例えば、 「日経マイクロデバイス、 1 9 9 6年 1 0月号、 p 1 4 7」 がある。 Liquid crystal display devices are widely used as display devices for portable devices typified by notebook computers because of their thin and lightweight characteristics. In particular, active matrix type liquid crystal display devices using active elements typified by thin-film transistor elements (TFTs) have recently been used in desktop computers because of their high image quality comparable to a brown tube. It has begun to spread widely as display terminals for monitors and OA equipment. However, liquid crystal display devices have specific disadvantages such as a narrow viewing angle and a slow response speed. As a means for solving these problems, for example, a display mode called an in-plane switching mode has been proposed as a method for improving the viewing angle, and the viewing angle is drastically improved. Methods for improving the response speed include, for example, an optical compensatory bending (OCB) mode and a vertical alignment (VA) mode. Regarding these, in regard to the in-plane switching mode, for example, see "R.Kiefer, B.Weber, F.W indcheidand G.Baur, isplay '9 2) pp. 5 4 7-5 5 0 ”, and for optical compensity bending mode (0CB), for example,“ T. U chidaand T. Μ i ν as hita, Proceedings of The 2nd International Display Workshop (IDW'95) pp. 39-42, `` For vertical alignment mode, see, for example, Nikkei Microdevices, 1996. October issue, p 1 4 7 ”.
しかしながら、 上記イ ンプレーンスイ ッチングモー ドを利用する 液晶表示装置では、 応答速度が速いものでも 1 0 0 m s弱程度であ り、 動画表示を行うために必要とされる 4 0〜 2 0 m s以下の応答 速度には程遠く 、 動画表示を行った時に動画の残像が発生し、 画像 が彗星の様に尾を引いて流れるように見えるという問題がある。  However, in the liquid crystal display device using the above-mentioned in-plane switching mode, even if the response speed is fast, it is slightly less than 100 ms, and the response of 40 to 20 ms or less required for displaying moving images is required. It is far from the speed, and there is a problem that when displaying a moving image, the afterimage of the moving image occurs, and the image looks like a trailing trail like a comet.
一方、オプティ カルコ ンペンセーティ ドベンディ ングモー ドでは、 液晶のベン ド配向を実現させるのが、 極めて難しく、 実用化に至つ ていない。  On the other hand, in the optical compensatory bending mode, it is extremely difficult to realize the liquid crystal bend alignment, and it has not been put to practical use.
また、 垂直配向モー ドでは、 上下方向の視野角が悪く、 配向分割 技術を使わなければならず、 配向分割を施すために、 液晶分子のプ レチルトを 2方向にするような処理が必要で、 垂直配向の状態で、 2方向のプレチル卜の状態を安定に維持するこ とが難しく、 長時間 輝度均一性を維持できないという点で、 信頼性に問題があった。 本発明は上記の課題を解決するもので、 本発明の目的は、 ブラウ ン管並の広い視野角、 かつ、 動画に対応できる高速応答を有し、 か つ、 良好な画質を長時間安定的に維持できる高信頼性のアクティ ブ マ ト リ クス型液晶表示装置を提供するこ とにある。  In the vertical alignment mode, the viewing angle in the vertical direction is poor, and it is necessary to use an alignment division technique.In order to perform the alignment division, it is necessary to treat the liquid crystal molecules in two directions. In the vertical alignment state, it was difficult to stably maintain the pretilt state in two directions, and there was a problem in reliability in that luminance uniformity could not be maintained for a long time. An object of the present invention is to solve the above-described problems. An object of the present invention is to provide a wide viewing angle comparable to that of a Brownian tube, a high-speed response capable of responding to a moving image, and stable image quality for a long time. An object of the present invention is to provide a highly reliable active matrix type liquid crystal display device which can be maintained at a high level.
【発明の開示]  [Disclosure of the Invention]
本願によって開示される発明のう ち代表的なものの概要を以下に 述べる。  An outline of typical inventions disclosed by the present application is described below.
前記目的を達成するために、 本発明では、 第 1 の構成として、 一 対の基板と、 前記一対の基板に挟持された正の誘電率異方性を有す る液晶組成物と、 電圧無印加時に前記液晶組成物層中の液晶分子の 光軸を基板面に略垂直に配向させ得る配向制御膜と、 前記液晶組成 物層に前記一対の基板の基板面に略平行な電界を発生させる一対の 電極構造と、 前記基板面に平行な電界成分と一方の光透過軸との間 の角度が約 4 5度で、 他方の光透過軸が一方の光透過軸と約 9 0度 で配置される一対の偏光板とを有し、 前記電界で前記液晶組成物層 を透過する光の透過率を変調するこ とを特徴とする。 In order to achieve the above object, the present invention provides, A pair of substrates, a liquid crystal composition having a positive dielectric anisotropy sandwiched between the pair of substrates, and an optical axis of liquid crystal molecules in the liquid crystal composition layer substantially without a voltage applied to the substrate surface when no voltage is applied. An alignment control film that can be vertically aligned; a pair of electrode structures that generate an electric field in the liquid crystal composition layer that is substantially parallel to the substrate surfaces of the pair of substrates; an electric field component parallel to the substrate surface and one light transmission An angle with respect to the axis is about 45 degrees, and the other light transmission axis has a pair of polarizing plates arranged at one light transmission axis and about 90 degrees, and the liquid crystal composition layer is formed by the electric field. It is characterized by modulating the transmittance of light passing through the light.
第 2の構成として、 第 1 の構成を含み、 多数の走査配線と、 多数 の信号配線と、 前記多数の走査配線と前記多数の信号緯線に各々の 略交点に形成された能動素子と、 前記一対の基板の基板面に略平行 な電界を発生させ得る一対の電極を有する構成とする。  As a second configuration, including the first configuration, a large number of scanning wirings, a large number of signal wirings, an active element formed at each intersection of the large number of scanning wirings and the large number of signal latitude lines, A structure including a pair of electrodes capable of generating an electric field substantially parallel to the substrate surfaces of the pair of substrates is employed.
第 3の構成として、 第 1 の構成を含み、 多数の走査配線と、 多数 の信号配線と、 前記多数の走査配線と前記多数の信号緯線に各々の 略交点に形成された薄膜トラ ンジスタ素子と、 前記一対の基板の基 板面に略平行な電界を発生させ得る一対の電極を有する構成とする 第 4の構成として、 第 1 の構成を含み、 不要な光漏れ部分を遮光 し絶縁性を有するブラ ックマ ト リ クスを有する構成とする。  As a third configuration, the semiconductor device includes the first configuration, a large number of scanning wirings, a large number of signal wirings, a thin film transistor element formed at a substantially intersection of the large number of scanning wirings and the large number of signal latitude lines. The fourth configuration includes a pair of electrodes capable of generating an electric field substantially parallel to the substrate surfaces of the pair of substrates. The fourth configuration includes the first configuration, and shields unnecessary light leakage portions to improve insulation. The configuration has a black matrix.
第 5の構成として、 第 1 の構成を含み、 前記一対の基板の前記液 晶組成物の挟持面の反対側の基板面の少なく とも一方の基板面上に 透明導電膜を有する構成とする。  A fifth configuration includes the first configuration, wherein a transparent conductive film is provided on at least one of the substrate surfaces of the pair of substrates opposite to the holding surface of the liquid crystal composition.
[図面の簡単な説明]  [Brief description of drawings]
F i g . 1 は、 本発明の原理を示す断面図である。  FIG. 1 is a sectional view showing the principle of the present invention.
F i g . 2は、 本発明の原理を示す平面図である。  FIG. 2 is a plan view showing the principle of the present invention.
F i g . 3は、 本発明の印加電界方向、 偏光板透過軸の関係を示 す図である。 F i g . 4は、 本発明の第 1 の実施例のアクティ ブ . マ ト リ ッ ク ス型カラー液晶表示装置の液晶表示部の一画素とその周辺を示す要 部平面図である。 FIG. 3 is a diagram showing the relationship between the direction of the applied electric field and the transmission axis of the polarizing plate according to the present invention. FIG. 4 is a plan view of an essential part showing one pixel of a liquid crystal display portion of the active matrix type color liquid crystal display device according to the first embodiment of the present invention and its periphery.
F i g . 5は、 F i g . 4の 6 — 6切断線における画素の断面図 である。  FIG. 5 is a cross-sectional view of a pixel taken along section line 6-6 in FIG.
F i g . 6は、 F i g . 4の 7 — 7切断線における薄膜 トランジ スタ素子 T F Tの断面図である。  6 is a cross-sectional view of the thin-film transistor element T FT along the 7-7 section line of FIG.
F i g . 7は、 F i g . 4の 8 — 8切断線における蓄積容量 C stg の断面図である。  7 is a cross-sectional view of the storage capacitor C stg at section line 8-8 in FIG.
F i g . 8は、 表示パネルのマ ト リ クス周辺部の構成を説明する ための平面図である。  FIG. 8 is a plan view for explaining the configuration of the matrix peripheral portion of the display panel.
F i g · 9は、 左側に走査信号端子、 右側に外部接続端子の無い パネル縁部分を示す断面図である。  Fig. 9 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.
F i g . 1 0は、 ゲー ト端子 G TMとゲ一 ト配線 G Lの接続部近 辺を示す平面と断面の図である。  FIG. 10 is a plan and cross-sectional view showing the vicinity of the connection between the gate terminal GTM and the gate wiring GL.
F i g . 1 1 は、 ドレイ ン端子 D T Mと映像信号線 D L との接続 部付近を示す平面と断面の図である。  FIG. 11 is a plan and cross-sectional view showing the vicinity of the connection between the drain terminal DTM and the video signal line DL.
F i g . 1 2は、 共通電極端子 C TM 1 、 共通バスライ ン C B 1 および共通電圧信号線 C Lの接続部付近を示す平面と断面の図であ る。  FIG. 12 is a plan and cross-sectional view showing the vicinity of a connection part of the common electrode terminal C TM 1, the common bus line CB 1, and the common voltage signal line CL.
F i g . 1 3は、 共通電極端子 C TM 2、 共通バスライ ン C B 2 および共通電圧信号線 C Lの接続部付近を示す平面と断面の図であ る。  FIG. 13 is a plan and cross-sectional view showing the vicinity of a connection portion of the common electrode terminal C TM2, the common bus line CB 2, and the common voltage signal line CL.
F i g . 1 4は、 本発明のアクティブ ' マ ト リ ックス型カラ一液 晶表示装置のマ ト リ クス部とその周辺を含む回路図である。  FIG. 14 is a circuit diagram of the active matrix type color liquid crystal display device of the present invention, including the matrix portion and its periphery.
F i g . 1 5は、 本発明のアクティブ ' マ ト リ ックス型カラ一液 晶表示装置の駆動波形を示す図である。 Fig. 15 is the active matrix liquid of the present invention. FIG. 6 is a diagram showing a driving waveform of the crystal display device.
F i g . 1 6は、 基板 S U B 1側の工程 A〜 Cの製造工程を示す 画素部とゲー ト端子部の断面図のフローチヤ一 トである。  FIG. 16 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes A to C on the substrate SUB1.
F i g . 1 7は、 基板 S U B 1側の工程 D〜 Eの製造工程を示す 画素部とゲー ト端子部の断面図のフローチャー トである。  FIG. 17 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes D to E on the substrate SUB1.
F i g . 1 8は、 基板 S U B 1側の工程 Gの製造工程を示す画素 部とゲ一 ト端子部の断面図のフローチヤ一 卜である。  FIG. 18 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process in a process G on the substrate SUB 1 side.
F i g . 1 9は、 液晶表示パネルに周辺の駆動回路を実装した状 態を示す上面図である。  FIG. 19 is a top view showing a state where peripheral driving circuits are mounted on the liquid crystal display panel.
F i g . 2 0は、 駆動回路を構成する集積回路チップ C H I がフ レキシブル配線基板に搭載されたテープキャ リアパッケージ T C P の断面構造を示す図である。  FIG. 20 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.
F i g . 2 1 は、 テープキャ リアパッケージ T C Pを液晶表示パ ネル P N Lの走査信号回路用端子 G T Mに接続した状態を示す要部 断面図である。  FIG. 21 is a cross-sectional view of a principal part showing a state where the tape carrier package TCP is connected to the scanning signal circuit terminal GTM of the liquid crystal display panel PNL.
F i g . 2 2は、 液晶表示モジュールの分解斜視図である。  FIG. 22 is an exploded perspective view of the liquid crystal display module.
F i g . 2 3は、 本発明の第 2の実施例のアクティ ブ · マ ト リ ッ クス型カラー液晶表示装置の液晶表示部の一画素とその周辺を示す 要部平面図である。  FIG. 23 is a plan view of a principal part showing one pixel of the liquid crystal display section of the active matrix type color liquid crystal display device of the second embodiment of the present invention and the periphery thereof.
F i g . 2 4は、 本発明の第 3の実施例のアクティブ ' マ ト リ ツ クス型カラー液晶表示装置の液晶表示部の一画素とその周辺を示す 要部平面図である。  FIG. 24 is a plan view of a principal part showing one pixel of a liquid crystal display section of an active matrix type color liquid crystal display device according to a third embodiment of the present invention and the periphery thereof.
[発明を実施するための最良の形態]  [Best Mode for Carrying Out the Invention]
本発明をより詳細に説述するために、 添付図面に従ってこれを説 明する。  The present invention will be described in more detail with reference to the accompanying drawings.
F i g . 1 , F i g . 2に本発明の原理図を示す。 F i g . 1 は 本発明の液晶表示装置の 1つの画素の表示部の断面を、 基板面に平 行な方向から見た図であり、 F i g . 2は基板面に垂直な方向から 見た図である。 なお、 F i g . 1 . F i g . 2説明の簡略化のため に、 T F T等の素子は省略している。 Fig. 1 and Fig. 2 show the principle diagram of the present invention. Figure 1 FIG. 2 is a view of a cross section of a display portion of one pixel of the liquid crystal display device of the present invention as viewed from a direction parallel to the substrate surface, and FIG. 2 is a view as viewed from a direction perpendicular to the substrate surface. 1 and FIG. 2 are not shown for simplicity of description.
F i g . 1 — a、 F i g . 2 — a に示すように、 本発明では、 電 界無印加時に液晶組成物層の中の殆どの液晶分子の長軸 （光軸） を 基板面に垂直な方向に配列するように配向制御膜 （配向膜） で初期 状態を制御する。 この初期状態では、 入射光に対して複屈折位相差 が発生しない。  As shown in FIG. 1—a and FIG. 2—a, in the present invention, the long axis (optical axis) of most liquid crystal molecules in the liquid crystal composition layer is perpendicular to the substrate surface when no electric field is applied. The initial state is controlled by the alignment control film (orientation film) so that they are arranged in different directions. In this initial state, there is no birefringence phase difference for the incident light.
この液晶組成物層に基板に形成された櫛歯電極により基板面に 平行な電界を印加するこ とにより、 F i g . 1 - b , F i g . 2 — bの様に液晶分子の長軸を基板面に平行な方向に配列させる。 これ により液晶組成物中を通過する光に対し複屈折位相差が発生し、 光 が変調される。 ここで、 F i g . 3に示す偏光板の配置により、 本 発明の液晶表示装置の表示を通過する光の透過率 T Z T。は、 以下 のよう になる。  By applying an electric field parallel to the substrate surface to the liquid crystal composition layer with a comb-shaped electrode formed on the substrate, the long axis of the liquid crystal molecules is changed as in FIG. 1-b and FIG. 2—b. They are arranged in a direction parallel to the substrate surface. As a result, a birefringent phase difference is generated for light passing through the liquid crystal composition, and the light is modulated. Here, the transmittance T Z T of light passing through the display of the liquid crystal display device of the present invention is determined by the arrangement of the polarizing plate shown in FIG. Is as follows.
T / T。 = s i n 2 ( 2 χ ) s i n 2 ( Δ n - d / λ ) … （式T / T. = sin 2 (2 χ) sin 2 (Δ n-d / λ)… (expression
1) 1)
ここで、 Tは出射光強度、 Τ。は入射光強度、 Xは液晶分子と光 軸 （液晶層の実効的光軸） と偏光板の偏光透過軸とのなす角、 Δ η は液晶層の屈折率異方性 （ Δ η = η ε— η。） 、 スは入射光の波長、 dは基板間の間隔 （液晶層の実効的厚み） 、 7Γは円周率を表す。 Here, T is the output light intensity, Τ. Is the incident light intensity, X is the angle between the liquid crystal molecules and the optical axis (the effective optical axis of the liquid crystal layer) and the polarization transmission axis of the polarizer, and Δ η is the refractive index anisotropy of the liquid crystal layer (Δ η = η ε — Η.), Where s is the wavelength of the incident light, d is the distance between the substrates (the effective thickness of the liquid crystal layer), and 7Γ is the pi.
ここで、 本発明では、 F i g . 3に示すように偏光板と液晶分子 と光軸のなす角ズは 4 5度でとすると、 式 1 の第 1項が 1 となるの で、 第 2項により透過率 T / T。が決定される。  Here, in the present invention, assuming that the angle formed between the polarizing plate and the liquid crystal molecules and the optical axis is 45 degrees as shown in FIG. 3, since the first term of the equation 1 becomes 1, the second Transmission T / T by term. Is determined.
したがって、 本発明では、 電圧の印加により液晶層の Δ nを制御 し、 式 1 の第 2項を変化させ、 透過率を制御し、 所望の表示を得る ものである。 F i g . 1 , F i g . 2に戻って説明すると、 電圧無 印加時には複屈折位相差が発生しない、 すなわち、 屈折率異方性 Δ nが 0であり、 透過率は 0 となる。 このとき視角方向を変化させて も、 本発明の様に垂直配向した状態で複屈折位相差が発生しないよ う に負の位相差フ イルム （ n x = n y〉 n z ) を用いる。 また、 わず かに発生する液晶材料の初期配向の傾き （基板面の法線方向からの 傾き） を補正するために、 微少な正の位相差フ ィルム （ n x〉 n y = n z ) を用いる。 これにより、 全視角方向で良好な黒レベルを得る こ とができる。 Therefore, in the present invention, Δn of the liquid crystal layer is controlled by applying a voltage. Then, by changing the second term of Expression 1, the transmittance is controlled, and a desired display is obtained. Returning to FIG. 1 and FIG. 2, when no voltage is applied, no birefringence phase difference occurs. That is, the refractive index anisotropy Δn is 0, and the transmittance is 0. Be this time by changing the viewing direction, using a negative retardation off Ilm (n x = n y> n z) in the Hare by birefringence phase difference in a state of being vertically aligned it does not occur as in the present invention. The slope of the initial alignment of the liquid crystal material to crab occur without I in order to correct the (tilt from the normal direction of the substrate surface), slight positive retardation off Irumu (n x> n y = n z) Is used. Thereby, a good black level can be obtained in all viewing angle directions.
一方、 電圧印加時には、 液晶分子の光軸が基板面に平行になり入 射光に対し最大の屈折率異方性を表す。 このとき、 液晶の屈折率異 方性 Δ n と液晶層の厚み dの積 （ リ タデ一シヨ ン） を入射光の波長 λ (約 4 0 0 11 111〜 7 0 0 11 111 ) の lZ 2に設定すれば、 透過率は 最大となり、 白表示を得るこ とができる。  On the other hand, when a voltage is applied, the optical axis of the liquid crystal molecules is parallel to the substrate surface, and exhibits the maximum refractive index anisotropy with respect to the incident light. At this time, the product (retardation) of the refractive index anisotropy Δn of the liquid crystal and the thickness d of the liquid crystal layer is defined as the lZ 2 of the wavelength λ of the incident light (approximately 400 1111 to 70011111). When set to, the transmittance is maximized and a white display can be obtained.
ここで、 本発明が従来の垂直配向モー ドと異なる点は、 本発明で は、 液晶組成物層に一対の基板の基板面に略平行な電界を印加する ための電極構成により、 電気力線が半円上に湾曲しているため、 必 然的に液晶分子の動作が 2方向に別れるため、 従来の垂直配向で、 白表示の視野角特性を広げるために行っている配向分割を施すこ と が不必要であり、 それにともなって問題となっていた配向安定性が 向上し、 長時間高画質を維持できる高信頼性を得るこ とができるこ とである。  Here, the point that the present invention differs from the conventional vertical alignment mode is that, in the present invention, an electrode configuration for applying an electric field substantially parallel to the substrate surfaces of the pair of substrates to the liquid crystal composition layer causes the lines of electric force to flow. Since the liquid crystal molecules are curved in a semicircle, the movements of the liquid crystal molecules are inevitably separated in two directions. This is not necessary, and the alignment stability, which has been a problem, is improved, and high reliability for maintaining high image quality for a long time can be obtained.
したがって、 高コ ン トラス ト比が得られ、 かつ、 広視野角特性を 得られると同時に、 高画質を維持できる高信頼性を両立できる。  Therefore, a high contrast ratio can be obtained, a wide viewing angle characteristic can be obtained, and high reliability that can maintain high image quality can be achieved.
また、 第 2の作用として、 配向膜と液晶の界面での、 液晶分子を 固定する力 （アンカ リ ング） が小さいため、 液晶分子が、 液晶層内 で動き易く 、 そのため、 応答速度が極めて速く なる。 The second effect is that the liquid crystal molecules at the interface between the alignment film and the liquid crystal are Since the fixing force (anchoring) is small, the liquid crystal molecules are easy to move in the liquid crystal layer, so that the response speed is extremely high.
さ らに、 第 3の作用として、 従来の垂直配向モー ドでは、 高い透 過率状態 （白表示） を得るために、 液晶分子の光軸を基板面に平行 な方向に動かすために、 電界と垂直方向に光軸を揃える性質を有す る負の誘電異方性 （ Δ ε < 0 ) の液晶組成物を使う必要があるが、 本発明では、 液晶組成物層に一対の基板の基板面に略平行な電界を 印加するこ とにより、 高い誘電率異方性が得られ、 低電圧で駆動可 能な正の誘電異方性 （ Δ ε 〉 0 ) を有する液晶組成物 （正の誘電異 方性を有する液晶は電界方向と同方向に光軸を揃える） を使用する こ とができる。  Third, in the conventional vertical alignment mode, an electric field is applied to move the optical axis of the liquid crystal molecules in a direction parallel to the substrate surface in order to obtain a high transmittance state (white display). It is necessary to use a liquid crystal composition having a negative dielectric anisotropy (Δε <0) having a property of aligning the optical axis in a direction perpendicular to the substrate. By applying an electric field substantially parallel to the plane, a high dielectric anisotropy can be obtained, and a liquid crystal composition having a positive dielectric anisotropy (Δε> 0) that can be driven at a low voltage (positive The liquid crystal having dielectric anisotropy aligns the optical axis in the same direction as the electric field direction).
また、 第 4の作用として、 印加電界の方向で、 液晶分子の光軸の 基板面に平行な面内での方向が決定されるため、 従来の垂直配向モ — ドで行なっていたラビング処理等での配向方向制御が不必要であ る。 これにより、 その配向規制力による液晶分子の動きにく さも改 善でき、 さらに応答速度を向上するこ とができる。  The fourth effect is that the direction of the applied electric field determines the direction of the optical axis of the liquid crystal molecules in a plane parallel to the substrate surface, so that the rubbing treatment or the like performed in the conventional vertical alignment mode is performed. It is not necessary to control the alignment direction at the same time. Thereby, the movement of the liquid crystal molecules due to the alignment regulating force can be improved, and the response speed can be further improved.
これらの作用により、 イ ンプレーンスイ ッチングモ一 ドで実現で きない高速応答と、 垂直配向モ一 ドで実用化できない広視野角と高 信頼性の両立を、 全て解決するこ とができ、 極めて高画質で、 ブラ ゥン管を凌駕できる理想的な液晶表示装置を実現するこ とができる c 本発明、 本発明の更に他の目的及び本発明の更に他の特徴は図面 を参照した以下の実施例の説明から明らかとなるであろう。  These functions can solve both high-speed response that cannot be realized in the in-plane switching mode and wide viewing angle and high reliability that cannot be practically used in the vertical alignment mode. Thus, it is possible to realize an ideal liquid crystal display device that can surpass a Braun tube. C The present invention, still another object of the present invention, and other features of the present invention are described in the following embodiments with reference to the drawings. Will be clear from the description.
《アクティブ · マ ト リ クス液晶表示装置》  << Active matrix liquid crystal display device >>
以下、 アクティブ · マ ト リ クス方式のカラー液晶表示装置に本発 明を適用した実施例を説明する。 なお、 以下説明する図面で、 同一 機能を有するものは同一符号を付け、 その繰り返しの説明は省略す る。 Hereinafter, an embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described. In the drawings described below, those having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. You.
《マ ト リ クス部 （画素部） の平面構成》  << Planar configuration of matrix part (pixel part) >>
F i g . 4は本発明のアクティブ ' マ ト リ クス方式カラ一液晶表 示装置の一画素とその周辺を示す平面図である。  FIG. 4 is a plan view showing one pixel of the active matrix type color liquid crystal display device of the present invention and its periphery.
F i g . 4に示すよう に、 各画素は走査信号線 （ゲー ト信号線ま たは水平信号線） G L と、 対向電圧信号線 （対向電極配線） じしと、 隣接する 2本の映像信号線 （ ドレイ ン信号線または垂直信号線） D L との交差領域内 （ 4本の信号線で囲まれた領域内） に配置されて いる。 各画素は薄膜 ト ラ ンジスタ T F T、 蓄積容量 C stg、 画素電極 P Xおよび対向電極 C Tを含む。 走査信号線 G L、 対向電圧信号線 C Lは図では左右方向に延在し、上下方向に複数本配置されている。 映像信号線 D Lは上下方向に延在し、 左右方向に複数本配置されて いる。 画素電極 P Xはソース電極 S D 1 を介して薄膜 ト ラ ンジスタ T F Tと電気的に接続され、 対向電極 C Tも対向電圧信号線 C L と 電気的に接続されている。  As shown in Fig. 4, each pixel consists of a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode wiring), and two adjacent video signals. The line (drain signal line or vertical signal line) is arranged in the intersection area with the DL (in the area surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode CT. The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL are arranged in the vertical direction. The video signal lines DL extend in the up-down direction, and a plurality of video signal lines DL are arranged in the left-right direction. The pixel electrode PX is electrically connected to the thin-film transistor TFT via the source electrode SD1, and the counter electrode CT is also electrically connected to the counter voltage signal line CL.
画素電極 P Xと対向電極 C Tは互いに対向し、 各画素電極 P Xと 対向電極 C Tとの間で発生させられる基板面に略平行な電界により 液晶組成物 L Cの光学的な状態を制御し、 表示を制御する。 画素電 極 P Xと対向電極 C Tは櫛歯状に構成され、 それぞれ、 図の上下方 向に長細い電極となっている。  The pixel electrode PX and the counter electrode CT are opposed to each other, and the electric state of the liquid crystal composition LC is controlled by an electric field substantially parallel to the substrate surface generated between each pixel electrode PX and the counter electrode CT, and the display is performed. Control. The pixel electrode PX and the counter electrode CT are formed in a comb-like shape, and each is a thin electrode extending upward and downward in the figure.
1画素内の対向電極 C Tの本数 0 (櫛歯の本数） は、 画素電極 P Xの本数 （櫛歯の本数） P と 0 = P + 1 の関係を持つように構成す る （本実施例では、 0 = 3、 P = 2 ) 。 これは、 対向電極 C Tと画 素電極 P Xを交互に配置し、 かつ、 対向電極 C Tを映像信号線 D L に隣接させるためである。 これにより、 対向電極 C Tと画素電極 P Xの間の電界が、 映像信号線 D Lから発生する電界から影響を受け ないよう に、 対向電極 C Tで映像信号線 D Lからの不要な電気力線 をシール ドするこ とができる。対向電極 C Tは、画素電極と異なり、 後述の対向電圧信号線 C Lにより常に外部から電位を供給されてい るため電位は安定しており、 映像信号線 D Lに隣接しても電位が変 動がほとんどない。 したがって、 映像信号線 D Lからの不要な電気 力線をシールドするこ とができる。 また、 画素電極 P Xの映像信号 線 D Lからの幾何学的な位置が遠く なるので、 画素電極 P Xと映像 信号線 D Lの間の寄生容量が大幅に減少し、 画素電極電位 V sの映 像信号電圧による変動も抑制できる。 これらにより、 上下方向に発 生するクロス トーク （縦スミ アと呼ばれる画質不良） を抑制するこ とができる。 The number of counter electrodes CT (the number of comb teeth) 0 in one pixel is configured so as to have a relationship of 0 = P + 1 with the number of pixel electrodes PX (the number of comb teeth) P (in this embodiment, , 0 = 3, P = 2). This is because the counter electrode CT and the pixel electrode PX are alternately arranged, and the counter electrode CT is adjacent to the video signal line DL. As a result, the electric field between the counter electrode CT and the pixel electrode PX is affected by the electric field generated from the video signal line DL. Thus, unnecessary lines of electric force from the video signal line DL can be shielded by the counter electrode CT. The counter electrode CT is different from the pixel electrode in that the potential is constantly supplied from the outside through the counter voltage signal line CL described later, so that the potential is stable, and the potential fluctuates almost even when adjacent to the video signal line DL. Absent. Therefore, unnecessary electric power lines from the video signal lines DL can be shielded. In addition, since the geometric position of the pixel electrode PX from the video signal line DL is farther away, the parasitic capacitance between the pixel electrode PX and the video signal line DL is greatly reduced, and the video signal of the pixel electrode potential Vs Fluctuation due to voltage can also be suppressed. Thus, it is possible to suppress crosstalk (improper image quality called vertical smear) occurring in the vertical direction.
画素電極 P Xと対向電極 C Tの電極幅はそれぞれ 6 χα とする。 これは、 液晶層の厚み方向に対して、 液晶層全体に十分な電界を印 加するために、 後述の液晶組成物層の厚み 3 . 9 m より も十分大 き く設定する。 望ま しく は、 液晶組成物層の 1 . 5倍以上に設定す る。  The electrode widths of the pixel electrode PX and the counter electrode CT are respectively 6 6α. In order to apply a sufficient electric field to the entire liquid crystal layer in the thickness direction of the liquid crystal layer, the thickness is set to be sufficiently larger than 3.9 m of a liquid crystal composition layer described later. Desirably, the thickness is set to 1.5 times or more of the liquid crystal composition layer.
また、 開口率を大き くするためにできるだけ細くする。 また、 映 像信号線 D Lも 6 m とする。 映像信号線 D Lの電極幅は断線を防 止するために、 画素電極 P Xと対向電極 C Tに比較して若干広して も良い。 但し、 映像信号線 D Lの電極幅が、 隣接する対向電極 C T の電極幅の 2倍以下になるように設定する。 映像信号線 D Lの電極 幅が歩留りの生産性から決まっている場合には、 映像信号線 D Lに 隣接する対向電極 C Tの電極幅を映像信号線 D Lの電極幅の 1 ノ 2 以上にする。 これは、 映像信号線 D Lから発生する不要な電気力線 をそれぞれ両脇の対向電極 C Tで吸収するためであり、 ある電極幅 から発生する電気力線を吸収するには、 それと同一幅以上のの電極 幅を持つ電極が必要である。 したがって、 映像信号線 D Lの電極の 半分 （ 4 ^mずつ） から発生する電気力線をそれぞれ両脇の対向電 極 C Tが吸収しればよいため、 映像信号線 D Lに隣接する対向電極 C Tの電極幅が 1 Z 2以上とする。 これにより、 映像信号の影響に よるクロス トークが発生、 特に上下方向 （縦方向） のク ロス トーク を防止する。 Also, make it as thin as possible to increase the aperture ratio. The video signal line DL is also 6 m. The electrode width of the video signal line DL may be slightly wider than the pixel electrode PX and the counter electrode CT in order to prevent disconnection. However, the electrode width of the video signal line DL is set to be less than twice the electrode width of the adjacent counter electrode CT. When the electrode width of the video signal line DL is determined from the productivity of the yield, the electrode width of the counter electrode CT adjacent to the video signal line DL is set to be equal to or more than 1 to 2 of the electrode width of the video signal line DL. This is because the unnecessary lines of electric force generated from the video signal line DL are absorbed by the counter electrodes CT on both sides, respectively.To absorb the lines of electric force generated from a certain electrode width, the lines with the same width or more must be absorbed. Electrode An electrode with a width is required. Therefore, since the lines of electric force generated from half (4 ^ m each) of the electrode of the video signal line DL need only be absorbed by the counter electrode CT on each side, the electrode of the counter electrode CT adjacent to the video signal line DL is required. The width should be 1 Z 2 or more. This prevents crosstalk due to the effect of the video signal, and in particular, prevents vertical (vertical) crosstalk.
走査信号線 G Lは末端側の画素 （後述の走査電極端子 G T Mの反 対側） のゲー ト電極 G Tに十分に走査電圧が伝搬されるだけの抵抗 値を満足するように電極幅を設定する。 また、 対向電圧信号線 C L も末端側の画素 （後述の共通バスライ ン C B 1 および C B 2から最 も遠い画素すなわち C B 1 と C B 2の中間の画素） の対向電極 C T に十分に対向電圧が印加できるだけの抵抗値を満足するように電極 幅を設定する。  The width of the scanning signal line GL is set so as to satisfy a resistance value enough to transmit a scanning voltage sufficiently to the gate electrode GT of the terminal pixel (opposite to the scanning electrode terminal GTM described later). In addition, a sufficient counter voltage is applied to the counter voltage signal line CL to the counter electrode CT of the pixel on the terminal side (the pixel farthest from the common bus lines CB 1 and CB 2 described later, that is, the pixel between CB 1 and CB 2). Set the electrode width to satisfy the required resistance.
一方、 画素電極 P Xと対向電極 C Tの間の電極間隔は、 用いる液 晶材料によって変える。 これは、 液晶材料によって最大透過率を達 成する電界強度が異なるため、電極間隔を液晶材料に応じて設定し、 用いる映像信号駆動回路 （信号側 ドライバ） の耐圧で設定される信 号電圧の最大振幅の範囲で、 最大透過率が得られるよう にするため である。 後述の液晶材料を用いると電極間隔は、 1 6 im となる。 《マ ト リ クス部 （画素部） の断面構成》  On the other hand, the electrode spacing between the pixel electrode PX and the counter electrode CT changes depending on the liquid crystal material used. This is because the electric field intensity that achieves the maximum transmittance varies depending on the liquid crystal material, so the electrode spacing is set according to the liquid crystal material, and the signal voltage set by the withstand voltage of the video signal drive circuit (signal driver) used. This is so that the maximum transmittance can be obtained in the maximum amplitude range. When a liquid crystal material described later is used, the electrode interval is 16 im. 《Cross-sectional configuration of matrix part (pixel part)》
F i g . 5は F i g . 4 の 6 — 6切断線における断面を示す図、 F i g . 6は F i g . 4の 7 — 7切断線における薄膜 トランジスタ T F Tの断面図、 F i g . 7は F i g . 4の 8 — 8切断線における 蓄積容量 Cstg の断面を示す図である。 F i g . 5〜 F i g . 7 に 示すように、 液晶組成物層 L Cを基準にして下部透明ガラス基板 S U B 1側には薄膜 トラ ンジスタ T F T、 蓄積容量 C stg および電極 群が形成され、 上部透明ガラス基板 S U B 2側にはカラーフィルタ F I L、遮光用ブラ ッ クマ ト リ クスパターン B Mが形成されている。 また、 透明ガラス基板 S U B 1、 S U B 2のそれぞれの内側 （液 晶 L C側） の表面には、 液晶の初期配向を制御する配向膜 A F 1、 A F 2が設けられており 、 透明ガラス基板 S U B 1、 S U B 2のそ れぞれの外側の表面には、 偏光板が設けられている。 5 is a cross-sectional view of FIG. 4 taken along the line 6-6, FIG. 6 is a cross-sectional view of the thin film transistor TFT taken along the line 7-7 of FIG. 4, and FIG. 7 is F. 4 is a diagram showing a cross section of the storage capacitor Cstg at the 8-8 cutting line of ig. 4. FIG. As shown in Fig. 5 to Fig. 7, the lower transparent glass substrate SUB1 has a thin film transistor TFT, a storage capacitor Cstg and an electrode on the SUB1 side with respect to the liquid crystal composition layer LC. A group is formed, and a color filter FIL and a light blocking black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side. In addition, alignment films AF 1 and AF 2 for controlling the initial alignment of the liquid crystal are provided on the inner surface (the liquid crystal LC side) of each of the transparent glass substrates SUB 1 and SUB 2. A polarizing plate is provided on the outer surface of each of the sub 2 and the sub 2.
《 T F T基板》  << T F T board >>
まず、 下側透明ガラス基板 S U B 1側 （ T F T基板） の構成を詳 しく説明する。  First, the configuration of the lower transparent glass substrate SUB1 side (TFT substrate) will be described in detail.
《薄膜 トラ ンジスタ T F T》  《Thin film transistor T F T》
薄膜 トラ ンジスタ T F Tは、 ゲー 卜電極 G Tに正のバイアスを印 加すると、 ソース— ドレイ ン間のチャネル抵抗が小さ く なり、 バイ ァスを零にすると、 チャネル抵抗は大き く なるよう に動作する。 薄膜 トラ ンジスタ T F Tは、 F i g . 6に示すよう に、 ゲー ト電 極 G T、 絶縁膜 G I、 i 型 （真性、 intrinsic^ 導電型決定不純物が ドープされていない） 非晶質シ リ コン （ S i ) からなる i 型半導体 層 A S、 一対のソ一ス電極 S D 1 、 ドレイ ン電極 S D 2を有す。 な お、 ソース、 ドレイ ンは本来その間のバイアス極性によって決まる もので、 この液晶表示装置の回路ではその極性は動作中反転するの で、 ソース、 ド レイ ンは動作中入れ替わる と理解されたい。 しカヽし、 以下の説明では、 便宜上一方をソース、 他方を ドレイ ンと固定して 表現する。  When a positive bias is applied to the gate electrode GT, the thin-film transistor TFT operates such that the channel resistance between the source and the drain decreases, and when the bias is reduced to zero, the channel resistance increases. . As shown in Fig. 6, the thin-film transistor TFT has a gate electrode GT, an insulating film GI, an i-type (intrinsic, not doped with intrinsic ^ conductivity-type-determining impurities) amorphous silicon (S i), an i-type semiconductor layer AS, a pair of source electrodes SD 1, and a drain electrode SD 2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity of the liquid crystal display device is reversed during operation, so that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.
《ゲー ト電極 G T》  《Gate electrode G T》
ゲ一 ト電極 G Tは走査信号線 G Lと連続して形成されており、 走 査信号線 G Lの一部の領域がゲー ト電極 G Tとなるよう に構成され ている。 ゲー ト電極 G Tは薄膜 トラ ンジスタ T F Tの能動領域を超 える部分である。 本例では、 ゲー ト電極 G Tは、 単層の導電膜 g 3 で形成されている。 導電膜 g 3 と しては例えばスパッ クで形成され たク ロム—モ リ ブデン合金 （ C r - M o ) 膜が用いられるがそれに 限ったものではない。 The gate electrode GT is formed continuously with the scanning signal line GL, and is configured so that a part of the scanning signal line GL becomes the gate electrode GT. Gate electrode GT exceeds the active area of thin-film transistor TFT Part. In this example, the gate electrode GT is formed of a single conductive film g3. As the conductive film g3, for example, a chromium-molybdenum alloy (Cr-Mo) film formed by using a spark is used, but not limited thereto.
《走査信号線 G L》  《Scan signal line G L》
走査信号線 G Lは導電膜 g 3で構成されている。 この走査信号線 G Lの導電膜 g 3 はゲ一 卜電極 G Tの導電膜 g 3 と同一製造工程で 形成され、 かつ一体に構成されている。 この走査信号線 G Lにより、 外部回路からゲー ト電圧 （走査電圧） V g をゲ一 ト電極 G Tに供給 する。 本例では、 導電膜 g 3 と しては例えばスパッ夕で形成された ク ロム—モリ ブデン合金 （ C r 一 M o ) 膜が用いられる。 また、走査 信号線 G Lおよびはゲー ト電極 G Tは、ク ロム—モ リ ブデン合金の みに限られたものではな く 、たとえば、低抵抗化のためにアルミニゥ ムまたはアルミニウム合金をク ロム—モ リ ブデンで包み込んだ 2層 構造と してもよい。  The scanning signal line GL is formed of the conductive film g3. The conductive film g3 of the scanning signal line GL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, and is integrally formed. A gate voltage (scanning voltage) Vg is supplied from an external circuit to the gate electrode GT through the scanning signal line GL. In this example, as the conductive film g3, for example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used. Further, the scanning signal lines GL and the gate electrodes GT are not limited to the chromium-molybdenum alloy, but may be made of, for example, aluminum or an aluminum alloy to reduce resistance. It may be a two-layer structure wrapped in ribden.
さ らに、 映像信号線 D L と交差する部分は映像信号線 D L との短 絡の確率を小さ く するため細く し、 また、 短絡しても、 レーザー ト リ ミ ングで切り離すこ とができるよう に二股にしても良い。  In addition, the part that intersects with the video signal line DL is made thinner to reduce the probability of a short circuit with the video signal line DL, and even if it is short-circuited, it can be separated by laser trimming. You may be bifurcated.
《対向電圧信号線 C し》  《Opposite voltage signal line C》
対向電圧信号線 C Lは導電膜 g 3で構成されている。 この対向電 圧信号線 C Lの導電膜 g 3はゲー ト電極 G T、 走査信号線 G Lおよ び対向電極 C Tの導電膜 g 3 と同一製造工程で形成され、 かつ対向 電極 C T と電気的に接続できるよう に構成されている。 この対向電 圧信号線 C Lにより、 外部回路から対向電圧 V comを対向電極 C T に供給する。 また、対向電圧信号線 C Lは、ク ロム一モ リ ブデン合金 のみに限られたものではなく 、たとえば、低抵抗化のためにアルミ二 ゥムまたはアルミニウム合金をクロム一モ リ ブデンで包み込んだ 2 層構造としてもよい。 さ らに、 映像信号線 D L と交差する部分は映 像信号線 D L との短絡の確率を小さ くするため細く し、 また、 短絡 しても、 レーザ一 ト リ ミ ングで切り離すこ とができるよう に二股に しても良い。 The counter voltage signal line CL is formed of the conductive film g3. The conductive film g3 of the counter voltage signal line CL is formed in the same manufacturing process as the gate electrode GT, the scanning signal line GL, and the conductive film g3 of the counter electrode CT, and is electrically connected to the counter electrode CT. It is configured to be able to do so. The counter voltage Vcom is supplied from an external circuit to the counter electrode CT through the counter voltage signal line CL. Further, the counter voltage signal line CL is not limited to the chromium-molybdenum alloy, but may be, for example, an aluminum alloy to reduce resistance. It may be a two-layer structure in which a chrome or aluminum alloy is wrapped with chromium-molybdenum. Furthermore, the portion that intersects with the video signal line DL is made thinner to reduce the probability of short-circuit with the video signal line DL, and even if it is short-circuited, it can be separated by laser trimming. It may be forked.
《絶縁膜 G I 》  《Insulating film G I》
絶縁膜 G I は、 薄膜 トラ ンジスタ T F Tにおいて、 ゲー ト電極 G Tと共に半導体層 A Sに電界を与えるためのゲー ト絶縁膜として使 用される。 絶縁膜 G I はゲ一 ト電極 G Tおよび走査信号線 G Lの上 層に形成されている。 絶縁膜 G I としては例えばプラズマ C V Dで 形成された窒化シリ コン膜が選ばれ、 2 0 0 0 〜 4 5 0 0人の厚さ に （本実施例では、 3 5 0 0 A程度） 形成される。 また、絶縁膜 G I は走査信号線 G Lおよび対向電圧信号線 C L と映像信号線 D Lの層 間絶縁膜としても働き、 それらの電気的絶縁にも寄与している。 《 i 型半導体層 A S》  The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected, and is formed to a thickness of 2000 to 450 persons (in this embodiment, about 350 A). . Further, the insulating film GI also functions as an inter-layer insulating film of the scanning signal line GL, the counter voltage signal line CL, and the video signal line DL, and also contributes to their electrical insulation. 《I-type semiconductor layer A S》
i 型半導体層 A Sは、 非晶質シ リ コ ンで、 1 5 0 〜 2 5 0 0 Aの 厚さに （本実施例では、 1 2 0 0 A程度の膜厚） で形成される。 層 d 0はォ一ミ ックコンタク ト用のリ ン （ P ) を ド一プした N ( + )型 非晶質シリ コン半導体層であり、下側に i 型半導体層 A Sが存在し、 上側に導電層 d 3が存在するところのみに残されている。  The i-type semiconductor layer AS is made of amorphous silicon and has a thickness of 150 to 250 A (in this embodiment, a thickness of about 1200 A). The layer d0 is an N (+) type amorphous silicon semiconductor layer obtained by doping a phosphorus (P) for a common contact, and an i-type semiconductor layer AS exists on the lower side and an upper side on the upper side. It is left only where the conductive layer d3 is present.
i 型半導体層 A Sおよび層 d 0は、 走査信号線 G Lおよび対向電 圧信号線 C Lと映像信号線 D Lとの交差部 （クロスオーバ部） の両 者間にも設けられている。 この交差部の i 型半導体層 A Sは交差部 における走査信号線 G Lおよび対向電圧信号線 C L と映像信号線 D Lとの短絡を低減する。  The i-type semiconductor layer AS and the layer d0 are also provided between the scanning signal line GL and the intersection (crossover portion) between the counter voltage signal line CL and the video signal line DL. The i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL at the intersection.
《ソース電極 S D 1 、 ドレイ ン電極 S D 2》 ソース電極 S D 1 、 ドレイ ン電極 S D 2のそれぞれは、 N(+)型 半導体層 d 0に接触する導電膜 d 3から構成されている。 《Source electrode SD 1, Drain electrode SD 2》 Each of the source electrode SD 1 and the drain electrode SD 2 is formed of a conductive film d3 that is in contact with the N (+) type semiconductor layer d0.
導電膜 d 3はスパッ夕で形成したク ロム—モリ ブデン合金 （ C r — M o ) 膜を用い、 5 0 0〜 3 0 0 O Aの厚さに （本実施例では、 2 δ 0 O A程度） で形成される。 C r 一 M o膜は低応力であるので、 比較的膜厚を厚く 形成するこ とができ配線の低抵抗化に寄与する。 また、 C r 一 M o膜は N(+)型半導体層 d O との接着性も良好であ る。 導電膜 d 3 と して、 C r 一 M o膜の他に高融点金属 （M o、 T i 、 T a、 W) 膜、 高融点金属シ リサイ ド （M o S i 2、 T i S i 2、 T a S i 2、 W S i 2) 膜を用いてもよ く 、また、アルミニウム等との 積層構造にしてもよい。  The conductive film d3 uses a chromium-molybdenum alloy (Cr—Mo) film formed by sputtering and has a thickness of 500 to 300 OA (in this embodiment, about 2δ0 OA). ) Is formed. Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d O. As the conductive film d3, in addition to the Cr-Mo film, a refractory metal (Mo, Ti, Ta, W) film, a refractory metal silicide (MoSi2, TiS) i2, TaSi2, WSi2) A film may be used, or a laminated structure with aluminum or the like may be used.
《映像信号線 D L》  《Video signal line D L》
映像信号線 D Lはソース電極 S D 1 、 ドレイ ン電極 S D 2 と同層 の導電膜 d 3で構成されている。 また、 映像信号線 D Lは ドレイ ン 電極 S D 2 と一体に形成されている。 本例では、 導電膜 d 3はスパ ッ夕で形成したク ロム—モ リ ブデン合金 （ C r — M o ) 膜を用い、 5 0 0〜 3 0 0 O Aの厚さに （本実施例では、 2 5 0 O A程度） で 形成される。 C r 一 M o膜は低応力であるので、 比較的膜厚を厚く 形成するこ とができ配線の低抵抗化に寄与する。 また、 C r 一 M o 膜は N( + )型半導体層 d 0 との接着性も良好である。 導電膜 d 3 と して、 C r — M o膜の他に高融点金属 （M o、 T i 、 T a、 W) 膜、 高融点金属シ リ サイ ド （M o S i 2、 T i S i 2、 T a S i 2、 W S i 2) 膜を用いてもよ く 、 また、 アルミ ニウム等との積層構造に し てもよい。  The video signal line DL is formed of a conductive film d3 of the same layer as the source electrode SD1 and the drain electrode SD2. The video signal line DL is formed integrally with the drain electrode SD2. In this example, the conductive film d3 uses a chromium-molybdenum alloy (Cr—Mo) film formed by sputtering, and has a thickness of 500 to 300 OA (in this example, , About 250 OA). Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d 0. As the conductive film d 3, in addition to the Cr—Mo film, a high melting point metal (Mo, Ti, Ta, W) film, a high melting point metal silicide (MoSi 2, Ti) Si 2, Ta Si 2, WS i 2) A film may be used, or a laminated structure with aluminum or the like may be used.
《蓄積容量 Cstg》  《Storage capacity Cstg》
導電膜 d 3は、 薄膜 トラ ンジスタ T F Tのソース電極 S D 2部分 において、 対向電圧信号線 C L と重なるよう に形成されている。 こ の重ね合わせは、 F i g . 7からも明らかなよう に、 ソース電極 S D 2 ( d 3 ) を一方の電極と し、 対向電圧信号 C Lを他方の電極と する蓄積容量 （静電容量素子） C stg を構成する。 こ の蓄積容量 C stg の誘電体膜は、 薄膜 トラ ンジスタ T F Tのゲー 卜絶縁膜として 使用される絶縁膜 G I で構成されている。 The conductive film d 3 is a thin film transistor TFT source electrode SD 2 portion In this case, it is formed so as to overlap the counter voltage signal line CL. As is clear from Fig. 7, this superposition is performed by using a storage capacitor (capacitance element) in which the source electrode SD 2 (d 3) is used as one electrode and the counter voltage signal CL is used as the other electrode. Configure C stg. The dielectric film of the storage capacitor C stg is composed of an insulating film GI used as a gate insulating film of the thin-film transistor TFT.
F i g . 4 に示すよう に平面的には蓄積容量 C stg は対向電圧信 号線 C Lの一部分に形成されている。  As shown in FIG. 4, the storage capacitance C stg is formed in a part of the counter voltage signal line CL in plan view.
《保護膜 P S V 1 》  《Protective film P S V 1》
薄膜 トラ ンジスタ T F T上には保護膜 P S V 1 が設けられている。 保護膜 P S V 1 は主に薄膜 トラ ンジスタ T F Tを湿気等から保護す るために形成されており、 透明性が高く しかも耐湿性の良いものを 使用する。 保護膜 P S V 1 はたとえばプラズマ C V D装置で形成し た酸化シ リ コ ン膜ゃ窒化シ リ コ ン膜で形成されており、 0. 1〜 1 m程度の膜厚で形成する。  A protective film PSV1 is provided on the thin film transistor TFT. The protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film / silicon nitride film formed by a plasma CVD device, and has a thickness of about 0.1 to 1 m.
保護膜 P S V 1 は、 外部接続端子 D T M、 G T Mを露出するよう 除去されている。 保護膜 P S V 1 と絶縁膜 G I の厚さ関係に関して は、 前者は保護効果を考え厚く され、 後者は ト ラ ンジスタの相互コ ンダクタ ンス g mを薄く される。  The protective film PSV1 is removed so as to expose the external connection terminals DTM and GTM. Regarding the thickness relationship between the protective film PSV1 and the insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner by the transconductance gm of the transistor.
また、 画素部では、 対向電圧信号線 C L と後述の対向電極 C Tと の電気的接続、 および、 ソース電極 S D 2 と画素電極 P Xとの電気 的接続のために、 スルーホール T H 2および T H 1 を設けている。 スルーホール T H 2では、 保護膜 P S V 1 と絶縁膜 G I がー括で加 ェされるので g 3層までの孔があき、 スルーホール T H 1 では d 3 でブロ ッキングされるので d 3層までの孔があく 。  In the pixel portion, through holes TH 2 and TH 1 are provided for electrical connection between the counter voltage signal line CL and a counter electrode CT described later, and for electrical connection between the source electrode SD 2 and the pixel electrode PX. Provided. In the through-hole TH2, the protective film PSV1 and the insulating film GI are added together so that a hole up to the g3 layer is formed. A hole is made.
また、 保護膜 P S V 1 は、 ポ リ イ ミ ド等の有機膜を厚く構成した ものとの積層構造としても良い。 In addition, the protective film PSV 1 is made of a thick organic film such as polyimide. It may have a laminated structure with the object.
《画素電極 P X》  《Pixel electrode P X》
画素電極 P Xは、 透明導電層 i 1で形成されている。 この透明導 電膜 i 1 はスパッタ リ ングで形成された透明導電膜 （Indium-Tin- Oxide I T O : ネサ膜） からなり、 1 0 0〜 2 0 0 0 Αの厚さに (本実施例では、 1 4 0 0人程度の膜厚） 形成される。 また、 画素 電極 Ρ Xはスルーホール Τ Η 1 を介して、 ソース電極 S D 2に接続 されている。  The pixel electrode PX is formed of the transparent conductive layer i1. This transparent conductive film i1 is composed of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering, and has a thickness of 100 to 200 mm (in this embodiment, , About 140 people). In addition, the pixel electrode ΡX is connected to the source electrode SD2 via the through hole Τ1.
画素電極が本実施例のように透明になるこ とにより、 その部分の 透過光により、 白表示を行う時の最大透過率が向上するため、 画素 電極が不透明な場合より も、 より明るい表示を行う こ とができる。 この時、 後述するよう に、 電圧無印加時には、 液晶分子は初期の配 向状態を保ち、 その状態で黒表示をするよう に偏光板の配置を構成 する （ノーマリ ブラ ックモー ドにする） にしているので、 画素電極 を透明にしても、 その部分の光を透過するこ とがなく、 良質な黒を 表示するこ とができる。 これにより、 最大透過率が向上させ、 かつ 十分なコン トラス ト比を達成するこ とができる。  By making the pixel electrode transparent as in this embodiment, the transmitted light in that part improves the maximum transmittance when white display is performed, so that a brighter display is displayed than when the pixel electrode is opaque. It can be carried out. At this time, as described later, when no voltage is applied, the liquid crystal molecules maintain the initial alignment state, and the polarizing plate is arranged so as to display black in that state (normal black mode). Therefore, even if the pixel electrode is transparent, light of that part does not pass through, and high-quality black can be displayed. As a result, the maximum transmittance can be improved, and a sufficient contrast ratio can be achieved.
《対向電極 C τ》  《Counter electrode C τ》
対向電極 C Τは透明導電層 i 1で形成されている。 この透明導電 膜 i 1 はスパッ ク リ ングで形成された透明導電膜 （ Indium-Tin- Oxide I T O : ネサ膜） からなり、 1 0 0〜 2 0 0 0 Aの厚さに (本実施例では、 1 4 0 0人程度の膜厚） 形成される。 また、 対向 電極 C Tはスルーホール Τ Η 2を介して、 対向電圧信号線 C Lに接 続されている。 画素電極 Ρ Χと同様、 対向電極を透明にするこ とに より、 白表示を行う時の最大透過率が向上する。  The counter electrode C is formed of the transparent conductive layer i1. The transparent conductive film i1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering, and has a thickness of 100 to 200 A (in this embodiment, , About 140 people). Further, the common electrode CT is connected to the common voltage signal line CL via the through-hole # 2. As in the case of the pixel electrode Ρ, by making the counter electrode transparent, the maximum transmittance when white display is performed is improved.
対向電極 C Τには対向電圧 V comが印加されるように構成されて いる。 本実施例では、 対向電圧 Vcomは映像信号線 D Lに印加され る最小レベルの駆動電圧 V d min と最大レベルの駆動電圧 V d max との中間直流電位から、 薄膜 トラ ンジスタ素子 T F Tをオフ状態に するときに発生するフィ ー ドスルー電圧 Δ Vs 分だけ低い電位に設 定されるが、 映像信号駆動回路で使用される集積回路の電源電圧を 約半分に低減したい場合は、 交流電圧を印加すれば良い。 The counter electrode C Τ is configured so that a counter voltage V com is applied. I have. In this embodiment, the counter voltage Vcom turns off the thin-film transistor element TFT from an intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL. Although is set to potential lower Fi over Dosuru voltage delta V s min which occurred at the time of, if you want to decrease the power supply voltage of the integrated circuit to be used in the video signal driver circuit to approximately half, by applying an alternating voltage Good.
《カラ一フィルタ基板》  《Color filter board》
次に、 F i g . 4、 F i g . 5 に戻り、 上側透明ガラス基板 S U B2側 （カラーフィルタ基板） の構成を詳し く説明する。  Next, returning to FIGS. 4 and 5, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail.
《遮光膜 B M》  《Light shielding film B M》
上部透明ガラス基板 S U B 2側には、 不要な間隙部 （画素電極 P Xと対向電極 C Tの間以外の隙間） からの透過光が表示面側に出射 して、 コン トラス ト比等を低下させないよう に遮光膜 B M (いわゆ るブラ ッ クマ ト リ クス） を形成している。 遮光膜 B Mは、 外部光ま たはバッ ク ライ ト光が i 型半導体層 A Sに入射しないよう にする役 割も果たしている。 すなわち、 薄膜 トラ ンジスタ T F Tの i 型半導 体層 A Sは上下にある遮光膜 B Mおよび大き目のゲー ト電極 G Tに よってサン ドイ ッチにされ、 外部の自然光やバッ ク ライ ト光が当た らな く なる。  On the upper transparent glass substrate SUB2 side, the transmitted light from unnecessary gaps (gap other than between the pixel electrode PX and the counter electrode CT) is emitted to the display surface side so as not to lower the contrast ratio etc. A light-shielding film BM (so-called black matrix) is formed on the surface. The light shielding film BM also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched between the upper and lower light shielding films BM and the large gate electrode GT, and is exposed to external natural light or backlight light. It disappears.
F i g . 4に示す遮光膜 B Mは、 薄膜 トラ ンジスタ素子 T F T上 部に左右方向に線状に延在した構成である。 このパター ンは、 1例 であり、 開口部を孔状にあけたマ ト リ クス状の様にするこ ともでき る。 櫛歯電極端部等の電界方向が乱れる部分においては、 その部分 の表示は、 画素内の映像情報に 1対 1で対応し、 かつ、 黒の場合に は黒、 白の場合には白になるため、 表示の一部と して利用するこ と が可能である。 また、 図の上下方向における対向電極 C Tと映像信 号線 D L との間隙部は、 ゲー ト電極 G Tと同一工程で形成した第 2 遮光層 S Hで遮光する。 これにより左右方向の上下方向の遮光は、 T F T工程のァライメ ン ト精度で高精度に遮光できるので、 映像信 号線 D Lに隣接する対向電極 C Τの電極間に第 2遮光層 S Ηの境界 を設定でき、 上下基板のあわせ精度に依存する遮光膜 Β Μによる遮 光より も、 より開口部を拡大するこ とができる。 The light-shielding film BM shown in FIG. 4 has a configuration extending linearly in the left-right direction above the thin-film transistor element TFT. This pattern is an example, and the opening may be formed in a matrix shape with holes. In a part where the electric field direction is disturbed, such as the end of a comb-shaped electrode, the display of that part corresponds to the video information in the pixel on a one-to-one basis, and is black in black and white in white. Therefore, it can be used as part of the display. In addition, the counter electrode CT and the video signal The gap with the signal line DL is shielded from light by a second light-shielding layer SH formed in the same process as the gate electrode GT. As a result, the light shielding in the vertical direction in the horizontal direction can be accurately shielded with the alignment accuracy of the TFT process, so that the boundary of the second light shielding layer SΗ between the electrodes of the counter electrode CΤ adjacent to the video signal line DL is formed. It can be set and the opening can be enlarged more than the light shielding by the light shielding film 遮光 which depends on the alignment accuracy of the upper and lower substrates.
また、 遮光膜 Β Μを薄膜 トラ ンジスタ基板 S U B 1上に形成する こ ともできる。 これにより、 第 2遮光層 S H同様、 上下基板のあわ せ精度に依存する基板 S U B 2上の遮光膜 B Mによる遮光より も、 より開口部を拡大するこ とができる。  Further, the light-shielding film can be formed on the thin-film transistor substrate SUB1. As a result, similarly to the second light-shielding layer SH, the opening can be further enlarged as compared with the light-shielding by the light-shielding film BM on the substrate SUB2 which depends on the accuracy of the upper and lower substrates.
但し、 遮光膜 B Mは光に対する遮蔽性を有し、 かつ、 画素電極 P Xと対向電極 C Tの間の電界に影響を与えないよう に絶縁性の高い 膜で形成されており、 本実施例では黒色の有機顔料をレジス ト材に 混入し、 1.2 im程度の厚さで形成している。 また、 光に対する遮 蔽性を向上させるためにカーボン、 チタ ン酸化物 （ T i x O y ) を、 絶縁性が液晶組成物層内の電界に影響を与えない 1 0 8 Ω c m以上 を維持できる範囲で、 混入させても良い。 また、 第 2遮光層 S Hは 映像信号線からの電気力戦を吸収しやすい様に、 導電性を有するほ うが良い。  However, the light-shielding film BM has a light-shielding property and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the counter electrode CT. The organic pigment is mixed with a resist material to form a thickness of about 1.2 im. In addition, carbon and titanium oxide (TixOy) can be maintained to improve the light shielding property, and 108 Ωcm or more, whose insulating property does not affect the electric field in the liquid crystal composition layer, can be maintained. It may be mixed within the range. Further, it is preferable that the second light-shielding layer SH has conductivity so as to easily absorb electric power from the video signal line.
遮光膜 B Mは各行の画素に左右方向に線状に形成され、 この線で 各行の有効表示領域が仕切られている。 従って、 各行の画素の輪郭 が遮光膜 B Mによってはっきり とする。 つま り、 遮光膜 B Mは.ブラ ックマ ト リ クスと i 型半導体層 A Sに対する遮光との 2つの機能を もつ。  The light-shielding film BM is linearly formed in the pixels in each row in the left-right direction, and the lines partition the effective display area in each row. Therefore, the outline of the pixels in each row is made clear by the light-shielding film BM. That is, the light shielding film BM has two functions of black matrix and light shielding for the i-type semiconductor layer AS.
遮光膜 B Mは周辺部にも額縁状に形成され、 そのパターンは F i g - 4 に示すマ ト リ クス部のパターンと連続して形成されている。 周辺部の遮光膜 B Mは、 シール部 S Lの外側に延長され、 パ ソ コ ン 等の実装機に起因する反射光等の漏れ光がマ ト リ クス部に入り込む のを防ぐと共に、 パ'ッ ク ライ ト等の光が表示エリ ア外に漏れるのも 防いでいる。 他方、 この遮光膜 B Mは基板 S U B 2の縁より も約 0 . 3〜 1 . 0 m m程内側に留められ、 基板 S U B 2 の切断領域を避け て形成されている。 The light-shielding film BM is also formed in a frame shape at the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG. The light-shielding film BM in the peripheral portion is extended outside the seal portion SL to prevent leakage light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion and to prevent the light from leaking. It also prevents light such as light from leaking out of the display area. On the other hand, the light-shielding film BM is retained about 0.3 to 1.0 mm inside the edge of the substrate SUB2, and is formed so as to avoid the cut region of the substrate SUB2.
. 《カラ一フ イ ソレタ F I L》 《Colorful I Soleta F I L》
カラーフ ィ ルタ F I Lは画素に対向する位置に赤、 緑、 青の繰り 返しでス トライプ状に形成される。 カラ一フィ ルタ F I Lは 2重遮 光膜 S Hのエッ ジ部分と重なるよう に形成されている。  The color filter FIL is formed in a stripe shape by repeating red, green, and blue at a position facing the pixel. The color filter FIL is formed so as to overlap the edge portion of the double light shielding film SH.
カラーフィ ルタ F I Lは次のよう に形成するこ とができる。まず、 上部透明ガラス基板 S U B 2の表面にァク リル系樹脂等の染色基材 を形成し、 フ ォ ト リ ソグラフィ技術で赤色フィルタ形成領域以外の 染色基材を除去する。 この後、 染色基材を赤色顔料で染め、 固着処 理を施し、 赤色フ ィ ルタ Rを形成する。 つぎに、 同様な工程を施す こ とによって、 緑色フ ィ ルタ G、 青色フィ ルタ Bを順次形成する。 なお、 染色には染料を用いてもよい。  The color filter FIL can be formed as follows. First, a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed base material is dyed with a red pigment and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process. A dye may be used for dyeing.
《オーバ—コー 卜膜 0 C》  《Over-coating film 0 C》
オーバ一コー ト膜 0 Cはカラーフィルタ F I Lの染料の液晶組成 物層 L Cへの漏洩の防止、 および、 カラ一フィルタ F I L、 遮光膜 B Mによる段差の平坦化のために設けられている。 ォ一バーコ一 ト 膜 0 Cはたとえばァク リ ル樹脂、 エポキシ樹脂等の透明樹脂材料で 形成されている。 また、 ォ一バーコ一 ト膜ォ C として、 流動性の良 ぃポリ イ ミ ド等の有機膜を使用しても良い。  The overcoat film 0C is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal composition layer LC, and to flatten the steps due to the color filter FIL and the light shielding film BM. The overcoat film 0C is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin. Further, as the bar coat film C, an organic film such as polyimide having good fluidity may be used.
《液晶層および偏向板》  《Liquid crystal layer and polarizing plate》
次に、 液晶層、 配向膜、 偏光板等について説明する。 液晶組成物 L C としては、誘電率異方性 Δ £が正でその値が 1 3. 2、 屈折率異方性 Δ η力、' 0. 0 8 1 ( 5 8 9 n m 2 0 °C) のネマ ティ ッ ク液晶を用いる。 液晶組成物層の厚み （ギャ ップ） は、 3. 8 とし、 リタデーシヨ ン Δ η · dは 0. 3 1 mとする。 この リ タデーシ ヨ ン Δ n · dの値 （屈折率異方性とギャ ップの組み合わ せ） は、 0. 2 5 〃 m以上から 0. 3 5 〃 mの間、 好ま しく は、 0. 2 8 i m以上から 0. 3 2 / mの間に設定し、 後述の偏光板と組み 合わせにより、 液晶分子の光軸が電界方向に配列したとき最大透過 率を得るこ とができ、 可視光の範囲ないで波長依存性がほとんどな い透過光を得るこ とができるよう にする。 Next, the liquid crystal layer, the alignment film, the polarizing plate, and the like will be described. For the liquid crystal composition LC, the dielectric anisotropy Δ £ is positive and its value is 13.2, the refractive index anisotropy Δη force, '0.081 (5.89 nm 20 ° C) The nematic liquid crystal is used. The thickness (gap) of the liquid crystal composition layer is set to 3.8, and the retardation Δη · d is set to 0.31 m. The value of this retardation Δn · d (combination of refractive index anisotropy and gap) is between 0.25 μm and 0.35 μm, preferably between 0.35 μm and 0.35 μm. By setting it between 28 im or more and 0.32 / m and combining with a polarizing plate described later, the maximum transmittance can be obtained when the optical axes of the liquid crystal molecules are arranged in the direction of the electric field. Thus, it is possible to obtain transmitted light having almost no wavelength dependence within the range described above.
また、 液晶組成物層の厚み （ギャ ップ） は、 ポリマビーズで制御 している。  The thickness (gap) of the liquid crystal composition layer is controlled by polymer beads.
なお、 液晶材料 L Cは、 特に限定したものではなく、 誘電率異方 性 Δ εは、 その値が大きいほうが、 駆動電圧が低減でき、 屈折率異 方性 Δη は小さいほう力 液晶層の厚み （ギャ ップ） を厚くでき、 液晶の封入時間が短縮され、 かつギャ ップばらつきを少なくするこ とができる。  Note that the liquid crystal material LC is not particularly limited. The larger the value of the dielectric anisotropy Δε, the lower the driving voltage can be, and the smaller the refractive index anisotropy Δη, the smaller the liquid crystal layer thickness ( The gap can be made thicker, the liquid crystal filling time can be shortened, and the gap variation can be reduced.
また、 液晶組成物の比抵抗としては、 1 0 9 Q c m以上 1 0 1 4 Ω c m以下、好ましく は 1 O ^ Q c m以上 1 0 1 3 Q c m以下のものを 用いる。 本方式では、 液晶組成物の抵抗が低くても、 画素電極と対 向電極間に充電された電圧を十分保持するこ とができ、 その下限は 1 09 Ω c m, 好ま しく は 1 O ^ Q c mである。 これは、 画素電極 と対向電極を、 同一基板上に構成しているこ とによる。 また、 抵抗 が高すぎると、 製造工程上に入った静電気を緩和しにく いため、 1 0 1 4 Q c m以下、 好ま しく は 1 0 1 3 Q c m以下が良い。 《配向膜》 As the specific resistance of the liquid crystal composition, 1 0 9 Q cm or more 1 0 1 4 Ω cm or less, preferably using the following 1 O ^ Q cm or more 1 0 1 3 Q cm. In this method, even if the resistance of the liquid crystal composition is low, it is sufficiently retained child a voltage charged between the pixel electrode and the counter counter electrode, the lower limit 1 0 9 Ω cm, the preferred properly 1 O ^ Q cm. This is because the pixel electrode and the counter electrode are configured on the same substrate. Further, when the resistance is too high, damage to difficulty alleviate static electricity entering the production process, 1 0 1 4 Q cm or less, preferred properly is 1 0 1 3 Q cm or less is good. 《Orientation film》
配向膜 A F としては、例えば、 日本合成ゴム（株）製ポリイ ミ ド（ J A L S 2 0 3 ) を用いる。 この配向膜は表面に疎水基 （例えば C H 3 ) が存在し、 液晶分子の長軸 （光軸） が基板面に垂直方向に配列 させるものである。 これにより、 電界無印加時に後述の偏光板との 組み合わせにより、 良好な黒レベルを表示する。 また、 本発明では、 ラ ビング処理は施さない。 このため、 ラ ビング処理に関わるラ ビン グされない部分ができるこ とによる表示不良領域の発生によるコン トラス ト比の低下や、 ラ ビング角度のばらつきによるむらの発生等 の不良をなくすこ とができる。  As the alignment film AF, for example, polyimide (JALS203) manufactured by Nippon Synthetic Rubber Co., Ltd. is used. This alignment film has a hydrophobic group (eg, CH 3) on the surface, and the major axis (optical axis) of the liquid crystal molecules is arranged in a direction perpendicular to the substrate surface. Thus, when no electric field is applied, a good black level is displayed by combination with a polarizing plate described later. In the present invention, no rubbing treatment is performed. Therefore, it is possible to eliminate defects such as a decrease in contrast ratio due to the occurrence of a display defect area due to the formation of a non-rubbing portion related to the rubbing process and unevenness due to a variation in the rubbing angle. .
《偏光板》  "Polarizer"
偏光板 P O L としては、 導電性を有する偏光板を用い、 下側の偏 光板 P O L 1 の偏光透過軸 MA X 1 を電界印加方向 （櫛歯電極の長 手方向と直交する方向） に対して約 4 5度の角度に設定し、 上側の 偏向板 P 0 L 2の偏光透過軸 M A X 2を、 それに直交させる。 F i g . 3にその関係を示している。 これにより、 作用に示した様な表 示を行う こ とができ、 印加される電圧 （画素電極 P Xと対向電極 C Tの間の電圧） を増加させるに伴い、 透過率が上昇するノーマリ ク ローズ特性を得るこ とができる。  As the polarizer POL, a conductive polarizer is used, and the polarization transmission axis MAX1 of the lower polarizer POL1 is set to about the electric field application direction (the direction orthogonal to the longitudinal direction of the comb-teeth electrode). Set the angle to 45 degrees, and make the polarization transmission axis MAX2 of the upper deflector P0L2 perpendicular to it. FIG. 3 shows the relationship. As a result, the display as shown in the operation can be performed, and the normally closed characteristic in which the transmittance increases as the applied voltage (the voltage between the pixel electrode PX and the counter electrode CT) increases. Can be obtained.
なお、 本実施例では、 偏光板に導電性を持たせるこ とにより、 外 部からの静電気による表示不良および E M I 対策を施している。 導 電性に関しては、 静電気による影響を対策するためだけであれば、 シー ト抵抗が 1 0 8 ΩΖ口以下、 Ε Μ Ι に対しても対策するのであ れば、 1 04 Ω /口以下とするのが望ま しい。 また、 ガラス基板の 液晶組成物の挟持面の裏面 （偏光板を粘着させる面） に導電層を設 けてもよい。 《位相差フ ィ ルム》 In this embodiment, measures are taken against display failure and EMI caused by static electricity from the outside by imparting conductivity to the polarizing plate. With respect to conductivity, if only to measure the effects of static electricity, sheet resistance 1 0 8 ΩΖ port below Nodea lever to measures against Ε Μ Ι, 1 0 4 Ω / mouth below It is desirable that Further, a conductive layer may be provided on the back surface (the surface on which the polarizing plate is adhered) of the sandwiching surface of the liquid crystal composition of the glass substrate. 《Phase difference film》
視角方向を変化させても、 本発明の様に垂直配向した状態で複屈 折位相差が発生しないよう に負の位相差フ イ ルム （ n x = n y > n z ) を用いる。 また、 わずかに発生する液晶材料の初期配向の傾き (基板面の法線方向からの傾き） を補正するために、 微少な正の位 相差フ イ ルム （ n x > n y = n z ) を用いる。 Be changed viewing direction, using a negative retardation off Lee Lum (n x = n y> n z) as double refraction phase difference in a state of being vertically aligned does not occur as in the present invention. Further, in order to correct the inclination of the initial orientation of the liquid crystal material to slightly occur (inclination from the normal direction of the substrate surface), a slight positive phase difference off Lee Lum (n x> n y = n z) Used.
本実施例では、 上側の偏光板と上側のガラス基板の間と、 下側の 偏光板と下側のガラス基板の間にそれぞれ、 負の位相差フ ィ ルム N R F 1、 N R F 2を設置した。 また、 上側の偏光板と上側のガラス 基板の間には、さ らに微少な正の位相差フ ィ ルム P R F も設置した。  In the present example, negative retardation films NRF1 and NRF2 were provided between the upper polarizing plate and the upper glass substrate and between the lower polarizing plate and the lower glass substrate, respectively. Further, between the upper polarizing plate and the upper glass substrate, a finer positive retardation film P RF was further provided.
2枚の負の位相差フィ ルム N R F 1、 N R F 2のリ タデ一ショ ン ( n x— n z = n y— n z ) は 0. 1 5 〃 mと した （合わせて 0. 3 m ) 。 これは、 液晶層の リ タデ一シ ヨ ンの約 1 Z 2 に設定する。 こ れにより、 全視角方向で良好な黑レベルを得るこ とができる。 また、 この負の位相差フ ィ ルムは、 どちらか 1枚でも良く 、 1 枚のみ使用 する ときは液晶層のリ タデーシ ヨ ンとほぼ同じにする。 ただし、 2 枚用いた方が、 全視角方向で良好な黒レベルを得るこ とができる。 Two negative retardation Fi Lum NRF 1, NRF 2 of Li Polygonum one sucrose emissions (n x - n z = n y - n z) was 0.1 5 〃 m (0. 3 combined m) . This is set to about 1 Z 2 of the retardation of the liquid crystal layer. As a result, it is possible to obtain a good 黑 level in all viewing angle directions. In addition, either one of the negative retardation films may be used, and when only one is used, the retardation film is almost the same as the retardation of the liquid crystal layer. However, better black level can be obtained in all viewing angle directions by using two sheets.
一方、 微少な正の位相差フ ィ ルム P R Fのリ タデ一 シ ヨ ン （ n x - n y = n x - n z ) は 0 . 0 5 ^ mと した。 また、 n xの方向は、 液 晶分子の光軸の基板面の法線方向からの僅かの傾き方向と直行させ る。 本実施例では水平方向にする。 これにより、 基板面の法線方向 からの僅かの傾きによる複屈折性が補償され、 さ らに、 全視角方向 で良好な黒レベルを得るこ とができる。 なお、 この微少な正の位相 差フ ィ ルム液晶分子の光軸が基板面の法線方向が全く一致する場合 は不要である。 On the other hand, Li knotweed one minute positive retardation full I Lum PRF Shi Yo emissions (n x - n y = n x - n z) was 0 0 5 ^ m.. The direction of n x is Ru is orthogonal to the slight inclination direction from the normal direction of the substrate surface of the optical axes of the liquid crystal molecules. In this embodiment, the horizontal direction is set. This compensates for birefringence due to a slight inclination of the substrate surface from the normal direction, and furthermore makes it possible to obtain a good black level in all viewing angle directions. Note that this is not necessary when the optical axis of the minute positive retardation film liquid crystal molecules exactly coincides with the normal direction of the substrate surface.
《マ ト リ クス周辺の構成》 F i g . 8は上下のガラス基板 S U B 1、 S U B 2を含む表示パ ネル P N Lのマ ト リ クス （ A R ) 周辺の要部平面を示す図である。 また、 F i g . 9は、 左側に走査回路が接続されるべき外部接続端 子 G T M付近の断面を、 右側に外部接続端子が無いところのシール 部付近の断面を示す図である。 《Structure around the matrix》 FIG. 8 is a diagram showing a plane of a main part around a matrix (AR) of a display panel PNL including upper and lower glass substrates SUB 1 and SUB 2. FIG. 9 is a view showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.
このパネルの製造では、 小さいサイズであればスループッ 卜向上 のため 1枚のガラス基板で複数個分のデバイスを同時に加工してか ら分割し、 大きいサイズであれば製造設備の共用のためどの品種で も標準化された大きさのガラス基板を加工してから各品種に合った サイズに小さ く し、 いずれの場合も一通りの工程を経てからガラス を切断する。 F i g . 8 , F i g . 9は後者の例を示すもので、 F i g . 8、 F i g . 9の両図とも上下基板 S U B 1、 S U B 2の切 断後を表しており、 L Nは両基板の切断前の縁を示す。 いずれの場 合も、完成状態では外部接続端子群 T g、 T dおよび端子 C O T (添 字略） が存在する （図で上辺と左辺の） 部分はそれらを露出するよ うに上側基板 S U B 2の大きさが下側基板 S U B 1 より も内側に制 限されている。 端子群 T g、 T dはそれぞれ後述する走査回路接続 用端子 G T M、 映像信号回路接続用端子 D T Mとそれらの引出配線 部を集積回路チップ C H I が搭載されたテープキヤ リアパッ ケー ジ T C P ( F i g . 1 9、 F i g . 2 0 ) の単位に複数本まとめて名 付けたものである。 各群のマ ト リ クス部から外部接続端子部に至る までの引出配線は、 両端に近づく につれ傾斜している。 これは、 パ ッケージ T C Pの配列ピッチ及び各パッケージ T C Pにおける接続 端子ピッチに表示パネル P N Lの端子 D T M、 G T Mを合わせるた めである。 また、 対向電極端子 C O Tは、 対向電極 C Tに対向電圧 を外部回路から与えるための端子である。 マ ト リ クス部の対向電圧 信号線 C Lは、 走査回路用端子 G T Mの反対側 （図では右側） に引 き出し、 各対向電圧信号線を共通バスライ ン C Bで一纏めにして、 対向電極端子 C O Tに接続している。 Which varieties for this panel in the production of, and at the same time processing the plurality fraction of the device in one glass substrate for long if throughput Bok improved small size or we were divided, manufacturing facilities if large size shared However, a glass substrate of a standardized size is processed and then reduced to a size suitable for each product type. In each case, the glass is cut after a single process. Fig. 8 and Fig. 9 show the latter example, and both Figs. 8 and 9 show the upper and lower substrates SUB1 and SUB2 after cutting, and LN shows both. 2 shows an edge of a substrate before cutting. In any case, in the completed state, the external connection terminal groups T g and T d and the terminal COT (subscript omitted) exist (the upper and left sides in the figure) are exposed on the upper substrate SUB 2 so that they are exposed. The size is limited inside the lower substrate SUB1. The terminal groups Tg and Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, and their lead-out wiring portions, which will be described later, are tape carrier packages TCP (Fig. 1) on which an integrated circuit chip CHI is mounted. 9, Fig. 20) is a group of multiple units. The lead wiring from the matrix part of each group to the external connection terminal part is inclined as approaching both ends. This is because the terminals DTM and GTM of the display panel PNL are matched to the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP. The counter electrode terminal COT is a terminal for applying a counter voltage to the counter electrode CT from an external circuit. Opposite voltage of matrix part The signal line CL is drawn out to the opposite side (right side in the figure) of the scanning circuit terminal GTM, and the common voltage signal lines are grouped together by a common bus line CB and connected to the common electrode terminal COT.
透明ガラス基板 S U B 1、 S U B 2の間にはその縁に沿って、 液 晶封入口 I N J を除き、液晶 L Cを.封止するよう にシールパターン S Lが形成される。 シール材は例えばエポキシ樹脂から成る。  A seal pattern SL is formed between the transparent glass substrates SUB1 and SUB2 along the edges of the transparent glass substrates SUB1 and SUB2 so as to seal the liquid crystal LC except for the liquid crystal inlet INJ. The sealing material is made of, for example, an epoxy resin.
配向膜〇 R I 1、 〇 R I 2の層は、 シールパターン S Lの内側に 形成される。 偏光板 P O L 1、 P O L 2 はそれぞれ下部透明ガラス 基板 S U B 1 、 上部透明ガラス基板 S U B 2の外側の表面に構成さ れている。 液晶 L Cは液晶分子の向きを設定する下部配向膜 0 R I 1 と上部配向膜 0 R I 2 との間でシールパターン S Lで仕切られた 領域に封入されている。 下部配向膜 O R I 1 は下部透明ガラス基板 S U B 1側の保護膜 P S V 1 の上部に形成される。  The layers of the alignment films 〇 RI 1 and 〇 RI 2 are formed inside the seal pattern SL. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively. The liquid crystal LC is sealed in a region partitioned by the seal pattern SL between the lower alignment film 0RI1 and the upper alignment film 0RI2 for setting the direction of the liquid crystal molecules. The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.
この液晶表示装置は、 下部透明ガラス基板 S U B 1側、 上部透明 ガラス基板 S U B 2側で別個に種々の層を積み重ね、 シールパター ン S Lを基板 S U B 2側に形成し、 下部透明ガラス基板 S U B 1 と 上部透明ガラス基板 S U B 2 とを重ね合わせ、 シール材 S Lの開口 部 I N J から液晶 L Cを注入し、 注入口 I N J をエポキシ樹脂など で封止し、 上下基板を切断するこ とによって組み立てられる。  In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB 1 side and the upper transparent glass substrate SUB 2 side, and a seal pattern SL is formed on the substrate SUB 2 side. It is assembled by superimposing the upper transparent glass substrate SUB2, injecting liquid crystal LC through the opening INJ of the sealing material SL, sealing the inlet INJ with epoxy resin, and cutting the upper and lower substrates.
《ゲ一 卜端子部》  《Gate terminal section》
F i g . 1 0 は表示マ ト リ クスの走査信号線 G Lからその外部接 続端子 G T Mまでの接続構造を示す図であり、 F i g . 1 0 — Aは 平面であり F i g . 1 0 — Bは F i g . 1 0 — Aの B — B切断線に おける断面を示している。 なお、 同図は F i g . 8下方付近に対応 し、 斜め配線の部分は便宜状一直線状で表した。  10. FIG. 10 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, wherein FIG. 10 — A is a plane and FIG. 10 — B shows the cross section of the Fig. 10 — A cut at the B — B section line. The figure corresponds to the vicinity of FIG. 8 below, and the diagonal wiring portion is represented by a straight line for convenience.
図中 C r — M o層 g 3は、判り易 く するためハッチを施してある。 ゲ一 卜端子 G TMは C r 一 M o層 g 3 と、更にその表面を保護し、 かつ、 T C P ( T a p e C a r r i e r P a c k e g e ) との 接続の信頼性を向上させるための透明導電層 i 1 とで構成されてい る。 この透明導電層 i 1 は画素電極 P Xと同一工程で形成された透 明導電膜 I T〇を用いている。 In the figure, the Cr-Mo layer g3 is hatched for easy understanding. The gate terminal G TM is a transparent conductive layer i for improving the reliability of the connection between the Cr-Mo layer g 3 and the surface of the Cr-Mo layer g 3 and the TCP (Tape Carrier Package). It consists of one and one. The transparent conductive layer i1 uses a transparent conductive film IT # formed in the same step as the pixel electrode PX.
平面図において、 絶縁膜 G I および保護膜 P S V 1 はその境界線 より も右側に形成されており、 左端に位置する端子部 G TMはそれ らから露出し外部回路との電気的接触ができるよう になっている。 図では、 ゲ一 ト線 G L とゲ一 ト端子の一つの対のみが示されている が、 実際はこのような対が F i g . 8に示すよう に上下に複数本並 ベられ端子群 T g ( F i g . 8 ) が構成され、 ゲー ト端子の左端は、 製造過程では、 基板の切断領域を越えて延長され配線 S H g (図示 せず） によつて短絡される。 製造過程における配向膜 O R I 1 のラ ビング時等の静電破壊防止に役立つ。  In the plan view, the insulating film GI and the protective film PSV1 are formed on the right side of the boundary line, and the terminal portion GTM located on the left end is exposed therefrom so that it can make electrical contact with an external circuit. Has become. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, such pairs are arranged in a row at the top and bottom as shown in FIG. 8, and the terminal group T g (FIG. 8) is formed, and the left end of the gate terminal is extended beyond the cut area of the substrate in the manufacturing process and is short-circuited by the wiring SH g (not shown). This is useful for preventing electrostatic breakdown during rubbing of the alignment film ORI1 in the manufacturing process.
《 ドレイ ン端子 D T M》  《Drain terminal D T M》
F i g . 1 1 は映像信号線 D Lからその外部接続端子 D TMまで の接続を示す図であり、 F i g . 1 1 — Aはその平面を示し、 F i g . l l — Bは F i g . 1 1 _ Aの B— B切断線における断面を示 す。 なお、 同図は F i g . 8右上付近に対応し、 図面の向きは便宜 上変えてあるが右端方向が基板 S U B 1 の上端部に該当する。  11 is a diagram showing the connection from the video signal line DL to its external connection terminal DTM, FIG. 11 1 —A indicates the plane, and FIG. Ll — B indicates FIG. 1 Shows a cross section of 1 _ A at B-B section line. 8 corresponds to the vicinity of the upper right of FIG. 8 and the direction of the drawing is changed for convenience, but the right end corresponds to the upper end of the substrate SUB1.
T S T dは検査端子でありここには外部回路は接続されないが、 プローブ針等を接触できるよう配線部より幅が広げられている。 同 様に、 ドレイ ン端子 D T Mも外部回路との接続ができるよう配線部 より幅が広げられている。 外部接続 ドレイ ン端子 D T Mは上下方向 にに配列され、 ドレイ ン端子 D TMは、 F i g . 5に示すよう に端 子群 T d (添字省略） を構成し基板 S U B 1の切断線を越えて更に 延長され、 製造過程中は静電破壊防止のためその全てが互いに配線TST d is a test terminal, which is not connected to an external circuit, but is wider than the wiring part so that probe needles can be contacted. Similarly, the drain terminal DTM is wider than the wiring part so that it can be connected to external circuits. The external connection drain terminals DTM are arranged in the vertical direction, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and extend beyond the cutting line of the substrate SUB1. Further All of them are wired together to prevent electrostatic breakdown during the manufacturing process.
S H d (図示せず） によって短絡される。 検査端子 T S T dは F i g . 1 1 に示すように一本置きの映像信号線 D Lに形成される。 Shorted by S H d (not shown). The inspection terminal TSTd is formed on every other video signal line DL as shown in FIG. 11.
ドレイ ン接続端子 D T Mは透明導電層 i 1で形成されており、 保 護膜 P S V I を除去した部分で映像信号線 D L と接続されている。 この透明導電膜 ί 1 はゲー ト端子 G T Mの時と同様に画素電極 Ρ Χ と同一工程で形成された透明導電膜 I T Oを用いている。  The drain connection terminal DTM is formed of the transparent conductive layer i1, and is connected to the video signal line DL at a portion where the protective film PSVI is removed. This transparent conductive film # 1 uses a transparent conductive film ITO formed in the same step as the pixel electrode 同 様, as in the case of the gate terminal GTM.
マ ト リ クス部から ドレイ ン端子部 D T Mまでの引出配線は、 映像 信号線 D Lと同じレベルの層 d 3が構成されている。  The lead-out wiring from the matrix part to the drain terminal part DTM has a layer d3 at the same level as the video signal line DL.
《対向電極端子 C T M》  《Counter electrode terminal C T M》
F i g . 1 2は対向電圧信号線 CLからその外部接続端子 C T M までの接続を示す図であり、 F i g . 1 2 — Aはその平面を示し、 F i g . 1 2 — Bは F 】' g . 1 2 — Aの B — B切断線における断面 を示す。 なお、 同図は F i g . 8左上付近に対応する。  Fig. 1 2 is a diagram showing the connection from the counter voltage signal line CL to its external connection terminal CTM, Fig. 1 2 —A indicates the plane, and Fig. 1 2-B is F] '. g. 1 2 — Shows the cross section of A along the line B — B The figure corresponds to the vicinity of the upper left of FIG.
各対向電圧信号線 C Lは共通バスライ ン C B 1で一纏めして対向 電極端子 C T Mに引き出されている。 共通バスライ ン C Bは導電層 g 3の上に導電層 3を積層し、 透明導電層 i 1 でそれらを電気的に 接続した構造となっている。 これは、 共通バスライ ン C Bの抵抗を 低減し、 対向電圧が外部回路から各対向電圧信号線 C Lに十分に供 給されるようにするためである。 本構造では、 特に新たに導電層を 負荷するこ となく、 共通バスライ ンの抵抗を下げられるのが特徴で ある。  The common voltage signal lines CL are collectively connected to a common bus line CB1 and are led to a common electrode terminal CTM. The common bus line CB has a structure in which a conductive layer 3 is laminated on a conductive layer g3 and they are electrically connected by a transparent conductive layer i1. This is to reduce the resistance of the common bus line CB so that the opposing voltage is sufficiently supplied from an external circuit to each opposing voltage signal line CL. The feature of this structure is that the resistance of the common bus line can be reduced without any additional load on the conductive layer.
対向電極端子 C T Mは、 導電層 g 3の上に透明導電層 i 1が積層 された構造になっている。 この透明導電膜 i 1 は他の端子の時と同 様に画素電極 P Xと同一工程で形成された透明導電膜 I T 0を用い ている。 透明導電層 i 1 により、 その表面を保護し、 電食等を防ぐ ために耐久性のよい透明導電層 i lで、 導電層 g 3を覆っている。 また透明導電層 i 1 と導電層 g 3および導電層 d 3 との接続は保護 膜 P S V 1 および絶縁膜 G I にうスルーホールを形成し導通を取つ ている。 The counter electrode terminal CTM has a structure in which a transparent conductive layer i1 is laminated on a conductive layer g3. This transparent conductive film i 1 uses the transparent conductive film IT 0 formed in the same process as the pixel electrode PX, as in the case of the other terminals. Transparent conductive layer i 1 protects its surface and prevents electrolytic corrosion Therefore, the conductive layer g3 is covered with a transparent conductive layer il having high durability. The connection between the transparent conductive layer i 1 and the conductive layer g 3 and the conductive layer d 3 is formed by forming through holes in the protective film PSV 1 and the insulating film GI to establish conduction.
一方、 F i g . 1 3は対向電圧信号線 CLのもう一方の端からそ の外部接続端子 C T M 2までの接続を示す図であり、 F i g . 1 3 — Aはその平面を示し、 F i g . 1 3 — Bは F i g . 1 3 — Aの B 一 B切断線における断面を示す。 なお、 同図は F i g . 5右上付近 に対応する。 ここで、 共通バスライ ン C B 2では各対向電圧信号線 C Lのもう一方の端 （ゲ一 ト端子 G T M側） をで一纏めして対向電 極端子 C T M 2に引き出されている。 共通バスライ ン C B 1 と異な る点は、 走査信号線 G L とは絶縁されるよう に、 導電層 d 3 と透明 導電層 i 1 で形成しているこ とである。 また、 走査信号線 G Lとの 絶縁は絶縁膜 G I で行っている。  On the other hand, FIG. 13 is a diagram showing the connection from the other end of the counter voltage signal line CL to its external connection terminal CTM 2, and FIG. 13—A shows the plane, and FIG. 1 3 — B shows the cross section of Fig. 1 3 — A taken along section line B-B. The figure corresponds to the vicinity of the upper right in FIG. 5. Here, in the common bus line CB2, the other end (gate terminal GTM side) of each counter voltage signal line CL is brought together to be drawn to the counter electrode terminal CTM2. The difference from the common bus line CB1 is that the common bus line CB1 is formed of a conductive layer d3 and a transparent conductive layer i1 so as to be insulated from the scanning signal line GL. Insulation with the scanning signal line GL is performed by the insulating film GI.
《表示装置全体等価回路》  《Equivalent circuit of entire display device》
表示マ ト リ クス部の等価回路とその周辺回路の結線図を F i g . 1 4に示す。 同図は回路図ではあるが、 実際の幾何学的配置に対応 して描かれている。 A Rは複数の画素を二次元状に配列したマ ト リ クス · アレイである。  Fig.14 shows the connection diagram of the equivalent circuit of the display matrix and its peripheral circuits. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.
図中、 Xは映像信号線 D Lを意味し、 添字 G、 Bおよび Rがそれ ぞれ緑、 青および赤画素に対応して付加されている。 Yは走査信号 線 G Lを意味し、 添字 1、 2、 3、 ···、 end は走査タイ ミ ングの順 序に従つて付加されている。  In the figure, X represents a video signal line DL, and suffixes G, B, and R are added corresponding to green, blue, and red pixels, respectively. Y means the scanning signal line GL, and the subscripts 1, 2, 3,..., End are added according to the order of the scanning timing.
走査信号線 Y (添字省略） は垂直走査回路 Vに接続されており、 映像信号線 X (添字省略）は映像信号駆動回路 Hに接続されている。  The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.
S U Pは 1つの電圧源から複数の分圧した安定化された電圧源を 得るための電源回路やホス 卜 （上位演算処理装置）からの C R T (陰 極線管） 用の情報を T F T液晶表示装置用の情報に交換する回路を 含む回路である。 SUP provides multiple divided and stabilized voltage sources from one voltage source. It is a circuit that includes a power supply circuit for obtaining the information and a circuit for exchanging information for the cathode ray tube (CRT) from the host (higher-level processing unit) with information for the TFT LCD.
《駆動方法》  《Driving method》
F i g . 1 5に本実施例の液晶表示装置の駆動波形を示す。 対向 電圧 V cは一定電圧とする。走査信号 V gは 1 走査期間ごとに、 オン レベルをとり、 その他はオフレベルをとる。 映像信号電圧は、 液晶 層に印加したい電圧の 2倍の振幅で正極と負極を 1 フ レーム毎に反 転して 1つの画素に伝えるよう に印加する。 ここで、 映像信号電圧 V dは 1列毎に極性を反転し、 2行毎にも極性を反転する。 これに より、 極性が反転した画素が上下左右にとなりあう構成となり、 フ リ ッカ、 クロス トーク （スミア） を発生しにく くすることができる。 また、対向電圧 V cは映像信号電圧の極性反転のセンター電圧から、 一定量さげた電圧に設定する。 これは、 薄膜 トラ ンジスタ素子がォ ンからオフに変わるときに発生するフィ 一 ドスルー電圧を補正する ものであり、 液晶に直流成分の少ない交流電圧を印加するために行 う。 液晶は直流が印加されると、 残像、 劣化等が激しくなる。 FIG. 15 shows a driving waveform of the liquid crystal display device of this embodiment. The counter voltage Vc is a constant voltage. Scanning signal V g in each scanning period, takes on level, others take off level. The video signal voltage is applied so that the positive and negative poles are inverted every frame and transmitted to one pixel with twice the amplitude of the voltage to be applied to the liquid crystal layer. Here, the polarity of the video signal voltage Vd is inverted every column, and the polarity is also inverted every two rows. As a result, the pixels whose polarities are inverted are arranged vertically and horizontally, so that flicker and crosstalk (smear) can be suppressed. Further, the counter voltage Vc is set to a voltage which is a certain amount lower than the center voltage of the polarity inversion of the video signal voltage. This is to correct the feedthrough voltage generated when the thin film transistor element changes from ON to OFF, and is performed to apply an AC voltage having a small DC component to the liquid crystal. When a direct current is applied to a liquid crystal, afterimages, deterioration, and the like become severe.
また、 この他に、 対向電圧は交流化するこ とで映像信号電圧の最 大振幅を低減でき、 映像信号駆動回路 （信号側 ドライバ） に耐圧の 低いものを用いるこ とも可能である。  In addition, the maximum amplitude of the video signal voltage can be reduced by converting the counter voltage into an alternating current, and a low withstand voltage signal can be used for the video signal drive circuit (signal-side driver).
《蓄積容量 C stgの働き》  << Function of storage capacity C stg >>
蓄積容量 C stg は、 画素に書き込まれた （薄膜 トラ ンジスタ T F Tがオフした後の） 映像情報を、 長く蓄積するために設ける。 本発 明で用いている電界を基板面と平行に印加する方式では、 電界を基 板面に垂直に印加する方式と異なり、 画素電極と対向電極で構成さ れる容量 （いわゆる液晶容量） がほとんど無いため、 蓄積容量 C stg が映像情報を画素に蓄積するこ とができない。 したがって、 電界を 基板面と平行に印加する方式では、 蓄積容量 Cstg は必須の構成要 素である。 The storage capacitor C stg is provided to store video information (after the thin-film transistor TFT is turned off) written to the pixel for a long time. In the method of applying an electric field parallel to the substrate surface used in the present invention, unlike the method of applying an electric field perpendicular to the substrate surface, most of the capacitance (so-called liquid crystal capacitance) composed of the pixel electrode and the counter electrode is used. No storage capacity C stg Cannot store video information in pixels. Therefore, in a system in which an electric field is applied in parallel with the substrate surface, the storage capacitance Cstg is an essential component.
また、 蓄積容量 Cstg は、 薄膜 トランジスタ T F Tがスィ ッチン グするとき、画素電極電位 Vsに対するゲ一 ト電位変化 AVgの影響 を低減するよう にも働く。 この様子を式で表すと、次のようになる。  The storage capacitor Cstg also works to reduce the influence of the gate potential change AVg on the pixel electrode potential Vs when the thin film transistor TFT switches. This situation is represented by the following equation.
Δ V s= {C gs/(C gs+C stg+ C pix)} x Δ V g  Δ V s = {C gs / (C gs + C stg + C pix)} x Δ V g
ここで、 C gsは薄膜 トラ ンジスタ T F Tのゲ一 ト電極 G Tとソ一 ス電極 S D 1 との間に形成される寄生容量、 Cpix は画素電極 P X と対向電極 C Tとの間に形成される容量、 AVsは AVgによる画素 電極電位の変化分いわゆるフィー ドスル一電圧を表わす。 この変化 分 AVs は液晶 L Cに加わる直流成分の原因となるが、 保持容量 C stg を大き くすればする程、 その値を小さ くすることができる。 液 晶 L Cに印加される直流成分の低減は、 液晶 L Cの寿命を向上し、 液晶表示画面の切り替え時に前の画像が残るいわゆる焼き付きを低 減するこ とができる。  Here, C gs is a parasitic capacitance formed between the gate electrode GT of the thin-film transistor TFT and the source electrode SD 1, and Cpix is a capacitance formed between the pixel electrode PX and the counter electrode CT. AVs represents a so-called feed-through voltage corresponding to a change in pixel electrode potential due to AVg. The change AVs causes a DC component applied to the liquid crystal LC, but the value can be reduced as the storage capacitance C stg is increased. The reduction of the DC component applied to the liquid crystal LC improves the life of the liquid crystal LC, and reduces the so-called burn-in in which the previous image remains when switching the liquid crystal display screen.
前述したように、 ゲー ト電極 G Tは i 型半導体層 A Sを完全に覆 う よう大き く されている分、 ソース電極 S D 1、 ドレイ ン電極 S D 2 とのオーバラ ップ面積が増え、従って寄生容量 C gsが大き く なり、 画素電極電位 Vsはゲー ト （走査）信号 Vgの影響を受け易く なると いう逆効果が生じる。 しかし、 蓄積容量 Cstg を設けることにより このデメ リ ッ トも解消するこ とができる。 As described above, since the gate electrode GT is made large to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance is increased. C gs increases, and the pixel electrode potential Vs has an adverse effect of being easily affected by the gate (scan) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cstg.
《製造方法》  "Production method"
つぎに、 上述した液晶表示装置の基板 S U B 1側の製造方法につ いて F i g . 1 6〜 F i g . 1 8を参照して説明する。 なお同図に おいて、 中央の文字は工程名の略称であり、 左側は F i g . 6に示 す薄膜 トラ ンジスタ T F T部分、 右側は F i g . 1 0に示すゲ一 ト 端子付近の断面形状でみた加工の流れを示す。 工程 B、 工程 Dを除 き工程 A〜工程 I は各写真処理に対応して区分けしたもので、 各ェ 程のいずれの断面図も写真処理後の加工が終わり フ ォ 卜 レジス 卜を 除去した段階を示している。 なお、 写真処理とは本説明ではフ ォ ト レジス 卜の塗布からマスクを使用した選択露光を経てそれを現像す るまでの一連の作業を示すものとし、 繰返しの説明は避ける。 以下 区分けした工程に従って、 説明する。 Next, a method of manufacturing the above-described liquid crystal display device on the substrate SUB 1 side will be described with reference to FIGS. 16 to 18. In the same figure, the middle letter is the abbreviation of the process name, and the left side is shown in Fig. 6. The thin film transistor TFT part, the right side shows the processing flow viewed from the cross-sectional shape near the gate terminal shown in Fig. 10. Processes A to I were classified according to each photographic process except process B and process D. All cross-sectional views of each process were completed after photographic process and the photo resist was removed. Shows the stages. In this description, photographic processing refers to a series of operations from application of a photo resist, through selective exposure using a mask to development of the resist, and a repeated description is omitted. The following is an explanation according to the divided steps.
工程 A、 F i g . 1 6  Process A, Fig. 1 6
A N 6 3 5ガラス （商品名） からなる下部透明ガラス基板 S U B 1上に膜厚が 2 0 0 0 人の C r _ M o等からなる導電膜 g 3をスパ ッタ リ ングにより設ける。 写真処理後、 硝酸第 2セリ ウムアンモン で導電膜 g 3を選択的にエッチングする。 それによつて、 ゲー ト電 極 G T、 走査信号線 G L、 対向電圧信号線 Cし、 ゲ一 ト端子 G TM、 共通バスライ ン C B 1 の第 1導電層、 対向電極端子 C TM 1 の第 1 導電層、 ゲ一 ト端子 G T Mを接続するバスライ ン S H g (図示せず） を形成する。  On the lower transparent glass substrate SUB 1 made of A N 635 glass (trade name), a conductive film g 3 made of Cr—Mo and having a thickness of 2000 is provided by sputtering. After the photographic processing, the conductive film g3 is selectively etched with ceric ammonium nitrate. Accordingly, the gate electrode GT, the scanning signal line GL, the counter voltage signal line C, the gate terminal GTM, the first conductive layer of the common bus line CB1, and the first conductive layer of the counter electrode terminal CTM1. A bus line SH g (not shown) connecting the layer and the gate terminal GTM is formed.
工程 B、 F i g . 1 6  Process B, Fig. 1 6
プラズマ C V D装置にアンモニアガス、 シラ ンガス、 窒素ガスを 導入して、 膜厚が 3 5 0 O Aの窒化 S i 膜を設け、 プラズマ C V D 装置にシラ ンガス、 水素ガスを導入して、 膜厚が 1 2 0 0 Aの i 型 非晶質 S i 膜を設けたのち、 プラズマ C V D装置に水素ガス、 ホス フィ ンガスを導入して、 膜厚が 3 0 O Aの N(+)型非晶質 S i 膜を 設ける。  Ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD apparatus, and a 350 OA-thick Si nitride film was provided. By introducing silane gas and hydrogen gas into the plasma CVD apparatus, After an i-type amorphous Si film of 200 A is provided, hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus, and an N (+)-type amorphous Si film having a thickness of 30 OA is formed. Provide a membrane.
工程 C、 F i g . 1 6  Process C, Fig. 1 6
写真処理後、 ドライエッチングガスとして S F6、 C C 1 4を使用 して N( + )型非晶質 S i 膜、 i 型非晶質 S i 膜を選択的にエツチン グするこ とにより、 i 型半導体層 A Sの島を形成する。 After photo processing, use SF6 and CC14 as dry etching gas Then, an island of the i-type semiconductor layer AS is formed by selectively etching the N (+)-type amorphous Si film and the i-type amorphous Si film.
工程 D、 F i g . 1 7  Process D, Fig. 1 7
膜厚が 3 0 0人の C rからなる導電膜 d 3をスパッタ リ ングによ り設ける。 写真処理後、 導電膜 d 3を工程 Aと同様な液でエツチン グし、 映像信号線 D L、 ソース電極 S D 1 、 ドレイ ン電極 S D 2、 共通バスライ ン C B 2の第 1導電層，および ドレイ ン端子 D T Mを 短絡するバスライ ン S H d (図示せず） を形成する。 つぎに、 ドラ ィエッチング装置に C C 1 4、 S F6を導入して、 N(+)型非晶質 S i 膜をエッチングするこ とにより、 ソースと ドレイ ン間の N ( + )型 半導体層 d Oを選択的に除去する。 導電膜 d 3をマスクパターンで パターニングした後、 導電膜 d 3をマスク と して、 N(+)型半導体 層 d Oが除去される。 つま り、 i 型半導体層 A S上に残っていた N (+)型半導体層 d 0は導電膜 d 1 、 導電膜 d 2以外の部分がセルフ ァライ ンで除去される。 このとき、 N( + )型半導体層 d 0はその厚 さ分は全て除去されるようエッチングされるので、 i 型半導体層 A S も若干その表面部分がェッチングされるが、 その程度はェッチン グ時間で制御すればよい。  A conductive film d3 made of Cr having a thickness of 300 is formed by sputtering. After the photographic processing, the conductive film d3 is etched with the same liquid as in step A, and the first conductive layer of the video signal line DL, the source electrode SD1, the drain electrode SD2, the common bus line CB2, and the drain are formed. Form a bus line SH d (not shown) that shorts the terminal DTM. Next, the N (+)-type semiconductor layer between the source and the drain is etched by introducing CC14 and SF6 into the dry etching apparatus and etching the N (+)-type amorphous Si film. d O is selectively removed. After patterning the conductive film d3 with the mask pattern, the N (+) type semiconductor layer dO is removed using the conductive film d3 as a mask. In other words, in the N (+)-type semiconductor layer d0 remaining on the i-type semiconductor layer AS, portions other than the conductive film d1 and the conductive film d2 are removed by self-alignment. At this time, since the N (+)-type semiconductor layer d0 is etched so as to remove all of its thickness, the i-type semiconductor layer AS is also slightly etched at its surface, but the extent is the etching time. Can be controlled by
工程 E . F i . 1 7  Process E. F i. 1 7
プラズマ C V D装置にアンモニアガス、 シラ ンガス、 窒素ガスを 導入して、 膜厚が 0.4 //mの窒化 S i 膜を設ける。 写真処理後、 ド ライエッチングガスとして S F6 を使用して窒化 S i 膜を選択的に エッチングするこ とによって、 保護膜 P S V 1および絶縁膜 G I を パ夕一ニングする。 ここで、 保護膜 P S V 1 と絶縁膜 G I は同一ホ トマスクでパターニングされ、 一括で加工される。  Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD device to provide a 0.4 // m thick nitrided Si film. After the photoprocessing, the passivation of the protective film PSV1 and the insulating film GI is performed by selectively etching the nitrided Si film using SF6 as a dry etching gas. Here, the protective film PSV1 and the insulating film GI are patterned with the same photomask and are processed collectively.
工程 G、 F i g . 1 8 膜厚が 1 4 0 0人の I T 0膜からなる透明導電膜 i 1 をスパッタ リ ングにより設ける。 写真処理後、 エッチング液として塩酸と硝酸 との混酸液で透明導電膜 i 1 を選択的にエッチングすることにより、 ゲー ト端子 G T Mの最上層、 ドレイ ン端子 D T Mおよび対向電極端 子 C T M 1 および C T M 2の第 2導電層を形成する。 Process G, Fig. 1 8 A transparent conductive film i1 composed of an IT0 film having a thickness of 1,400 people is provided by sputtering. After the photographic processing, the transparent conductive film i 1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, so that the top layer of the gate terminal GTM, the drain terminal DTM, and the counter electrode terminals CTM 1 and CTM A second conductive layer is formed.
《表示パネル P N Lと駆動回路基板 P C B 1》  《Display panel PNL and drive circuit board PCB1》
F i g . 1 9は、 F i g . 8等に示した表示パネル P N Lに映像 信号駆動回路 Hと垂直走査回路 Vを接続した状態を示す上面図であ る。  FIG. 19 is a top view showing a state where the video signal drive circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.
C H I は表示パネル P N Lを駆動させる駆動 I Cチップ （下側の 5個は垂直走査回路側の駆動 I Cチップ、 左の 1 0個ずつは映像信 号駆動回路側の駆動 I Cチップ） である。 T C Pは F i g . 1 6、 F i g . 1 7で後述するよう に駆動用 I Cチップ C H I がテープ . オー トメイティ ド · ボンディ ング法 （ T A B ) により実装されたテ —プキャ リアパッケージ、 P C B 1 は上記 T C Pやコンデンサ等が 実装された駆動回路基板で、 映像信号駆動回路用と走査信号駆動回 路用の 2つに分割されている。 F G Pはフレームグラン ドパッ ドで あり、 シールドケース S H Dに切り込んで設けられたバネ状の破片 が半田付けされる。 F Cは下側の駆動回路基板 P C B 1 と左側の駆 動回路基板 P C B 1 を電気的に接続するフラ ッ トケ一ブルである。 フラ ッ トケーブル F C としては図に示すよう に、複数のリー ド線（り ん青銅の素材に S n鍍金を施したもの） をス トライプ状のポリエチ レン層とポリ ビニルアルコール層とでサン ドィ ツチして支持したも のを使用する。  CHI is the driving IC chip for driving the display panel PNL (the lower five driving IC chips on the vertical scanning circuit side, and each of the left ten driving IC chips on the video signal driving circuit side). As described later in Fig. 16 and Fig. 17, TCP is a carrier package in which the driving IC chip CHI is mounted by tape automated bonding (TAB). This is a drive circuit board on which TCPs, capacitors, etc. are mounted. It is divided into two parts, one for the video signal drive circuit and the other for the scan signal drive circuit. FGP is a frame ground pad, and a spring-like fragment provided by cutting into the shield case SHD is soldered. FC is a flat cable for electrically connecting the lower drive circuit board PCB1 to the left drive circuit board PCB1. As shown in the figure, the flat cable FC is made up of a striped polyethylene layer and a polyvinyl alcohol layer consisting of striped polyethylene (tin bronze material with Sn plating). Use the one that is supported by the switch.
《 T C Pの接続構造》  《TCP connection structure》
F i g . 2 0は走査信号駆動回路 Vや映像信号駆動回路 Hを構成 する、 集積回路チップ C H I がフ レキシブル配線基板に搭載された テープキャ リアパッケージ T C Pの断面構造を示す図であり、 F i g . 2 1 はそれを液晶表示パネルの、 本例では走査信号回路用端子 GT Mに接続した状態を示す要部断面図である。 Fig. 20 constitutes the scanning signal drive circuit V and the video signal drive circuit H FIG. 21 shows a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI is mounted on a flexible wiring board, and FIG. 21 shows the cross-sectional structure of a liquid crystal display panel, in this example, a scanning signal circuit terminal GT. FIG. 4 is a cross-sectional view of a main part showing a state connected to M.
同図において、 T T Bは集積回路 C H I の入力端子 · 配線部であ り、 T T Mは集積回路 C H I の出力端子 · 配線部であり、 例えば C uから成り、 それぞれの内側の先端部 （通称イ ンナ一 リー ド） には 集積回路 C H I のボンディ ングパッ ド P A Dがいわゆるフヱースダ ゥンボンディ ング法により接続される。 端子 T T B、 T T Mの外側 の先端部 （通称アウターリー ド） はそれぞれ半導体集積回路チップ C H I の入力及び出力に対応し、 半田付け等により C R TZT F T 変換回路 · 電源回路 S U Pに、 異方性導電膜 A C Fによって液晶表 示パネル P N Lに接続される。 パッケージ T C Pは、 その先端部が パネル P N L側の接続端子 GT Mを露出した保護膜 P S V 1 を覆う ようにパネルに接続されており、 従って、 外部接続端子 GTM (D T M) は保護膜 P S V 1かパッケージ T C Pの少なく とも一方で覆 われるので電触に対して強く なる。  In the same figure, TTB is an input terminal and a wiring portion of the integrated circuit CHI, and TTM is an output terminal and a wiring portion of the integrated circuit CHI. The lead pad is connected to the bonding pad PAD of the integrated circuit CHI by the so-called phase-bonding method. The outer ends of the terminals TTB and TTM (commonly called outer leads) correspond to the inputs and outputs of the semiconductor integrated circuit chip CHI, respectively. CR TZT FT conversion circuits and power supply circuits Connected to the liquid crystal display panel PNL by ACF. The package TCP is connected to the panel so that its tip covers the protective film PSV 1 exposing the connection terminal GTM on the panel PNL side.Therefore, the external connection terminal GTM (DTM) is connected to the protective film PSV 1 or the package. At least one side of TCP is covered, making it more resistant to touch.
B F 1 はポリイ ミ ド等からなるベ一スフ イルムであり、 S R Sは 半田付けの際半田が余計なところへつかないようにマスクするため のソルダレジス ト膜である。 シールパターン S Lの外側の上下ガラ ス基板の隙間は洗浄後エポキシ樹脂 E P X等により保護され、 パッ ケージ T C Pと上側基板 S U B 2の間には更にシリ コーン樹脂 S I Lが充填され保護が多重化されている。  B F 1 is a base film made of polyimide or the like, and S R S is a solder resist film for masking so that solder does not adhere to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by epoxy resin EPX, etc., and the silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 to multiplex protection. .
《駆動回路基板 P C B 2》  《Drive circuit board P C B 2》
駆動回路基板 P C B 2は、 I C、 コンデンサ、 抵抗等の電子部品 が搭載されている。 この駆動回路基板 P C B 2には、 1つの電圧源 から複数の分圧した安定化された電圧源を得るための電源回路や、 ホス ト （上位演算処理装置） からの C R T (陰極線管） 用の情報を T F T液晶表示装置用の情報に変換する回路を含む回路 S U Pが搭 載されている。 C J は外部と接続される図示しないコネクタが接続 されるコネクタ接続部である。 The driving circuit board PCB 2 has electronic components such as ICs, capacitors, and resistors mounted thereon. This drive circuit board PCB 2 has one voltage source A power supply circuit for obtaining a plurality of divided and stabilized voltage sources from a computer, and a circuit for converting information for a CRT (cathode ray tube) from a host (high-level processing unit) to information for a TFT liquid crystal display A circuit SUP that includes is installed. CJ is a connector connection part to which a connector (not shown) connected to the outside is connected.
駆動回路基板 P C B 1 と駆動回路基板 P C B 2 とはフラ ッ トケ一 ブル F Cにより電気的に接続されている。  The drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by a flat cable FC.
《液晶表示モジュールの全体構成》  《Overall configuration of LCD module》
F i g . 2 2 は、 液晶表示モジュール M D Lの各構成部品を示す 分解斜視図である。  FIG. 22 is an exploded perspective view showing each component of the liquid crystal display module MDL.
S H Dは金属板から成る枠状のシール ドケース （メ タルフ レー ム） 、 L C Wその表示窓、 P N Lは液晶表示パネル、 S P Bは光拡 散板、 L C Bは導光体、 R Mは反射板、 B Lはバッ ク ライ ト蛍光管、 L C Aはバックライ トケースであり、 図に示すような上下の配置関 係で各部材が積み重ねられてモジュール M D Lが組み立てられる。  SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide, RM is a reflection plate, and BL is a back plate. The light fluorescent tube and LCA are backlight cases, and the components are stacked in a vertical arrangement as shown in the figure to assemble the module MDL.
モジュール M D Lは、 シール ドケース S H Dに設けられた爪とフ ッ クによって全体が固定されるよう になっている。  The entire module MDL is fixed by claws and hooks provided on the shield case SHD.
ノく ッ クライ トケース L C Aはバッ クライ 卜蛍光管 B L、 光拡散板 S P B光拡散板、 導光体 L C B、 反射板 RMを収納する形状になつ ており、 導光体 L C Bの側面に配置されたバッ クライ ト蛍光管 B L の光を、 導光体 L C B、 反射板 R M、 光拡散板 S P Bにより表示面 で一様なバック ライ トにし、 液晶表示パネル P N L側に出射する。 バックライ ト蛍光管 B Lにはイ ンバータ回路基板 P C B 3が接続さ れており、 バッ クライ ト蛍光管 B Lの電源となっている。  The knock case LCA is configured to house the backlight fluorescent tube BL, light diffusion plate SPB light diffusion plate, light guide LCB, and reflection plate RM, and the battery case LCA is placed on the side of the light guide LCB. The light from the fluorescent light tube BL is converted into a uniform backlight on the display surface by the light guide LCB, the reflector RM, and the light diffuser SPB, and emitted to the liquid crystal display panel PNL. An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL, and serves as a power source for the backlight fluorescent tube BL.
(実施例 2 )  (Example 2)
F i g . 2 3 に本実施例のアクティ ブ · マ ト リ ッ クス型カラー液 晶表示装置の液晶表示部の一画素とその周辺を示す要部平面図を示 す。 本実施例は、 第 1 の実施例と異なり、 対抗電極 C Tを対向電極 信号線 C L と一体で形成している。 その他の構成は第 1 の実施例と 同様であり、 本発明の効果も同じである。 Fig. 23 shows the active matrix type color liquid of this embodiment. FIG. 2 is a plan view of a principal part showing one pixel of a liquid crystal display portion of a liquid crystal display device and its periphery. In the present embodiment, unlike the first embodiment, the counter electrode CT is formed integrally with the counter electrode signal line CL. Other configurations are the same as those of the first embodiment, and the effects of the present invention are also the same.
(実施例 3 )  (Example 3)
F i g . 2 4に本実施例のアクティ ブ ' マ ト リ ックス型カラー液 晶表示装置の液晶表示部の一画素とその周辺を示す要部平面図をし 示す。 本実施例は、 第 1 の実施例と異なり、 対抗電極 C Tを対向電 極信号線 C Lと一体で、 さ らに画素電極 P Xもソ一ス電極 S D 1 と 一体で形成している。 その他の構成は第 1 の実施例と同様であり、 本発明の効果も同じである。  FIG. 24 is a plan view of a principal part showing one pixel of the liquid crystal display portion of the active matrix type color liquid crystal display device of this embodiment and the periphery thereof. In this embodiment, unlike the first embodiment, the counter electrode CT is formed integrally with the counter electrode signal line CL, and the pixel electrode PX is formed integrally with the source electrode SD1. Other configurations are the same as those of the first embodiment, and the effects of the present invention are also the same.
以上詳述したよう に、 本発明によれば、 高コン トラス ト比、 かつ、 広視野角特性を得られると同時に、 高画質を維持できる高信頼性を 両立した液晶表示装置を得ることができる。  As described in detail above, according to the present invention, it is possible to obtain a liquid crystal display device that can achieve a high contrast ratio, a wide viewing angle characteristic, and a high reliability that can maintain high image quality. .
また、 同時に、 応答速度が極めて速く 、 低電圧で駆動可能な液晶表 示装置も得るこ とができる。  At the same time, it is possible to obtain a liquid crystal display device which has a very high response speed and can be driven at a low voltage.
[産業上の利用可能性]  [Industrial applicability]
本発明は、 上述したよう に液晶等に適用され、 液晶製造産業にお いて実用可能性がある。  The present invention is applied to liquid crystal and the like as described above, and has practical application in the liquid crystal manufacturing industry.

Claims

請 求 の 範 囲 The scope of the claims
1 . 一対の基板と、 前記一対の基板に挟持された正の誘電率異方性 を有する液晶組成物と、 電圧無印加時に前記液晶組成物層中の液晶 分子の光軸を基板面に略垂直に配向させ得る配向制御膜と、 前記液 晶組成物層に前記一対の基板の基板面に略平行な電界を発生させる 一対の電極構造と、 前記基板面に平行な電界成分と一方の光透過軸 との間の角度が約 4 5度で、 他方の光透過軸が一方の光透過軸と約 9 0度で配置される一対の偏光板とを有し、 前記電界で前記液晶組 成物層を透過する光の透過率を変調するこ とを特徴とする液晶表示 装置。  1. A pair of substrates, a liquid crystal composition having a positive dielectric anisotropy sandwiched between the pair of substrates, and an optical axis of liquid crystal molecules in the liquid crystal composition layer substantially without a voltage applied to the substrate surface when no voltage is applied. An alignment control film capable of being vertically oriented; a pair of electrode structures for generating an electric field in the liquid crystal composition layer substantially parallel to the substrate surfaces of the pair of substrates; an electric field component parallel to the substrate surface and one light An angle with respect to the transmission axis is about 45 degrees, and the other light transmission axis has a pair of polarizing plates arranged with one light transmission axis and about 90 degrees, and the liquid crystal composition is formed by the electric field. A liquid crystal display device characterized by modulating the transmittance of light transmitted through an object layer.
2 . 多数の走査配線と、 多数の信号配線と、 前記多数の走査配線と 前記多数の信号緯線に各々の略交点に形成された能動素子と、 前記 一対の基板の基板面に略平行な電界を発生させ得る一対の電極を有 することを特徴とする請求項 1記載の液晶表示装置。  2. A large number of scanning lines, a large number of signal lines, an active element formed at each intersection of the large number of scanning lines and the large number of signal latitude lines, and an electric field substantially parallel to the substrate surfaces of the pair of substrates. 2. The liquid crystal display device according to claim 1, comprising a pair of electrodes capable of generating an electric field.
3 . 多数の走査配線と、 多数の信号配線と、 前記多数の走査配線と 前記多数の信号緯線に各々の略交点に形成された薄膜 ト ラ ンジスタ 素子と、 前記一対の基板の基板面に略平行な電界を発生させ得る一 対の電極を有することを特徴とする請求項 1記載の液晶表示装置。  3. A large number of scanning wirings, a large number of signal wirings, a thin film transistor element formed substantially at each intersection of the large number of scanning wirings and the large number of signal latitude lines, 2. The liquid crystal display device according to claim 1, further comprising a pair of electrodes capable of generating a parallel electric field.
4 . 不要な光漏れ部分を遮光し絶縁性を有するブラックマ ト リ クス を有することを特徴とする請求項 1記載の液晶表示装置。 4. The liquid crystal display device according to claim 1, wherein the liquid crystal display device has a black matrix having an insulating property by shielding unnecessary light leakage portions.
5 . 前記一対の基板の前記液晶組成物の挟持面の反対側の基板面の 少なく とも一方の基板面上に透明導電膜を有することを特徴とする 請求項 1記載の液晶表示装置。  5. The liquid crystal display device according to claim 1, wherein a transparent conductive film is provided on at least one substrate surface of the pair of substrates opposite to the holding surface of the liquid crystal composition.
PCT/JP1997/004719 1997-12-19 1997-12-19 Liquid crystal display WO1999032924A1 (en)

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CN100447638C (en) * 2002-05-31 2008-12-31 夏普株式会社 Liquid crystal display device and method of producing the same
CN100347598C (en) * 2003-12-22 2007-11-07 夏普株式会社 Display unit and display device
WO2009154258A1 (en) * 2008-06-18 2009-12-23 シャープ株式会社 Liquid crystal panel and liquid crystal display device
WO2009154021A1 (en) * 2008-06-18 2009-12-23 シャープ株式会社 Liquid crystal panel and liquid crystal display device
JP2010217853A (en) * 2008-06-18 2010-09-30 Sharp Corp Liquid crystal panel and liquid crystal display
JP4621788B2 (en) * 2008-06-18 2011-01-26 シャープ株式会社 Liquid crystal panel and liquid crystal display device
US8054435B2 (en) 2008-06-18 2011-11-08 Sharp Kabushiki Kaisha Liquid crystal panel and liquid crystal display device
CN102047175B (en) * 2008-06-18 2013-11-20 夏普株式会社 Liquid crystal panel and liquid crystal display device
JPWO2010137217A1 (en) * 2009-05-29 2012-11-12 シャープ株式会社 Liquid crystal panel and liquid crystal display device
JP5389923B2 (en) * 2009-07-31 2014-01-15 シャープ株式会社 Liquid crystal panel and liquid crystal display device
WO2011024495A1 (en) * 2009-08-24 2011-03-03 シャープ株式会社 Liquid crystal display device
CN102472936A (en) * 2009-08-24 2012-05-23 夏普株式会社 Liquid crystal display device
JP2012168567A (en) * 2012-06-14 2012-09-06 Semiconductor Energy Lab Co Ltd Liquid crystal display device, personal computer, display, and electronic book

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