WO1997026780A1 - Circuit-board substrate - Google Patents

Circuit-board substrate Download PDF

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Publication number
WO1997026780A1
WO1997026780A1 PCT/DE1997/000050 DE9700050W WO9726780A1 WO 1997026780 A1 WO1997026780 A1 WO 1997026780A1 DE 9700050 W DE9700050 W DE 9700050W WO 9726780 A1 WO9726780 A1 WO 9726780A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
printed circuit
area
carrier device
conductor tracks
Prior art date
Application number
PCT/DE1997/000050
Other languages
German (de)
French (fr)
Inventor
Hans-Georg Mensch
Martin Gruber
Josef Dirnberger
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1997026780A1 publication Critical patent/WO1997026780A1/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path

Definitions

  • the present invention relates to a circuit board carrier device according to the preamble of claim 1, i.e. a printed circuit board carrier device with one or more printed circuit area (s) having printed conductors, the printed conductors of one or more of the printed circuit areas being at least partially electrically connected to one another.
  • Such a carrier device is e.g. a carrier tape to be processed into printed circuit boards, for example a glass epoxy carrier tape, which is continuously processed into printed circuit boards by successively performing the steps of punching, lamination, lithography, galvanizing and separation.
  • the steps of punching, lamination and lithography serve to form the openings for mounting components on the later printed circuit boards and the printed conductors, contact points and the like (hereinafter referred to simply as conductor tracks for the sake of simplicity) of the later printed circuit boards.
  • the galvanizing step serves to refine the conductor tracks by applying an additional layer of material to the conductor tracks.
  • the electroplating process requires that a predetermined voltage is applied to the conductor tracks to be coated.
  • the conductor tracks to be finished of each printed circuit board area are ie the conductor tracks of each circuit board to be refined and / or the conductor tracks of circuit boards provided adjacent on the carrier tape are preferably electrically connected to one another by conductor track connecting elements in such a way that the number of contact points on the carrier strip which have to be connected to a corresponding voltage wave during galvanizing, can be reduced to a minimum in order to put the corresponding conductor tracks under voltage.
  • Such a carrier tape is shown schematically in Figure 3.
  • the carrier tape 1 shown in FIG. 3 has two rows one above the other, each with a large number of adjacent, more precisely adjacent, printed circuit board areas, of which only a first printed circuit board area 10, a second printed circuit board area 20, and a third printed circuit board area 30 and a fourth circuit board area 40 are shown completely; the area boundaries of the respective circuit board areas are identified in FIG. 3 by dashed lines surrounding the respective circuit board areas.
  • each of the printed circuit board areas represents an individual printed circuit board along the assigned area boundaries, although the printed circuit board area area need not be identical to the final printed circuit board area (the latter generally becomes smaller be as the former).
  • the board areas also contain an arbitrarily higher number of printed circuit boards, which are then further processed and / or delivered as a coherent unit.
  • an upper interconnect connecting element 2 and a lower interconnect connecting element 3 also extend along these edge sections of the carrier tape 1.
  • a middle conductor connecting element 4 which (not shown in FIG. 3) can have electrical connections to the upper conductor connecting element 2 and / or to the lower conductor connecting element 3.
  • Each of the circuit board areas has any number of conductor tracks 11, 21, 31 or 41 to be refined. For the sake of simplicity, these conductor tracks are only indicated in FIG. 3 in the immediate vicinity of the respective conductor track connecting elements.
  • the conductor tracks 11, 21, 31 and 41 are, as can be seen from FIG. 3, connected to the upper, the middle and / or the lower conductor track connecting element. If a voltage suitable for the electroplating process is now applied to one or more interconnect connecting elements, this voltage is automatically applied to all interconnects to be refined. The effort required for electroplating can thus be reduced to a minimum.
  • the circuit board areas, each of which - as already mentioned above - are supplied can contain a large number of printed circuit boards, separated from one another along the region boundaries (separation step).
  • the separated circuit board areas are then subjected to an electrical test as part of quality assurance. Since the conductor tracks of the individual printed circuit board areas can still be short-circuited in whole or in part by the interconnect connecting elements, even in the separated state, these short-circuits must first be removed. This is currently usually done by punching out corresponding areas from the respective printed circuit board areas to interrupt the conductor track path to the connection point connecting the conductor tracks (to the relevant conductor track connecting element).
  • Stamping is a separate work step that requires high precision and is correspondingly complex.
  • the present invention is therefore based on the object of developing a circuit board carrier device in accordance with the preamble of patent claim 1 in such a way that an electrical connection provided for circuit board manufacture between conductor tracks of one or more circuit board areas can be separated easily, quickly and reliably.
  • the conductor tracks of a respective circuit board area to be electrically connected to one another are led outside of the relevant circuit board area and are connected to one another at one or more connection points which lie completely outside the relevant circuit board area.
  • the electrical connection provided for circuit board manufacture between conductor tracks of one or more conductor Board areas are thus automatically separated when the respective circuit board areas are removed from the circuit board carrier device.
  • Such a separation process does not require a separate work step and can therefore be carried out easily, quickly and safely.
  • FIG. 1 shows a schematic illustration of a circuit board carrier device according to the invention in accordance with a first exemplary embodiment
  • FIG. 2 shows a schematic illustration of a circuit board carrier device according to the invention in accordance with a second exemplary embodiment
  • Figure 3 is a schematic representation of a conventional circuit board carrier device.
  • the printed circuit board carrier devices shown in FIGS. 1 and 2 in the form of carrier tapes 1 largely correspond to the conventional carrier tape 1 described at the beginning and shown in FIG. 3. Unless explicitly referred to differences, the statements made regarding the carrier tape 1 according to FIG. 3 also apply in full to the carrier tapes shown in FIGS.
  • the carrier tape 1 shown in FIGS. 1 and 2 like the conventional carrier tape 1 according to FIG. 3, likewise has first, second, third and fourth printed circuit board regions 10, 20, 30 and 40, the conductor tracks 11, 21, 31 and 41 of which by upper, middle and are to be connected to one another under interconnect connecting elements 2, 3 and 4, and their area boundaries are in turn represented by dashed lines.
  • the carrier tapes according to the invention according to FIGS. 1 and 2 are, however, designed in such a way that the conductor tracks of a respective circuit board area to be electrically connected to one another are led outside the relevant circuit board area and are connected to one another at one or more locations which are completely outside of the relevant PCB area.
  • this can be achieved, for example, by arranging the area limits represented by dashed lines in a manner different from the area limits of the conventional carrier tape in such a way that a connection point connecting the conductor tracks of a circuit board area (the conductor connecting the conductor tracks) web connecting element section) comes to lie outside the relevant circuit board area.
  • the area boundary at those points where the connection points in question are present should be moved inwards into the circuit board area to be kept clear of the respective connection point in such a way that the connection point is more or less spacious is carried out.
  • the resulting region boundary curve is composed of straight lines with the formation of right angles.
  • the range limits can also be any other course (for example roundings instead of corners, have curved line segments instead of straight line segments, etc.);
  • the exact area boundary course is advantageously determined taking into account the technology and the tool with which the respective circuit board areas are separated from the carrier tape.
  • the respective interconnects with respect to this circuit board production are preferably to be arranged laterally offset, similarly to the illustration in FIG. 1, in such a way that they do not face one another (not even partially) face to face).
  • the exemplary embodiment illustrated in FIG. 2 provides that the conductor track connecting elements 2, 3 and 4, deviating from the conductor track connecting elements of the conventional carrier tape, are arranged in such a way that a connecting part connecting the conductor tracks of a printed circuit board area (the conductor track connecting element section connecting the conductor tracks) with an unchanged area boundary course outside of that shown in FIG concerned PCB area comes to rest.
  • FIG. 2 it is provided in detail for this that the area limit at those points where there are connection points in question are to be moved away from the circuit board area to be kept clear of the respective connection point in such a way that the connection point faces outside the relevant circuit board area comes to lie.
  • the resulting interconnect connecting element course in the exemplary embodiment shown in FIG. 2 is composed in each case of straight sections which are joined together to form right angles.
  • the interconnect connecting elements can also have any other course (for example, curves instead of corners, curved sections instead of straight sections, etc.).
  • the respective conductor tracks with respect to this conductor connecting element are preferably to be arranged laterally offset in a manner similar to that in the illustration in FIG. 2 in such a way that they do not face one another (not even partially) face to face).
  • interconnect connecting elements run along the longitudinal direction of the carrier tape.
  • the conductor track connecting elements run along the transverse direction of the carrier tape.
  • the present invention is not limited to flexible printed circuit boards, but can be adapted accordingly to the changed mechanical conditions. Nisse can also be used for the production of rigid circuit boards.

Abstract

Described is a circuit-board substrate (1) having one or more circuit-board zones (10, 20, 30, 40) with conductor tracks (11, 21, 31, 41), at least some of the printed conductors of one or more of the circuit-board zones being electrically connected to each other. The substrate is characterized in that the printed conductors to be connected to each other of one circuit-board zone are led out of the circuit-board zone concerned and connected to each other at one or more connection points located completely outside the circuit-board zone concerned.

Description

Beschreibungdescription
Leiterplatten-TrägervorrichtungPCB carrier device
Die vorliegende Erfindung betrifft eine Leiterplatten-Träger¬ vorrichtung gemäß dem Oberbegriff des Patentanspruchs 1, d.h. eine Leiterplatten-Trägervorrichtung mit einem oder mehreren, Leiterbahnen aufweisenden Leiterplattenbereich(en) , wobei die Leiterbahnen eines oder mehrerer der Leiterplattenbereiche zumindest teilweise jeweils elektrisch miteinander verbunden sind.The present invention relates to a circuit board carrier device according to the preamble of claim 1, i.e. a printed circuit board carrier device with one or more printed circuit area (s) having printed conductors, the printed conductors of one or more of the printed circuit areas being at least partially electrically connected to one another.
Eine derartige Trägervorrichtung ist z.B. ein zu Leiterplat¬ ten zu verarbeitende Trägerband, beispielsweise ein Glas- epoxy-Trägerband, das unter aufeinanderfolgender Durchführung der Schritte Stanzung, Lamination, Lithografie, Galvanisie¬ rung und Separierung fortlaufend zu Leiterplatten verarbeitet wird.Such a carrier device is e.g. a carrier tape to be processed into printed circuit boards, for example a glass epoxy carrier tape, which is continuously processed into printed circuit boards by successively performing the steps of punching, lamination, lithography, galvanizing and separation.
Die Schritte Stanzung, Lamination und Lithografie dienen dazu, die Öffnungen zur Montage von Bauelementen auf die spä¬ teren Leiterplatten und die Leiterbahnen, Kontaktstellen und dergleichen (nachfolgend der Einfachheit halber kurz alε Lei¬ terbahnen bezeichnet) der späteren Leiterplatten auszubilden.The steps of punching, lamination and lithography serve to form the openings for mounting components on the later printed circuit boards and the printed conductors, contact points and the like (hereinafter referred to simply as conductor tracks for the sake of simplicity) of the later printed circuit boards.
Der Galvanisierungsschritt dient dazu, die Leiterbahnen durch Aufbringen einer zusätzlichen Materialschicht auf die Leiter¬ bahnen zu veredeln.The galvanizing step serves to refine the conductor tracks by applying an additional layer of material to the conductor tracks.
Das Galvanisierungsverfahren erfordert, daß an die zu be¬ schichtenden Leiterbahnen eine vorbestimmte Spannung angelegt wird.The electroplating process requires that a predetermined voltage is applied to the conductor tracks to be coated.
Um nicht jede einzelne Leiterbahn jeder einzelnen herzustel- lenden Leiterplatte über eine separaten Leitung mit der er¬ forderlichen Spannung beaufschlagen zu müssen, werden die zu veredelnden Leiterbahnen eines jeden Leiterplattenbereichs, d.h. die zu veredelnden Leiterbahnen einer jeden Leiterplatte und/oder die Leiterbahnen von auf dem Trägerband benachbart vorgesehenen Leiterplatten durch Leiterbahnverbindungsele¬ mente vorzugsweise elektrisch derart miteinander verbunden, daß die Anzahl der Kontaktstellen auf dem Trägerstreifen, die beim Galvanisieren mit einer entsprechenden Spannungsςruelle verbunden werden müssen, um die entsprechenden Leiterbahnen unter Spannung zu setzen, auf ein Minimum reduzierbar ist.In order not to have to apply the required voltage to each individual conductor track of each individual printed circuit board to be manufactured via a separate line, the conductor tracks to be finished of each printed circuit board area are ie the conductor tracks of each circuit board to be refined and / or the conductor tracks of circuit boards provided adjacent on the carrier tape are preferably electrically connected to one another by conductor track connecting elements in such a way that the number of contact points on the carrier strip which have to be connected to a corresponding voltage wave during galvanizing, can be reduced to a minimum in order to put the corresponding conductor tracks under voltage.
Um die Anzahl der Arbeitsschritte bei der Leiterplattenher¬ stellung gering zu halten, kann vorgesehen werden, Leiter¬ bahnverbindungselemente wie die Leiterbahnen zusammen mit diesen herzustellen.In order to keep the number of work steps in the manufacture of printed circuit boards low, provision can be made for connecting interconnect elements such as the interconnects to be produced together with them.
Ein derart ausgebildetes Trägerband ist schematisch in Figur 3 gezeigt.Such a carrier tape is shown schematically in Figure 3.
Das in der Figur 3 gezeigte Trägerband 1 weist zwei überein¬ ander liegende Reihen mit jeweils einer Vielzahl von neben- einander liegenden, genauer gesagt aneinandergrenzenden Lei¬ terplattenbereichen auf, von welchen jedoch nur ein erster Leiterplattenbereich 10, ein zweiter Leiterplattenbereich 20, ein dritter Leiterplattenbereich 30 und ein vierter Leiter¬ plattenbereich 40 vollständig dargestellt sind; die Bereichs- grenzen der jeweiligen Leiterplattenbereiche sind in der Fi¬ gur 3 durch die jeweiligen Leiterplattenbereiche umgebende gestrichelte Linien gekennzeichnet.The carrier tape 1 shown in FIG. 3 has two rows one above the other, each with a large number of adjacent, more precisely adjacent, printed circuit board areas, of which only a first printed circuit board area 10, a second printed circuit board area 20, and a third printed circuit board area 30 and a fourth circuit board area 40 are shown completely; the area boundaries of the respective circuit board areas are identified in FIG. 3 by dashed lines surrounding the respective circuit board areas.
Jeder der Leiterplattenbereiche stellt im vorliegenden Auβ- fύhrungsbeispiel nach dem Heraustrennen desselben aus dem Trägerband längs der zugeordneten Bereichsgrenzen eine ein¬ zelne Leiterplatte dar, wobei jedoch die Leiterplatten¬ bereichsfläche nicht identisch mit der endgültigen Leiter¬ plattenfläche sein muß (letztere wird in der Regel kleiner als erstere sein) . Aus Gründen der leichteren Handhabbarkeit der Leiterplatten bei der abschließenden QualitatsSicherungs¬ prüfung, beim Transport und dergleichen kann jeder der Lei- terplattenbereiche jedoch auch eine beliebig höhere Anzahl von Leiterplatten enthalten, die dann als zusammenhängende Einheit weiterverarbeitet und/oder ausgeliefert werden.In the present exemplary embodiment, each of the printed circuit board areas, after being removed from the carrier tape, represents an individual printed circuit board along the assigned area boundaries, although the printed circuit board area area need not be identical to the final printed circuit board area (the latter generally becomes smaller be as the former). For reasons of easier handling of the printed circuit boards during the final quality assurance test, during transport and the like, each of the cables However, the board areas also contain an arbitrarily higher number of printed circuit boards, which are then further processed and / or delivered as a coherent unit.
An zwei gegenüberliegenden Randabschnitten des Trägerbandes 1 (entlang der gemäß der Figur 3 oberen und unteren Ränder des Trägerbandes 1) sind in der Figur 3 nicht gezeigte, zum Transport des Trägerbandes 1 dienende Perforations16eher vor¬ gesehen. Entlang dieser Randabschnitte des Trägerbandes 1 er- strecken sich darüber hinaus auch ein oberes Leiterbahnver¬ bindungselement 2 und ein unteres Leiterbahnverbindungsele¬ ment 3. Entlang der Bereichsgrenze zwischen den gemäß Figur 3 oberen Leiterplattenbereichen 10, 20 und den gemäß Figur 3 unteren Leiterplattenbereichen 30, 40 erstreckt sich ein mittleres Leiterbahnverbindungselement 4, das (in der Figur 3 nicht gezeigte) elektrische Verbindungen zum oberen Leiter¬ bahnverbindungselement 2 und/oder zum unteren Leiterbahnver¬ bindungselement 3 aufweisen kann.On two opposite edge sections of the carrier tape 1 (along the upper and lower edges of the carrier tape 1 according to FIG. 3), perforations 16 not shown in FIG. 3 and used to transport the carrier tape 1 are provided. An upper interconnect connecting element 2 and a lower interconnect connecting element 3 also extend along these edge sections of the carrier tape 1. Along the area boundary between the upper printed circuit board areas 10, 20 according to FIG. 3 and the lower printed circuit board areas 30, 40 according to FIG. 3 extends a middle conductor connecting element 4, which (not shown in FIG. 3) can have electrical connections to the upper conductor connecting element 2 and / or to the lower conductor connecting element 3.
Jeder der Leiterplattenbereiche weist eine beliebige Vielzahl von zu veredelnden Leiterbahnen 11, 21, 31 bzw. 41 auf. In der Figur 3 sind diese Leiterbahnen der Einfachheit halber jeweils nur in der unmittelbaren Umgebung der jeweiligen Lei¬ terbahnverbindungselemente angedeutet.Each of the circuit board areas has any number of conductor tracks 11, 21, 31 or 41 to be refined. For the sake of simplicity, these conductor tracks are only indicated in FIG. 3 in the immediate vicinity of the respective conductor track connecting elements.
Die Leiterbahnen 11, 21, 31 und 41 sind, wie aus Figur 3 er¬ sichtlich ist, mit dem oberen, dem mittleren und/oder den un¬ teren Leiterbahnverbindungselement verbunden. Wird nun an eine oder mehrere Leiterbahnverbindungselemente eine für den Galvanisierungsprozeß geeignete Spannung angelegt, so liegt diese Spannung automatisch an allen zu veredelnden Leiterbah¬ nen an. Der zum Galvanisieren erforderliche Aufwand läßt sich damit auf ein Minimum reduzieren.The conductor tracks 11, 21, 31 and 41 are, as can be seen from FIG. 3, connected to the upper, the middle and / or the lower conductor track connecting element. If a voltage suitable for the electroplating process is now applied to one or more interconnect connecting elements, this voltage is automatically applied to all interconnects to be refined. The effort required for electroplating can thus be reduced to a minimum.
Nach.dem Galvanisieren werden die Leiterplattenbereiche, von denen - wie vorstehend bereits erwähnt - jeder einer belie- bige Anzahl von Leiterplatten enthalten kann, entlang der Be¬ reichsgrenzen voneinander getrennt (Separierungsschritt) .After the electroplating, the circuit board areas, each of which - as already mentioned above - are supplied can contain a large number of printed circuit boards, separated from one another along the region boundaries (separation step).
Die getrennten Leiterplattenbereiche werden dann im Rahmen der Qualitätssicherung einer elektrischen Prüfung unterzogen. Da die Leiterbahnen der einzelnen Leiterplattenbereiche auch im getrennten Zustand noch ganz oder teilweise durch die Lei¬ terbahnverbindungselemente kurzgeschlossen sein können, müs¬ sen diese Kurzschlüsse zunächst entfernt werden. Dies ge- schient derzeit normalerweise dadurch, daß durch Ausstanzen entsprechender Bereiche aus den jeweiligen Leiterplatten¬ bereichen der Leiterbahnpfad zu der die Leiterbahnen jeweils verbindenden Verbindungsstelle (zum betreffenden Leiterbahn¬ verbindungselement) unterbrochen wird.The separated circuit board areas are then subjected to an electrical test as part of quality assurance. Since the conductor tracks of the individual printed circuit board areas can still be short-circuited in whole or in part by the interconnect connecting elements, even in the separated state, these short-circuits must first be removed. This is currently usually done by punching out corresponding areas from the respective printed circuit board areas to interrupt the conductor track path to the connection point connecting the conductor tracks (to the relevant conductor track connecting element).
Daε Stanzen ist ein separater Arbeitsschritt, der hohe Präzi¬ sion erfordert und entsprechend aufwendig ist.Stamping is a separate work step that requires high precision and is correspondingly complex.
Der vorliegenden Erfindung liegt daher die Aufgabe zugrunde, eine Leiterplatten-Trägervorrichtung gemäß dem Oberbegriff des Patentanspruchs 1 derart weiterzubilden, daß eine zur Leiterplattenherstellung vorgesehene elektrische Verbindung zwischen Leiterbahnen eines oder mehrerer Leiterplattenberei¬ che einfach, schnell und sicher auftrennbar ist.The present invention is therefore based on the object of developing a circuit board carrier device in accordance with the preamble of patent claim 1 in such a way that an electrical connection provided for circuit board manufacture between conductor tracks of one or more circuit board areas can be separated easily, quickly and reliably.
Diese Aufgabe wird erfindungsgemäß durch die im kennzeichnen¬ den Teil des Patentanspruchs l beanspruchten Merkmale gelöst.According to the invention, this object is achieved by the features claimed in the characterizing part of patent claim 1.
Demnach ist vorgesehen, daß die elektrisch miteinander zu verbindenden Leiterbahnen eines jeweiligen Leiterplatten¬ bereichs nach außerhalb des betreffenden Leiterplatten¬ bereichs geführt und miteinander an einer oder mehreren Ver¬ bindungsstellen verbunden sind, die vollständig außerhalb des betreffenden Leiterplattenbereichs liegen.Accordingly, it is provided that the conductor tracks of a respective circuit board area to be electrically connected to one another are led outside of the relevant circuit board area and are connected to one another at one or more connection points which lie completely outside the relevant circuit board area.
Die zur Leiterplattenherstellung vorgesehene elektrische Ver¬ bindung zwischen Leiterbahnen eines oder mehrerer Leiter- plattenbereiche werden damit automatisch mit dem Heraustren¬ nen der jeweiligen Leiterplattenbereiche aus der Leiterplat¬ ten-Trägervorrichtung aufgetrennt.The electrical connection provided for circuit board manufacture between conductor tracks of one or more conductor Board areas are thus automatically separated when the respective circuit board areas are removed from the circuit board carrier device.
Ein derartiger Trennvorgang erfordert keinen separaten Ar¬ beitsschritt und ist daher einfach, schnell und sicher durch¬ führbar.Such a separation process does not require a separate work step and can therefore be carried out easily, quickly and safely.
Vorteilhafte Weiterbildungen der Erfindung sind Gegenstand der Unteransprüche.Advantageous developments of the invention are the subject of the dependent claims.
Die Erfindung wird nachfolgend anhand eines Ausführungsbei- spiels unter Bezugnahme auf die Zeichnung näher erläutert.The invention is explained in more detail below on the basis of an exemplary embodiment with reference to the drawing.
Es zeigenShow it
Figur l eine schematische Darstellung einer erfindungsgemäßen Leiterplatten-Trägervorrichtung gemäß einem ersten Ausfüh¬ rungsbeispiel,FIG. 1 shows a schematic illustration of a circuit board carrier device according to the invention in accordance with a first exemplary embodiment,
Figur 2 eine schematische Darstellung einer erfindungsgemäßen Leiterplatten-Trägervorrichtung gemäß einem zweiten Ausfüh¬ rungsbeispiel, undFIG. 2 shows a schematic illustration of a circuit board carrier device according to the invention in accordance with a second exemplary embodiment, and
Figur 3 eine schematische Darstellung einer herkömmlichen Leiterplatten-Trägervorrichtung.Figure 3 is a schematic representation of a conventional circuit board carrier device.
Die in den Figuren l und 2 gezeigten Leiterplatten-Trägervor- richtungen in Form von Trägerbändern 1 entsprechen weitgehend dem eingangs beschriebenen, in Figur 3 gezeigten herkömmli¬ chen Trägerband l. Sofern nicht explizit auf Unterschiede hingewiesen wird, gelten die zum Trägerband 1 gemäß Figur 3 gemachten Ausführungen in vollem Umfang auch für die in den Figuren 1 und 2 gezeigten Trägerbänder. Das in den Figuren 1 und 2 gezeigte Trägerband 1 weist wie das herkömmlichen Trägerband 1 gemäß Figur 3 ebenfalls erste, zweite, dritte und vierte Leiterplattenbereiche 10, 20, 30 und 40 auf, deren Leiterbahnen 11, 21, 31 und 41 durch obere, mittlere und unter Leiterbahnverbindungselemente 2, 3 und 4 jeweils untereinander zu verbinden sind, und deren Bereichs¬ grenzen wiederum durch gestrichelte Linien dargestellt sind.The printed circuit board carrier devices shown in FIGS. 1 and 2 in the form of carrier tapes 1 largely correspond to the conventional carrier tape 1 described at the beginning and shown in FIG. 3. Unless explicitly referred to differences, the statements made regarding the carrier tape 1 according to FIG. 3 also apply in full to the carrier tapes shown in FIGS. The carrier tape 1 shown in FIGS. 1 and 2, like the conventional carrier tape 1 according to FIG. 3, likewise has first, second, third and fourth printed circuit board regions 10, 20, 30 and 40, the conductor tracks 11, 21, 31 and 41 of which by upper, middle and are to be connected to one another under interconnect connecting elements 2, 3 and 4, and their area boundaries are in turn represented by dashed lines.
Im Unterschied zum herkömmlichen Trägerband sind die erfin- dungsgemäßen Trägerbänder gemäß den Figuren 1 und 2 jedoch so ausgebildet, daß die elektrisch miteinander zu verbindenden Leiterbahnen eines jeweiligen Leiterplattenbereichs nach außerhalb des betreffenden Leiterplattenbereichs geführt und miteinander an einer oder mehreren Stellen verbunden sind, die vollständig außerhalb des betreffenden Leiterplatten¬ bereichs liegen.In contrast to the conventional carrier tape, the carrier tapes according to the invention according to FIGS. 1 and 2 are, however, designed in such a way that the conductor tracks of a respective circuit board area to be electrically connected to one another are led outside the relevant circuit board area and are connected to one another at one or more locations which are completely outside of the relevant PCB area.
Gemäß der Darstellung in Figur l kann dies beispielsweiεe da¬ durch erreicht werden, daß die durch gestrichelte Linien dar- gestellten Bereichsgrenzen abweichend von den Bereichsgrenzen des herkömmlichen Trägerbandes derart angeordnet werden, daß eine die Leiterbahnen eines Leiterplattenbereichs verbindende Verbindungsstelle (der die Leiterbahnen verbindende Leiter¬ bahnverbindungselement-Abschnitt) außerhalb des betreffenden Leiterplattenbereichs zu liegen kommt. Gemäß Figur 1 ist hierzu im einzelnen vorgesehen, die Bereichsgrenze an denje¬ nigen Stellen, wo in Rede stehende Verbindungsstellen vorhan¬ den sind, derart nach innen in den von der jeweiligen Verbin¬ dungsstelle freizuhaltenden Leiterplattenbereich zu verlegen, daß die Verbindungsstelle mehr oder weniger weiträumig umfah¬ ren wird.According to the illustration in FIG. 1, this can be achieved, for example, by arranging the area limits represented by dashed lines in a manner different from the area limits of the conventional carrier tape in such a way that a connection point connecting the conductor tracks of a circuit board area (the conductor connecting the conductor tracks) web connecting element section) comes to lie outside the relevant circuit board area. According to FIG. 1, it is provided in detail for this that the area boundary at those points where the connection points in question are present should be moved inwards into the circuit board area to be kept clear of the respective connection point in such a way that the connection point is more or less spacious is carried out.
Der daraus resultierende Bereichsgrenzenverlauf setzt sich bei dem in Figur 1 gezeigten Ausführungsbeispiel jeweils aus geraden Linienzügen unter jeweiliger Ausbildung von rechten Winkeln zusammen. Die Bereichsgrenzen können jedoch auch einen beliebigen anderen Verlauf (beispielsweise Rundungen statt Ecken, gekrümmte Liniensegmente statt gerader Linien¬ segmente etc.) aufweisen; Der genaue Bereichsgrenzenverlauf wird vorteilhafter Weise unter Berücksichtigung der Technik und des Werkzeuges festgelegt, mit welchen die jeweiligen Leiterplattenbereiche aus dem Trägerband herausgetrennt wer¬ den.In the exemplary embodiment shown in FIG. 1, the resulting region boundary curve is composed of straight lines with the formation of right angles. However, the range limits can also be any other course (for example roundings instead of corners, have curved line segments instead of straight line segments, etc.); The exact area boundary course is advantageously determined taking into account the technology and the tool with which the respective circuit board areas are separated from the carrier tape.
Sofern - wie beim mittleren Leiterbahnverbindungselement 4 - ein Leiterbahnverbindungselement mit Leiterbahnen mehrerer Leiterplattenbereiche zu verbinden ist, sind die jeweiligen Leiterbahnen bezüglich dieses Leiterplattenherstellung vor¬ zugsweise ähnlich wie bei der Darstellung in Figur 1 derart seitlich versetzt anzuordnen, daß sie einander nicht frontal (auch nicht teilweise frontal) gegenüberliegen.If - as with the middle interconnect connection element 4 - a interconnect connection element is to be connected to interconnects of several circuit board areas, the respective interconnects with respect to this circuit board production are preferably to be arranged laterally offset, similarly to the illustration in FIG. 1, in such a way that they do not face one another (not even partially) face to face).
Im Gegensatz zu der unter Bezugnahme auf Figur 1 beschriebe¬ nen Maßnahme zum Freihalten der jeweiligen Leiterplatten¬ bereiche von Verbindungsstellen für Leiterbahnen dieses Lei¬ terplattenbereichs ist bei dem in Figur 2 veranschaulichten Ausführungsbeispiel vorgesehen, daß die die Verbindungsstel¬ len tragenden Leiterbahnverbindungselemente 2, 3 und 4 abwei¬ chend von den Leiterbahnverbindungselementen des herkömmli¬ chen Trägerbandes derart angeordnet werden, daß eine die Lei¬ terbahnen eines Leiterplattenbereichs verbindende Verbin- dungssteile (der die Leiterbahnen verbindende Leiterbahn¬ verbindungselement-Abschnitt) bei gegenüber der Darstellung in Figur 3 unverändertem Bereichsgrenzenverlauf außerhalb des betreffenden Leiterplattenbereichs zu liegen kommt.In contrast to the measure described with reference to FIG. 1 for keeping the respective circuit board areas free of connection points for conductor tracks of this circuit board area, the exemplary embodiment illustrated in FIG. 2 provides that the conductor track connecting elements 2, 3 and 4, deviating from the conductor track connecting elements of the conventional carrier tape, are arranged in such a way that a connecting part connecting the conductor tracks of a printed circuit board area (the conductor track connecting element section connecting the conductor tracks) with an unchanged area boundary course outside of that shown in FIG concerned PCB area comes to rest.
Gemäß Figur 2 ist hierzu im einzelnen vorgesehen, die Be¬ reichsgrenze an denjenigen Stellen, wo in Rede stehende Ver- bindungεεtellen vorhanden sind, derart von dem von der jewei¬ ligen Verbindungsεtelle freizuhaltenden Leiterplattenbereich wegzuverlegen, daß die Verbindungsstelle außerhalb des be- treffenden Leiterplattenbereichs zu liegen kommt. Der daraus resultierende Leiterbahnverbindungselementverlauf setzt sich bei dem in Figur 2 gezeigten Ausführungsbeispiel jeweils aus geraden Teilstücken zusammen die unter Ausbildung von rechten Winkeln aneinadergesetzt sind. Die Leiterbahnver- bindungselemente können jedoch auch einen beliebigen anderen Verlauf (beispielsweise Rundungen statt Ecken, gekrümmte Teilstücke statt gerader Teilstücke etc.) aufweisen.According to FIG. 2, it is provided in detail for this that the area limit at those points where there are connection points in question are to be moved away from the circuit board area to be kept clear of the respective connection point in such a way that the connection point faces outside the relevant circuit board area comes to lie. The resulting interconnect connecting element course in the exemplary embodiment shown in FIG. 2 is composed in each case of straight sections which are joined together to form right angles. However, the interconnect connecting elements can also have any other course (for example, curves instead of corners, curved sections instead of straight sections, etc.).
Sofern - wie beim mittleren Leiterbahnverbindungselement 4 - ein Leiterbahnverbindungselement mit Leiterbahnen mehrerer Leiterplattenbereiche zu verbinden ist, sind die jeweiligen Leiterbahnen bezüglich dieses Leiterbahnverbinduπgselements vorzugsweise ähnlich wie bei der Darstellung in Figur 2 der¬ art seitlich versetzt anzuordnen, daß sie einander nicht frontal (auch nicht teilweise frontal) gegenüberliegen.If - as with the middle conductor connecting element 4 - a conductor connecting element is to be connected to conductor tracks of several printed circuit board areas, the respective conductor tracks with respect to this conductor connecting element are preferably to be arranged laterally offset in a manner similar to that in the illustration in FIG. 2 in such a way that they do not face one another (not even partially) face to face).
Die unter Bezugnahme auf die Figuren 1 und 2 beschriebenen Maßnahmen zur Lösung der der vorliegenden Erfindung zugrunde¬ liegenden Aufgabe können selbstverständlich auch kombiniert werden.The measures described with reference to FIGS. 1 and 2 for solving the problem on which the present invention is based can of course also be combined.
Bei den vorstehenden Ausführungen wurde jeweils davon ausge¬ gangen, daß Leiterbahnverbindungselemente längs der Längs¬ richtung des Trägerbandes verlaufen. Alternativ oder zusätz- lieh hierzu kann jedoch selbstverständlich auch vorgesehen werden, die Leiterbahnverbindungselemente längs der Querrich¬ tung des Trägerbandes verlaufen zu lassen. Eine entsprechende Festlegung des Verlaufs der Leiterbahnverbindungselemente und/oder der Bereichsgrenzen hat hier exakt die selbe posi- tive Wirkung wie das Vorsehen dieser Maßnahmen bei längs der Längsrichtung des Trägerbandes verlaufenden Leiterbahnverbin¬ dungselementen.In the foregoing, it was assumed that interconnect connecting elements run along the longitudinal direction of the carrier tape. As an alternative or in addition to this, however, it can of course also be provided that the conductor track connecting elements run along the transverse direction of the carrier tape. A corresponding determination of the course of the interconnect connecting elements and / or the area boundaries here has exactly the same positive effect as the provision of these measures in the case of interconnect connecting elements running along the longitudinal direction of the carrier tape.
Die vorliegende Erfindung ist darüber hinaus auch nicht auf flexible Leiterplatten beschränkt, sondern kann bei entspre¬ chender Anpassung an die veränderten mechanischen Verhält- nisse auch für die Herstellung starrer Leiterplatten verwen¬ det werden. Furthermore, the present invention is not limited to flexible printed circuit boards, but can be adapted accordingly to the changed mechanical conditions. Nisse can also be used for the production of rigid circuit boards.

Claims

Patentansprüche claims
1. Leiterplatten-Trägervorrichtung (1) mit einem oder meh¬ reren, Leiterbahnen (11, 21, 31, 41) aufweisenden Leiterplat- tenbereich(en) (10, 20, 30, 40), wobei die Leiterbahnen eines oder mehrerer der Leiterplattenbereiche zumindest teilweise jeweils elektrisch miteinander verbunden sind, d a d u r c h g e k e n n z e i c h n e t, daß die elektrisch miteinander zu verbindenden Leiterbahnen eines jeweiligen Leiterplattenbereichs nach außerhalb des be¬ treffenden Leiterplattenbereichs geführt und miteinander an einer oder mehreren Verbindungsstellen verbunden sind, die vollständig außerhalb des betreffenden Leiterplattenbereichs liegen.1. Printed circuit board carrier device (1) with one or more printed circuit area (s) (10, 20, 30, 40) having printed conductors (11, 21, 31, 41), the printed conductors being one or more of the printed circuit board areas are at least partially electrically connected to one another, characterized in that the conductor tracks of a respective circuit board area to be electrically connected to one another are guided outside the relevant circuit board area and are connected to one another at one or more connection points which lie completely outside the relevant circuit board area.
2. Leiterplatten-Trägervorrichtung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß auf der Leiterplatten-Trägervorrichtung (1) eine Vielzahl von unmittelbar aneinander grenzenden Leiterplattenbereichen (10, 20, 30, 40) vorgesehen ist.2. Printed circuit board carrier device according to claim 1, so that a plurality of immediately adjacent printed circuit board areas (10, 20, 30, 40) is provided on the printed circuit board carrier device (1).
3. Leiterplatten-Trägervorrichtung nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t, daß die Leiterplattenbereiche (10, 20, 30, 40) auf der Lei- terplatten-Trägervorrichtung (1) in mehreren Reihen und Spal¬ ten angeordnet sind.3. Printed circuit board carrier device according to claim 1 or 2, so that the printed circuit board regions (10, 20, 30, 40) on the printed circuit board carrier device (1) are arranged in a plurality of rows and columns.
4. Leiterplatten-Trägervorrichtung nach einem der vorherge¬ henden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Leiterplattenbereiche (10, 20, 30, 40) durch Abtren¬ nen entlang von äußeren Bereichsgrenzen separierbar sind.4. Printed circuit board carrier device according to one of the preceding claims, that the circuit areas (10, 20, 30, 40) can be separated by separating along outer area boundaries.
5. Leiterplatten- Trägervorrichtung Anspruch 4, d a d u r c h g e k e n n z e i c h n e t, daß die Bereichsgrenzen derart festgelegt sind, daß die Ver¬ bindungsstellen, an welchen die Leiterbahnen (11, 21, 31, 41) eines jeweiligen Leiterplattenbereichs (10, 20, 30, 40) elek¬ trisch miteinander verbunden sind, außerhalb der Bereichs¬ grenzen zu liegen kommen.5. Printed circuit board carrier device claim 4, characterized in that the range limits are set such that the Ver¬ connection points at which the conductor tracks (11, 21, 31, 41) of a respective circuit board area (10, 20, 30, 40) are electrically connected to one another, come to lie outside the area limits.
6. Leiterplatten-Trägervorrichtung nach einem der vorherge¬ henden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß jeder Leiterplattenbereich (10, 20, 30, 40) eine oder mehrere Leiterplatten beinhaltet.6. Printed circuit board carrier device according to one of the preceding claims, d a d u r c h g e k e n e z e i c h n e t that each printed circuit board area (10, 20, 30, 40) contains one or more printed circuit boards.
7. Leiterplatten-Trägervorrichtung nach einem der vorherge¬ henden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Leiterplattenbereiche (10, 20, 30, 40) und die diesen zugeordneten Leiterbahn-Verbindungsstellen jeweils derart an¬ geordnet sind, daß ein Heraustrennen eines Leiterplattenbe¬ reichs aus der Leiterplatten-Trägervorrichtung (1) längs der zugeordneten Bereichsgrenzen gleichzeitig ein Auftrennen der elektrischen Verbindung der Leiterbahnen (11, 21, 31, 41) dieses Leiterplattenbereichs bewirkt. 7. Printed circuit board carrier device according to one of the preceding claims, characterized in that the printed circuit board areas (10, 20, 30, 40) and the conductor connection points associated therewith are each arranged in such a manner that a circuit board area is separated from the area Printed circuit board carrier device (1) simultaneously causes the electrical connection of the conductor tracks (11, 21, 31, 41) of this printed circuit board area to be separated along the assigned area boundaries.
PCT/DE1997/000050 1996-01-16 1997-01-14 Circuit-board substrate WO1997026780A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19601388.7 1996-01-16
DE1996101388 DE19601388A1 (en) 1996-01-16 1996-01-16 PCB carrier device

Publications (1)

Publication Number Publication Date
WO1997026780A1 true WO1997026780A1 (en) 1997-07-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG97137A1 (en) * 1999-01-26 2003-07-18 Hitachi Cable Tape carrier for bga and semiconductor device using the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19822794C1 (en) * 1998-05-20 2000-03-09 Siemens Matsushita Components Multiple uses for electronic components, in particular surface acoustic wave components
JP3558921B2 (en) * 1999-05-14 2004-08-25 シャープ株式会社 Method of manufacturing tape carrier and tape carrier type semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2498873A1 (en) * 1981-01-23 1982-07-30 Sev Alternateurs Printed circuit mfr. using thick film track - subsequently thickened by chemical-and electro-deposition
JPS6420696A (en) * 1987-07-15 1989-01-24 Sharp Kk Manufacture of film carrier board
EP0468275A2 (en) * 1990-07-23 1992-01-29 Siemens Nixdorf Informationssysteme Aktiengesellschaft Filmcarrier for tape automated bonding
WO1995018522A1 (en) * 1993-12-24 1995-07-06 Ibiden Co., Ltd. Printed wiring board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2498873A1 (en) * 1981-01-23 1982-07-30 Sev Alternateurs Printed circuit mfr. using thick film track - subsequently thickened by chemical-and electro-deposition
JPS6420696A (en) * 1987-07-15 1989-01-24 Sharp Kk Manufacture of film carrier board
EP0468275A2 (en) * 1990-07-23 1992-01-29 Siemens Nixdorf Informationssysteme Aktiengesellschaft Filmcarrier for tape automated bonding
WO1995018522A1 (en) * 1993-12-24 1995-07-06 Ibiden Co., Ltd. Printed wiring board
EP0737025A1 (en) * 1993-12-24 1996-10-09 Ibiden Co, Ltd. Printed wiring board

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 13, no. 198 (E - 756) 11 May 1989 (1989-05-11) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG97137A1 (en) * 1999-01-26 2003-07-18 Hitachi Cable Tape carrier for bga and semiconductor device using the same

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