WO1996018245A1 - Phase locked loop controlled frequency synthesizer for use in frequency hopping - Google Patents

Phase locked loop controlled frequency synthesizer for use in frequency hopping Download PDF

Info

Publication number
WO1996018245A1
WO1996018245A1 PCT/EP1995/004783 EP9504783W WO9618245A1 WO 1996018245 A1 WO1996018245 A1 WO 1996018245A1 EP 9504783 W EP9504783 W EP 9504783W WO 9618245 A1 WO9618245 A1 WO 9618245A1
Authority
WO
WIPO (PCT)
Prior art keywords
synthesiser
frequency
frequency hopping
transmitting
time
Prior art date
Application number
PCT/EP1995/004783
Other languages
French (fr)
Inventor
Paul Howard
Alan Jones
Original Assignee
Motorola Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Limited filed Critical Motorola Limited
Priority to JP8517318A priority Critical patent/JPH09511639A/en
Priority to EP95941673A priority patent/EP0742974A1/en
Publication of WO1996018245A1 publication Critical patent/WO1996018245A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1077—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the phase or frequency detection means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/713—Spread spectrum techniques using frequency hopping

Definitions

  • This invention relates in general to communications systems, and more particularly to a method for implementing frequency hopping in a time domain system.
  • DCS 1800 have to be capable of supporting frequency hopping on a time slot by time slot basis. This requirement influences the linearity of the transmitter since power ramping must be employed to reduce spurious emissions from the step changes in transmit frequency. In order to reduce side-lobe levels it is desirable to spread the power ramp over a wide period. As a result, the synthesiser has an extremely small window in which to hop.
  • Several problems are encountered in the implementation of such a synthesiser, such as fast acquisition, low noise and high resistance to frequency pulling.
  • Slow frequency hopping is commonly employed in TDMA based cellular systems.
  • SFH slow frequency hopping
  • the frequency channel is altered at a rate which is lower than the bit rate. For example, in GSM the frequency channel is switched on a burst by burst basis.
  • SFH is employed for two reasons, to provide frequency diversity for slow moving mobiles and also inteferer diversity for increasing system capacity.
  • the synthesiser In order to support slow frequency hopping, it is necessary for the base station to support all time slots during the TDMA frame, consequently, the synthesiser has to frequency hop during a short period which exists between time slots, which is generally referred to as the guard period.
  • the frequency hopping mechanism is usually accomplished by employing two Phase-Locked Loop frequency synthesisers and a single pole double throw switch. When one synthesiser is providing the transmitting frequency, the other is reprogrammed and retuned to the next. The retuning process has to be accomplished within one time slot so that the required transmitting frequency is sufficiently stable before being directed to the transmitter output. This operation is illustrated in FIG. 1, which shows the transmitting frequency allocation per time slot and the guard period.
  • the switching mechanism which selects the appropriate synthesiser, causes an impulsive mismatch in load impedance which pulls the synthesiser off frequency. This causes a corresponding phase disturbance inside the loop which is eventually corrected by the loop feedback mechanism. However, if the synthesiser is unable to respond quickly, then a large phase excursion can occur at the beginning of the time slot resulting in significant performance degradation.
  • the required synthesiser board area can increase by upto 20%.
  • a method for implementing frequency hopping in a time domain system having at least a first synthesiser including the steps of locking onto a first frequency by the first synthesiser in wide loop bandwidth mode, transmitting from the first synthesiser, and converting to a narrow bandwidth mode on the first synthesiser after a delayed period of time.
  • the time domain system is a TDMA system.
  • FIG. 1 illustrates a TDMA frame structure.
  • FIG. 2 illustrates power ramping employed during a guard period of the TDMA frame structure of FIG. 1.
  • FIG. 3 illustrates a flow chart for a preferred embodiment of the present invention.
  • FIG. 4 is a block diagram of a synthesiser according to the present invention.
  • FIG. 5 simulation results of a synthesiser according to the prior art.
  • FIG. 6 simulation results of a synthesiser employing the method of the present invention.
  • FIG. 1 shows a frame 2 and slot 4 structure for a time division multiple access (TDMA) system employing frequency hopping.
  • the slots are shown changing frequency from one slot to the next thus each successive TDMA slot 4 is shown as being transmitted on a different frequency.
  • Frequencies are changed during a guard period 6 between two slots.
  • Two synthesisers may be employed to achieve such frequency hopping.
  • One synthesiser may be transmitting while a second synthesiser is tuning to the next slot's frequency.
  • the synthesisers then switch during the guard period 6.
  • Dual loop bandwidth is employed which has independent control of both noise and switching speed.
  • FIG. 2 shows slot n ramping down 20, 21 and slot n+1 ramping up 22, 23.
  • the designated end of the nth time slot 20 is where the transmitting synthesiser begins ramping down and is the beginning of a guard period 20.
  • the synthesiser that switches from tuning to transmitting begins ramping up 22 and ends ramp up near the start of the n+1 burst 23, the end of the guard period.
  • FIG. 3 shows a method according to the present invention to implement frequency hopping in a TDMA system as described. While a first synthesiser Si is employed as the transmitting frequency as shown in step 38, a second synthesiser S2 is retuned to the next frequency in wide loop bandwidth mode as in step 30. .After a finite time period, the second synthesiser S2 locks onto a new transmit frequency and maintains wide loop bandwidth mode as in step 32.
  • the transmitter output begins to ramp down until it reaches time 21 when the transmitter output power is inhibited as described by step 40 in FIG. 3.
  • step 34 the first synthesiser Si no longer transmits, step 42.
  • the second synthesiser S2 is still in wide loop bandwidth mode.
  • the transmitter power begins ramping up.
  • step 36 the second synthesiser S2 is in narrow loop bandwidth mode and the power ramp-up is finished.
  • the second synthesiser 2 maintains narrow loop bandwidth.
  • the first synthesiser SI becomes the transmitting frequency, and the second synthesiser S2 reverts back to wide loop bandwidth mode for retuning purposes.
  • This method is repeated and is applied to the first synthesiser SI.
  • a method for implementing frequency hopping is provided where a synthesiser locks onto a frequency in wide loop bandwidth mode, transmits from the first synthesiser, and then converts to a narrow bandwidth mode after a delayed period of time.
  • FIG. 4 shows a synthesiser circuit arrangement for implementing frequency hopping in a time domain system.
  • the circuit arrangement permits the implementation of the above described method. It consists of two phase-locked loop synthesisers 40, 42 and a single pole double throw (SPDT) switch.
  • Each phase-locked loop synthesiser 40 consists of four basic elements, a phase detector 44, a loop filter 46, a voltage controlled oscillator 48 and a frequency divider 45.
  • the gain of the phase detector 44 is adjusted by means of the bandwidth control line 43 as illustrated in FIG. 4.
  • the bandwidth control line 43 is a delayed version of the clock which is employed for selecting the appropriate synthesiser for the transmitting frequency.
  • the bandwidth control line 43 instructs the phase detector 44 to increase its gain accordingly, which results in a corresponding increase in bandwidth.
  • the bandwidth control line 43 instructs the phase detector 44 to decrease its gain producing a corresponding decrease in loop bandwidth.
  • FIG. 5 shows the simulation results of a dual loop bandwidth synthesiser converting to narrow bandwidth before transmitting.
  • FIG. 6 shows the simulation results of a dual loop bandwidth synthesiser maintaining to wide bandwidth mode before transmitting and then converting to narrow bandwidth a time after transmitting according to the method of the present invention.
  • the numbers on FIGS. 5 and 6 relate to the numbers in FIG 2.
  • the present invention provides an apparatus and method for implementing frequency hopping in a time domain system such as a GSM.
  • the method of the present invention requires a synthesiser to switch to a narrow loop bandwidth mode after a finite period of time after a channel is hopped.
  • the benefit of the present invention is twofold. Firstly, due to the wide loop bandwidth during the guard period frequency pulling from impedance mismatches is reduced. Secondly, no additional circuitry is required for the provision of high reverse isolation between the SPDT and the VCO.
  • the proposed technique derives the required clock signal from the burst clock which controls the SPDT switch.
  • This signal has to be delayed in order to provide the loop sufficient time to re-acquire lock-in.
  • the delay has to be short enough to ensure suppression of phase jitter at the start of the burst, since the length of the loop impulse response will be increased.
  • the present invention combines RF technology with the features of the time domain system in order to efficiently implement frequency hopping.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Transmitters (AREA)

Abstract

A method for implementing frequency hopping in a time domain system having at least a first synthesiser including the steps of locking (32) onto a first frequency by the first synthesiser in wide loop bandwith mode, transmitting from the first synthesiser (34), and converting to a narrow bandwith mode (36) on the first synthesiser after a delayed period of time.

Description

PHASE LOCKED LOOP CONTROLLED FREQUENCY SYNTHESIZER FOR USE IN FREQUENCY HOPPING.
Field of the Invention This invention relates in general to communications systems, and more particularly to a method for implementing frequency hopping in a time domain system.
Background to the Invention Base station transceivers for TDMA communications systems such as
DCS 1800, have to be capable of supporting frequency hopping on a time slot by time slot basis. This requirement influences the linearity of the transmitter since power ramping must be employed to reduce spurious emissions from the step changes in transmit frequency. In order to reduce side-lobe levels it is desirable to spread the power ramp over a wide period. As a result, the synthesiser has an extremely small window in which to hop. Several problems are encountered in the implementation of such a synthesiser, such as fast acquisition, low noise and high resistance to frequency pulling. Slow frequency hopping is commonly employed in TDMA based cellular systems. In slow frequency hopping (SFH) the frequency channel is altered at a rate which is lower than the bit rate. For example, in GSM the frequency channel is switched on a burst by burst basis. In GSM, SFH is employed for two reasons, to provide frequency diversity for slow moving mobiles and also inteferer diversity for increasing system capacity.
In order to support slow frequency hopping, it is necessary for the base station to support all time slots during the TDMA frame, consequently, the synthesiser has to frequency hop during a short period which exists between time slots, which is generally referred to as the guard period. The frequency hopping mechanism is usually accomplished by employing two Phase-Locked Loop frequency synthesisers and a single pole double throw switch. When one synthesiser is providing the transmitting frequency, the other is reprogrammed and retuned to the next. The retuning process has to be accomplished within one time slot so that the required transmitting frequency is sufficiently stable before being directed to the transmitter output. This operation is illustrated in FIG. 1, which shows the transmitting frequency allocation per time slot and the guard period. The switching mechanism which selects the appropriate synthesiser, causes an impulsive mismatch in load impedance which pulls the synthesiser off frequency. This causes a corresponding phase disturbance inside the loop which is eventually corrected by the loop feedback mechanism. However, if the synthesiser is unable to respond quickly, then a large phase excursion can occur at the beginning of the time slot resulting in significant performance degradation.
The prior art solution to this problem is to provide an increased reverse isolation between the switch and the synthesiser. This is achieved by cascading several gain blocks interleaved with large attenuators. There are several drawbacks with the prior art solution including:
i) The wide band noise performance of the transmitter can significantly degrade, ii) increasing the number of stages increases the component count, iii) the power consumption of a synthesiser can increase by as much as
40%, iv) the required synthesiser board area can increase by upto 20%.
It is desirable to have a method that would reduce the complexity and expense of the present frequency hopping schemes in time domain systems.
Summary of the Invention
According to the present invention, there is provided a method for implementing frequency hopping in a time domain system having at least a first synthesiser including the steps of locking onto a first frequency by the first synthesiser in wide loop bandwidth mode, transmitting from the first synthesiser, and converting to a narrow bandwidth mode on the first synthesiser after a delayed period of time. In a preferred embodiment the time domain system is a TDMA system.
Brief Description of the Drawing
FIG. 1 illustrates a TDMA frame structure. FIG. 2 illustrates power ramping employed during a guard period of the TDMA frame structure of FIG. 1. FIG. 3 illustrates a flow chart for a preferred embodiment of the present invention.
FIG. 4 is a block diagram of a synthesiser according to the present invention. FIG. 5 simulation results of a synthesiser according to the prior art.
FIG. 6 simulation results of a synthesiser employing the method of the present invention.
Detailed Description of the Preferred Embodiment FIG. 1 shows a frame 2 and slot 4 structure for a time division multiple access (TDMA) system employing frequency hopping. The slots are shown changing frequency from one slot to the next thus each successive TDMA slot 4 is shown as being transmitted on a different frequency. Frequencies are changed during a guard period 6 between two slots. Two synthesisers may be employed to achieve such frequency hopping.
One synthesiser may be transmitting while a second synthesiser is tuning to the next slot's frequency. The synthesisers then switch during the guard period 6. The synthesiser that was transmitting powers down and stops transmitting and the synthesiser that was tuning powers up and starts transmitting on a new frequency. Dual loop bandwidth is employed which has independent control of both noise and switching speed.
In order to suppress the spectral emissions from the rapid switching of frequency channels, power ramping is employed during the guard period. This is illustrated FIG. 2 which shows slot n ramping down 20, 21 and slot n+1 ramping up 22, 23. The designated end of the nth time slot 20 is where the transmitting synthesiser begins ramping down and is the beginning of a guard period 20. At the end of the ramp down 21 and before the beginning of the ramp up 22 of the tuned transmitter is when the synthesisers switch from transmitting to tuning and from tuning to transmitting. The synthesiser that switches from tuning to transmitting begins ramping up 22 and ends ramp up near the start of the n+1 burst 23, the end of the guard period.
FIG. 3 shows a method according to the present invention to implement frequency hopping in a TDMA system as described. While a first synthesiser Si is employed as the transmitting frequency as shown in step 38, a second synthesiser S2 is retuned to the next frequency in wide loop bandwidth mode as in step 30. .After a finite time period, the second synthesiser S2 locks onto a new transmit frequency and maintains wide loop bandwidth mode as in step 32.
Referring to FIG. 2 at the end of a slot time 20, the transmitter output begins to ramp down until it reaches time 21 when the transmitter output power is inhibited as described by step 40 in FIG. 3.
A finite period after ramp down 21 (FIG. 2), the second synthesiser S2 becomes the transmitting frequency as in step 34 (FIG. 3) and the first synthesiser Si no longer transmits, step 42. At this point, the second synthesiser S2 is still in wide loop bandwidth mode. At the end of the PA inhibit period 22 the transmitter power begins ramping up. A finite period later, the loop bandwidth converts to narrow mode operation as in step 36. In step 36, the second synthesiser S2 is in narrow loop bandwidth mode and the power ramp-up is finished. During the complete part of the active time slot and the subsequent ramp down period, the second synthesiser 2 maintains narrow loop bandwidth.
A finite period after the ramp down, the first synthesiser SI becomes the transmitting frequency, and the second synthesiser S2 reverts back to wide loop bandwidth mode for retuning purposes.
This method is repeated and is applied to the first synthesiser SI. Thus, a method for implementing frequency hopping is provided where a synthesiser locks onto a frequency in wide loop bandwidth mode, transmits from the first synthesiser, and then converts to a narrow bandwidth mode after a delayed period of time.
FIG. 4 shows a synthesiser circuit arrangement for implementing frequency hopping in a time domain system. The circuit arrangement permits the implementation of the above described method. It consists of two phase-locked loop synthesisers 40, 42 and a single pole double throw (SPDT) switch. Each phase-locked loop synthesiser 40 consists of four basic elements, a phase detector 44, a loop filter 46, a voltage controlled oscillator 48 and a frequency divider 45. In order to achieve both narrow and wide loop bandwidth modes of operation, the gain of the phase detector 44 is adjusted by means of the bandwidth control line 43 as illustrated in FIG. 4. The bandwidth control line 43 is a delayed version of the clock which is employed for selecting the appropriate synthesiser for the transmitting frequency. When wide loop bandwidth operation is required the bandwidth control line 43 instructs the phase detector 44 to increase its gain accordingly, which results in a corresponding increase in bandwidth. When narrow loop bandwidth operation is required, the bandwidth control line 43 instructs the phase detector 44 to decrease its gain producing a corresponding decrease in loop bandwidth.
FIG. 5 shows the simulation results of a dual loop bandwidth synthesiser converting to narrow bandwidth before transmitting.
FIG. 6 shows the simulation results of a dual loop bandwidth synthesiser maintaining to wide bandwidth mode before transmitting and then converting to narrow bandwidth a time after transmitting according to the method of the present invention. The numbers on FIGS. 5 and 6 relate to the numbers in FIG 2.
The present invention provides an apparatus and method for implementing frequency hopping in a time domain system such as a GSM. The method of the present invention requires a synthesiser to switch to a narrow loop bandwidth mode after a finite period of time after a channel is hopped.
The benefit of the present invention is twofold. Firstly, due to the wide loop bandwidth during the guard period frequency pulling from impedance mismatches is reduced. Secondly, no additional circuitry is required for the provision of high reverse isolation between the SPDT and the VCO.
The proposed technique derives the required clock signal from the burst clock which controls the SPDT switch. This signal has to be delayed in order to provide the loop sufficient time to re-acquire lock-in. However, the delay has to be short enough to ensure suppression of phase jitter at the start of the burst, since the length of the loop impulse response will be increased. Once the loop has converted to a narrow bandwidth its impulse response remains constant during the active part of the burst and also during the power ramp down. When the output power is sufficiently small the power ampUfier is inhibited to prevent spurious emissions. At this point the loop reverts back to its wide bandwidth for hopping to the next frequency channel in the next slot. This process is then repeated for the remainder and successive frames.
The present invention combines RF technology with the features of the time domain system in order to efficiently implement frequency hopping.

Claims

Claims
1. A synthesiser for implementing frequency hopping in a time domain system comprising: means for locking onto a first frequency by the first synthesiser in wide loop bandwidth mode; means for transmitting from the first synthesiser; means for converting to a narrow bandwidth mode on the first synthesiser after a delayed period of time.
2. A method for implementing frequency hopping in a time domain system having at least a first synthesiser comprising the steps of: locking onto a first frequency by the first synthesiser in wide loop bandwidth mode; transmitting from the first synthesiser; converting to a narrow bandwidth mode on the first synthesiser after a delayed period of time.
3. The method of claim 2 wherein the delayed period of time is defined as when a burst is transmitted from the first synthesiser.
4. The method of claim 2 wherein time domain system is a TDMA system.
PCT/EP1995/004783 1994-12-06 1995-12-05 Phase locked loop controlled frequency synthesizer for use in frequency hopping WO1996018245A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8517318A JPH09511639A (en) 1994-12-06 1995-12-05 Method and apparatus for performing frequency hopping in a time domain system
EP95941673A EP0742974A1 (en) 1994-12-06 1995-12-05 Phase locked loop controlled frequency synthesizer for use in frequency hopping

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9424596A GB2295930B (en) 1994-12-06 1994-12-06 Method and apparatus for implementing frequency hopping in a TDMA system
GB9424596.6 1994-12-06

Publications (1)

Publication Number Publication Date
WO1996018245A1 true WO1996018245A1 (en) 1996-06-13

Family

ID=10765494

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1995/004783 WO1996018245A1 (en) 1994-12-06 1995-12-05 Phase locked loop controlled frequency synthesizer for use in frequency hopping

Country Status (5)

Country Link
EP (1) EP0742974A1 (en)
JP (1) JPH09511639A (en)
CA (1) CA2182297A1 (en)
GB (1) GB2295930B (en)
WO (1) WO1996018245A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2323227B (en) * 1997-03-12 2001-01-03 Roke Manor Research Synthesiser
WO1998059436A1 (en) 1997-06-24 1998-12-30 Siemens Aktiengesellschaft Method and device for radiotransmission
GB2340679B (en) * 1998-08-17 2001-11-28 Ericsson Telefon Ab L M Frequency synthesis
US7602253B2 (en) 2006-12-11 2009-10-13 Silicon Image, Inc. Adaptive bandwidth phase locked loop with feedforward divider

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3899746A (en) * 1972-09-22 1975-08-12 Siemens Ag Two oscillators alternately switched into a phase lock loop with outputs taken only during free running period of each oscillator
FR2535545A1 (en) * 1982-10-29 1984-05-04 Thomson Csf Fast acquisition time frequency synthesizer and frequency hopping radio transmission system containing such a synthesizer.
FR2612028A1 (en) * 1987-03-05 1988-09-09 Aerospatiale System for generating microwave-frequency jumps
US4937536A (en) * 1988-08-19 1990-06-26 Hughes Aircraft Company Fast settling phase lock loop
US5224121A (en) * 1992-06-04 1993-06-29 Motorola, Inc. Rolling synthesizer method for baseband slow frequency hopping

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330758A (en) * 1980-02-20 1982-05-18 Motorola, Inc. Synchronized frequency synthesizer with high speed lock
US4568888A (en) * 1983-11-08 1986-02-04 Trw Inc. PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction
US4752749A (en) * 1986-12-22 1988-06-21 Rockwell International Corporation Fast response tuner
JP2806059B2 (en) * 1991-02-14 1998-09-30 日本電気株式会社 Phase locked loop synthesizer
DE69332617T2 (en) * 1992-04-10 2003-11-06 Nec Corp Method for a frequency synthesizer of a TDMA mobile unit with power saving mode during transmission and reception slots

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3899746A (en) * 1972-09-22 1975-08-12 Siemens Ag Two oscillators alternately switched into a phase lock loop with outputs taken only during free running period of each oscillator
FR2535545A1 (en) * 1982-10-29 1984-05-04 Thomson Csf Fast acquisition time frequency synthesizer and frequency hopping radio transmission system containing such a synthesizer.
FR2612028A1 (en) * 1987-03-05 1988-09-09 Aerospatiale System for generating microwave-frequency jumps
US4937536A (en) * 1988-08-19 1990-06-26 Hughes Aircraft Company Fast settling phase lock loop
US5224121A (en) * 1992-06-04 1993-06-29 Motorola, Inc. Rolling synthesizer method for baseband slow frequency hopping

Also Published As

Publication number Publication date
GB2295930A (en) 1996-06-12
GB9424596D0 (en) 1995-02-15
CA2182297A1 (en) 1996-06-13
JPH09511639A (en) 1997-11-18
GB2295930B (en) 1999-11-24
EP0742974A1 (en) 1996-11-20

Similar Documents

Publication Publication Date Title
US5424689A (en) Filtering device for use in a phase locked loop controller
US5745848A (en) Method and apparatus for eliminating interference caused by spurious signals in a communication device
US7911247B2 (en) Delta-sigma modulator clock dithering in a fractional-N phase-locked loop
EP0798880B1 (en) Method for generating frequencies in a direct conversion transceiver of a dual band radio communication system, a direct conversion transceiver of a dual band radio communication system and the use of this method and apparatus in a mobile station
US4969210A (en) Two-way radio having a PLL
KR0178619B1 (en) Apparatus and method for operating a phase locked loop frequency synthesizer responsive to radio frequency channel spacing
GB2317279A (en) Frequency synthesisers
US4348772A (en) Frequency stabilization circuit for a local oscillator
US6163710A (en) Method and apparatus for compliance to multiple frequency plans
JP2002050963A (en) Process and apparatus for reducing power consumption of digital information transmitting/receiving device
EP1356600B1 (en) Method and apparatus for reducing scan time in a radio receiver
US6112068A (en) Phase-locked loop circuit with switchable outputs for multiple loop filters
JPH10247851A (en) Frequency synthesizer of fractional-n type and repeater using the same
EP0742974A1 (en) Phase locked loop controlled frequency synthesizer for use in frequency hopping
US7039062B1 (en) System and method for pulsed cable telephony
JP3749075B2 (en) Oscillation output switching device and radio telephone device
KR100990802B1 (en) Rf synthesizer and rf transmitter or receiver incorporating the synthesizer
JPH1188164A (en) Frequency synthesizer
KR100287898B1 (en) up converter
JPH08242143A (en) Tuning circuit
JP2000201056A (en) Method for correcting frequency of receiver
JPH05335944A (en) Pll synthesizer circuit
JPH06334540A (en) Transmission equipment

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 1995941673

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2182297

Country of ref document: CA

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 1995941673

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1995941673

Country of ref document: EP