WO1995006953A1 - Implanteur d'ions - Google Patents
Implanteur d'ions Download PDFInfo
- Publication number
- WO1995006953A1 WO1995006953A1 PCT/JP1994/001374 JP9401374W WO9506953A1 WO 1995006953 A1 WO1995006953 A1 WO 1995006953A1 JP 9401374 W JP9401374 W JP 9401374W WO 9506953 A1 WO9506953 A1 WO 9506953A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor substrate
- ion
- ion beam
- silicon
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
- H01J37/3171—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation for ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/02—Details
- H01J2237/0203—Protection arrangements
- H01J2237/0213—Avoiding deleterious effects due to interactions between particles and tube elements
Definitions
- the present invention relates to an ion implantation apparatus, and more particularly, to an ion implantation apparatus which reduces metal impurity contamination and is suitable for manufacturing a high-performance semiconductor device.
- FIG. 1 when performing the injecting 2 X 1 0 15 cnf 2 impurity 4 5 0 ° C Aniru in the silicon substrate by using the ion implantation apparatus, the amount of metal impurities to be mixed in the silicon substrate 7 is a graph comparing the pn junction reverse leakage current with that of the pn junction. In the figure, the amount of metal impurities is represented by a ratio with respect to the dose. As is evident from FIG. 10, it is important to reduce the metal impurities mixed into the silicon substrate to reduce the pn junction reverse leakage current.
- the pn junction reverse leakage is reduced by reducing the metal impurity contamination generated in the ion implantation apparatus in front of the semiconductor substrate when viewed from the ion beam traveling direction, that is, by the Faraday cup, scan plate, aperture, etc. Attempts have been made to improve the current.
- Figure 11 shows the results of forming a Pn junction using the above ion implanter and measuring the reverse leakage current. Only it reduces metal impurities incorporated into the semiconductor substrate from where located in front of the ion beam within I O emissions implanter as shown in FIG. 1 1, the pn junction reverse leakage current is at most 1 0 7 A / cm — Currently only two units can be reduced.
- An object of the present invention is to provide an ion implantation apparatus with reduced metal impurity contamination.
- An ion implantation apparatus is directed to an ion implantation apparatus for introducing a predetermined impurity into the semiconductor substrate by irradiating the semiconductor substrate with an accelerated ion beam.
- a portion of the member located behind the semiconductor substrate irradiated with the ion beam is made of a material mainly containing at least one of a semiconductor constituting the semiconductor substrate, or an oxide thereof, or a nitride thereof. Or the surface thereof is covered with the material. It said material is a N-type or P-type silicon, it is preferable that the impurity concentration is IX 1 0 17 cm "or less.
- the semiconductor substrate is irradiated with an accelerated ion beam to thereby introduce a predetermined impurity into the semiconductor substrate.
- a member located behind the semiconductor substrate is configured not to be irradiated with the ion beam.
- a screen having an opening is provided in front of the semiconductor substrate, and the screen is It is preferable that a member located behind the semiconductor substrate is not irradiated with the ion beam.
- At least one of a semiconductor constituting the semiconductor substrate, an oxide thereof, or a nitride thereof is used. It is preferable that it is composed of a material containing one as a main component, or its surface is covered with the material.
- the semiconductor substrate has an outer edge held by a substrate holding member, and at least a surface of the substrate holding member irradiated with an ion beam has at least a surface of a semiconductor constituting the semiconductor or an oxide or nitride thereof. It is characterized by being composed of a material containing at least one as a main component. Still further, a member for providing the above-mentioned ion beam detecting means behind the semiconductor substrate, controlling the ion beam scanning means or the moving means of the semiconductor substrate by the output of the detecting means, and positioning the member behind the semiconductor substrate However, it is preferable that the structure is not irradiated with the ion beam. Action
- FIG. 1 is a conceptual diagram of an ion implantation apparatus showing a first embodiment of the present invention.
- FIG. 2 is a graph showing the relationship between the dose and the metal impurities mixed into the silicon substrate.
- FIG. 3 is a graph showing the relationship between the amount of mixed metal impurity elements and the pn junction reverse leakage current.
- FIG. 4 is a graph showing the relationship between the impurity concentration of the silicon plate for the spatter prevention plate and the amount of impurities flying into the silicon wafer.
- FIG. 5 is a conceptual diagram of an ion injection device showing a second embodiment of the present invention.
- FIG. 6 is a conceptual diagram of an ion implantation apparatus according to a third embodiment of the present invention.
- FIG. 7 is a conceptual diagram of an ion implantation apparatus showing a fourth embodiment of the present invention.
- FIG. 8 is a conceptual diagram of an ion pouring device according to a fifth embodiment of the present invention.
- FIG. 9 is a graph showing a relationship between an annealing temperature and a pn junction reverse leakage current.
- FIG. 10 is a graph showing the relationship between the amount of mixed metal impurity elements and the pn junction reverse leakage current.
- FIG. 11 is a graph showing a relationship between an annealing temperature and a pn junction reverse leakage current.
- FIG. 1 is a drawing of an ion implantation apparatus showing a first embodiment of the present invention, and is particularly shown in a cross-sectional view centering on a wafer holding section.
- 101 is a p-type silicon wafer for ion implantation
- 102 is an electrostatic chuck (wafer holder) for holding the silicon wafer
- 103 is a ground pin, and drops the ground potential to ground.
- Reference numeral 104 denotes a jig (susceptor) for fixing the electrostatic chuck 102, which is made of, for example, an A1 alloy.
- the accelerated ion beam 105 is irradiated to the silicon wafer through an opening 106 ′ of a silicon wafer, which is placed in front of a silicon wafer 101, and ion implantation is performed.
- 106 is made of, for example, silicon, and does not cause metal impurity contamination in silicon 108 even if it is sputtered by ion beams.
- Reference numeral 107 denotes a portion to be irradiated with the ion beam.
- This is a metal spatter prevention plate that is provided to prevent contamination of silicon wafers due to dust.
- the impurity concentration that is processed into a ring shape with 1 0 _l4 cnf 3 following F z Siri Konuweha.
- the spatter prevention plate is installed so as to cover the portion irradiated with ions, such as the A1 alloy jig 104 and the ground pin 103.
- the silicon wafer 101 is held by the electrostatic chuck 102 and the earth pin 103 from the back surface, and the member 106 located in front of the silicon wafer 101 and irradiated by the ion beam is , the impurity concentration is constituted by F z silicon plate below 1 0- 14 c m_ 3, as viewed in the traveling direction of the ion beam, the surface of the member to be positioned in front of Shirikonuweha 1 0 1 is irradiated by the ion beam This prevents metal impurities generated by the mixing from entering the silicon wafer 101. Also, this They are in an ultra-high vacuum of, for example, 5 ⁇ 10 _1 () Torr, and minimize the adsorption of residual gas such as moisture to the wafer surface and entry into the wafer by ion beams.
- FIG. 2 shows the relationship between the dose and the amount of metal impurity contaminants mixed into silicon wafer when AS ions were implanted into silicon wafer at 25 KeV using this embodiment and a conventional ion implantation apparatus.
- the amount of metal impurities was measured by SIMS.
- the metal impurities mixed into the silicon wafer 101 to be ion-implanted can be reduced by about one digit at all doses.
- Figure 3 shows the relationship between the amount of mixed metal impurity elements (expressed as a ratio to the dose) and the pn junction reverse leakage current.
- the amount of mixed metal impurities is 0.01%, and the leakage current is about 10 -7 A / cm 2 , whereas in the present embodiment, the metal impurities generated from the susceptor behind the wafer are By preventing it with 107, the amount of metal impurities mixed was reduced by about an order of magnitude, and the leakage current was also reduced by about an order of magnitude, resulting in an extremely low leakage pn junction of 10 -8 A / cm 2 .
- a practical pn junction can be formed for the first time at a low temperature of 450 ° C.
- a junction by performing ion implantation of a self-aligned source / drain using the A1 gate and annealing after attaching the A1 gate electrode.
- Figure 4 shows the impurity concentration of the Fz silicon wafer 107 used as the anti-sputtering plate and the silicon wafer to be implanted when oxygen ions of 1 ⁇ 10 18 cm— were injected at 20 OKeV in the S IMOX process.
- 4 is a graph showing a relationship with an impurity amount.
- the mixing ratio (the amount of impurity Z which is sputtered and fly to the silicon wafer) differs depending on the ion implanter, but is usually estimated to be 0.001 to 0.1%. Therefore, it can be seen from FIG. 4 that when the mixing ratio is 0.001%, the concentration of the spatter prevention plate 107 must be suppressed to 5 ⁇ 1 O 1 ′ ⁇ 3 or less.
- its concentration must be 5x10 lD cnf 3 or less, and if it is 0.1%, its concentration must be 5 x 10 15 cm “ 3 or less. In particular, it is preferably 1 x 10 14 cnf 3 or less. This enables more accurate impurity concentration control.
- the Fz silicon wafer 107 may be replaced when ions are implanted at a high concentration after a certain period of time. In other words, pollution can be efficiently reduced by simple maintenance.
- Fz silicon wafers having an impurity concentration of 1 ⁇ 10 14 cnf 3 or less have been described, but Cz silicon wafers or EPi silicon wafers may be used.
- 1 X 10 14 cm_ may be three or more non-pure concentration, for example, cost cheaper, a Frequently used impurity concentration 10 15 cm ⁇ stand C z silicon wafer using You may. Also, higher concentrations than this may be used. It is desirable that the silicon wafer has a low impurity concentration.
- the spatter prevention plate 107 may be made of a material other than silicon, for example, silicon oxide or silicon nitride.
- the sputter prevention plate 107 is a silicon oxide, it does not become a contamination source even if sputtered and mixed into the silicon wafer. There is no problem when ion implantation is performed using the silicon oxide film as a mask, and the same can be said when the silicon oxide film is a silicon nitride film.
- the case where the Fz silicon wafer is used as the spatter prevention plate 107 has been described, but silicon or silicon oxide or silicon nitride is directly deposited on the susceptor 104 by a CVD spacer. Is also good.
- silicon wafer is used as the semiconductor substrate.
- the present invention is not limited to a silicon semiconductor, and is suitably applied to Ge or a compound semiconductor.
- FIG. 5 is a drawing of an ion implantation apparatus showing a second embodiment of the present invention, and is particularly shown in a sectional view centering on a wafer holding section.
- the same components as those in FIG. 1 are indicated by the same numbers.
- the diameter of the opening 106 ′ is designed to be such that the silicon holder 104 behind the silicon wafer 101 is not irradiated with the ion beam 105.
- the plate 106 is made of a silicon plate, and does not cause metal impurity contamination on the silicon substrate 101 even if it is sputtered by ion beams.
- the impurity concentration was used 1 0 14 cm_ 3 following F z sheet Rikonuweha.
- the diameter of the silicon wafer 101 is 33 ⁇
- the opening of the new wafer 106 is 28 mm0
- the distance of the new silicon wafer is 101
- the distance of the silicon wafer 101 is 200. did.
- the silicon wafer 101 used 33 mm diameter, but this may be 6 inches, 8 inches or more, and in these cases, the opening should be determined to be slightly smaller than the diameter of the wafer. Good.
- the distance between the contact and the silicon wafer is not limited to the value of the present embodiment as long as the distance is between the X scan plate and the Y scan plate that determine the scan area of the wafer and the silicon wafer. Desirably, the closer to the silicon wafer, the more accurate the snow behind the silicon wafer. Can be prevented.
- Toko filtration to regard the leakage current of the pn junction were measured in the same manner as in Example 1, becomes 1 0- 8 A / cm 2 or so, very effectively suppressed ion implantation apparatus of the present embodiment is the incorporation of metal impurities It was confirmed that it was possible.
- the opening 106 ′ of the unit 106 is circular.
- the shape of the opening 106 ′ is May be squared.
- FIG. 6 is a drawing of an ion implantation apparatus showing a third embodiment of the present invention, and is particularly a sectional view mainly showing a wafer holding section.
- a silicon wafer 601 to be subjected to ion implantation is held in a wafer holder 602 by a jig 603 coated with silicon of the present invention.
- the jig 603 is made by depositing l ⁇ m of silicon on an aluminum alloy by the CVD method, and is designed to be larger than the area scanned by the ion beam 604. Therefore, the ion beam irradiates only the jig 603 coated with silicon, except for the silicon wafer, and does not cause metal impurity contamination therefrom.
- the area irradiated with the jig 603 is small. If the silicon wafer 601 to be ion-implanted is circular, the ion beam is scanned in a circular shape, and a circular jig 6 larger than that is scanned. In this case, it is preferable that the jig 603 be square and the jig 603 also be square without waste.
- the jig 603 coated with 1 zm of silicon by the CVD method has been described.
- the thickness is not limited to 1 ⁇ m. This thickness depends on the purpose, such as the accelerating voltage and ion species, and is set to 1; ⁇ with a margin.
- the concentration of silicon deposited by the CVD method varies depending on the purpose, but non-doped silicon is preferable.
- the jig 603 coated with silicon has been described.
- this jig may be a jig made of silicon, or may be a jig made by attaching silicon alloy to an aluminum alloy.
- the semiconductor substrate is a Ge-based semiconductor or a compound semiconductor such as GaAs
- the semiconductor constituting the semiconductor or its oxide or Similar effects can be obtained by coating with a material containing at least one of the nitrides as a main component. (Example 4)
- FIG. 7 is a drawing of an ion implantation apparatus showing a fourth embodiment of the present invention, and particularly shows a sectional view of a wafer holding section from a beam line.
- reference numeral 701 denotes a silicon wafer for ion implantation (33 reference 0)
- reference numeral 702 denotes an electrostatic chuck for holding the silicon wafer
- reference numeral 703 denotes a single spin
- a potential of the wafer To ground.
- Reference numeral 704 denotes a jig for fixing the electrostatic chuck 702, and is made of, for example, an A1 alloy.
- the accelerated ion beam 705 is scanned in the X and Y directions by a Y-scanner plate 706 and an X-scanner plate 707 (ion beam scanning means), respectively, and an X-scan aperture 708 and a beam line are provided.
- Aperture 709, Faraday cup 710, and silicon wafer 701 The silicon wafer 701 is illuminated through a rounded opening (40 mm ⁇ ) of silicon wafer 711 placed in front of it, and the silicon wafer is irradiated. An injection is performed. In addition, the distance between the new one and the silicon seven hundred seventy-one was set to 200.
- the Y-scanner plate 706 and the X-scanner plate 705 are used so that the ion beam 705 does not irradiate the wafer holder 704 at all, and only the inside of the silicon wafer 701 is ion-implanted. Controlled by 07 and scanning in the XY directions. When ions are implanted into a square liquid crystal panel, they are scanned squarely without overscanning, and when ions are implanted into a round silicon wafer, they are scanned circularly. The scanning range can be easily determined if the position of the holder and the size of the silicon are known.
- an ion beam detection means such as a post-stage Faraday cup is installed behind the silicon wafer, and feedback is applied when an ion beam is detected, so that the Y-scanner plate 706 and the X-scanner plate 707 can be controlled in real time. It is.
- the electrostatic deflection type ion implantation apparatus has been described. However, the same can be said for a parallel implantation ion implantation apparatus.
- FIG. 8 is a drawing of an ion implantation apparatus showing a fifth embodiment of the present invention,
- the holding part is ⁇ ;
- a silicon wafer 801 to be subjected to ion implantation is held from the back of the wafer by an electrostatic chuck (not shown) and an earth pin (not shown).
- Reference numeral 804 denotes a jig for fixing the electrostatic chuck
- reference numeral 805 denotes an arm having a mechanism for rotating the needle vertically, horizontally, and further.
- the accelerated ion beam 806 is not scanned, and is constantly irradiated onto the silicon wafer through the opening 807 made of silicon to perform ion implantation.
- the silicon wafer is mechanically controlled to scan only the inside of the silicon wafer 801 without irradiating the ion beam 806 force holder 804 at all, and scan in the XY direction. are doing.
- the wafer is scanned squarely without overscanning, and when implanting ions into a round silicon wafer, the wafer is scanned circularly.
- the scanning range can be easily determined if the size and shape of the silicon wafer are known. Also, the scanning area should be as large as possible if it is inside the silicon wafer. This is because silicon wafers can be used more effectively.
- scanning may be performed by controlling the speed in the vertical and horizontal directions.
- the wafer may be rotated and scanned in the left / right (up / down) direction to control the number of rotations and the scanning speed so that the wafer may be uniformly injected.
- metal impurity contamination from a member located behind the semiconductor substrate is reduced, and the Pn junction reverse leakage current is reduced.
- a high-performance semiconductor device such as a small number of semiconductor devices can be provided.
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- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
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Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94924392A EP0722181A4 (en) | 1993-08-20 | 1994-08-19 | ION IMPLANTER |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5206742A JPH0765778A (ja) | 1993-08-20 | 1993-08-20 | イオン注入装置 |
JP5/206742 | 1993-08-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1995006953A1 true WO1995006953A1 (fr) | 1995-03-09 |
Family
ID=16528354
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1994/001374 WO1995006953A1 (fr) | 1993-08-20 | 1994-08-19 | Implanteur d'ions |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0722181A4 (ja) |
JP (1) | JPH0765778A (ja) |
WO (1) | WO1995006953A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002329677A (ja) * | 2001-04-27 | 2002-11-15 | Semiconductor Energy Lab Co Ltd | ドーピング装置 |
KR100412354B1 (ko) * | 2001-05-30 | 2003-12-31 | 삼성전자주식회사 | 이온주입장치 |
JP6336894B2 (ja) * | 2014-11-21 | 2018-06-06 | 日本電子株式会社 | 試料作製装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6113542A (ja) * | 1984-06-28 | 1986-01-21 | Nippon Telegr & Teleph Corp <Ntt> | イオン注入用マスク装置及びそれを用いたイオン注入法 |
JPH0346741A (ja) * | 1989-07-10 | 1991-02-28 | Applied Materials Inc | 半導体ウェーハの処理工程中の核種の相互汚染の防止方法と装置 |
JPH04363854A (ja) * | 1991-06-10 | 1992-12-16 | Nissin Electric Co Ltd | イオン処理装置 |
JPH05217541A (ja) * | 1992-02-03 | 1993-08-27 | Hitachi Ltd | 半導体ウエハの処理装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54106180A (en) * | 1978-02-08 | 1979-08-20 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor integrated circuit |
EP0217616A3 (en) * | 1985-09-23 | 1989-01-25 | Vg Instruments Group Limited | Substrate processing apparatus |
EP0405855A3 (en) * | 1989-06-30 | 1991-10-16 | Hitachi, Ltd. | Ion implanting apparatus and process for fabricating semiconductor integrated circuit device by using the same apparatus |
JPH0473932A (ja) * | 1990-07-16 | 1992-03-09 | Fujitsu Ltd | 半導体製造装置 |
-
1993
- 1993-08-20 JP JP5206742A patent/JPH0765778A/ja active Pending
-
1994
- 1994-08-19 EP EP94924392A patent/EP0722181A4/en not_active Withdrawn
- 1994-08-19 WO PCT/JP1994/001374 patent/WO1995006953A1/ja not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6113542A (ja) * | 1984-06-28 | 1986-01-21 | Nippon Telegr & Teleph Corp <Ntt> | イオン注入用マスク装置及びそれを用いたイオン注入法 |
JPH0346741A (ja) * | 1989-07-10 | 1991-02-28 | Applied Materials Inc | 半導体ウェーハの処理工程中の核種の相互汚染の防止方法と装置 |
JPH04363854A (ja) * | 1991-06-10 | 1992-12-16 | Nissin Electric Co Ltd | イオン処理装置 |
JPH05217541A (ja) * | 1992-02-03 | 1993-08-27 | Hitachi Ltd | 半導体ウエハの処理装置 |
Non-Patent Citations (1)
Title |
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See also references of EP0722181A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP0722181A4 (en) | 1997-01-08 |
JPH0765778A (ja) | 1995-03-10 |
EP0722181A1 (en) | 1996-07-17 |
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