WO1991010170A1 - Appareil de masquage programmable - Google Patents

Appareil de masquage programmable Download PDF

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Publication number
WO1991010170A1
WO1991010170A1 PCT/US1990/007331 US9007331W WO9110170A1 WO 1991010170 A1 WO1991010170 A1 WO 1991010170A1 US 9007331 W US9007331 W US 9007331W WO 9110170 A1 WO9110170 A1 WO 9110170A1
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WO
WIPO (PCT)
Prior art keywords
masking device
recited
providing
target surface
pixels
Prior art date
Application number
PCT/US1990/007331
Other languages
English (en)
Inventor
Hector Franco
Original Assignee
Manufacturing Sciences, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Manufacturing Sciences, Inc. filed Critical Manufacturing Sciences, Inc.
Publication of WO1991010170A1 publication Critical patent/WO1991010170A1/fr

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70283—Mask effects on the imaging process
    • G03F7/70291—Addressable masks, e.g. spatial light modulators [SLMs], digital micro-mirror devices [DMDs] or liquid crystal display [LCD] patterning devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H1/00—Holographic processes or apparatus using light, infrared or ultraviolet waves for obtaining holograms or for obtaining an image from them; Details peculiar thereto
    • G03H1/22—Processes or apparatus for obtaining an optical image from holograms
    • G03H1/2294—Addressing the hologram to an active spatial light modulator
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03H—HOLOGRAPHIC PROCESSES OR APPARATUS
    • G03H2225/00—Active addressable light modulator
    • G03H2225/20—Nature, e.g. e-beam addressed
    • G03H2225/22—Electrically addressed SLM [EA-SLM]

Definitions

  • This invention relates generally to a programmable masking apparatus and more particularly to a liquid crystal based, electronically programmable high resolution masking device and method for use in conjunction with image generation and image transfer systems.
  • a specific application of the present invention relates to programmable masking devices for use in conjunction with exposure systems for the purpose of generating photolithographic images on photosensitive surfaces.
  • An even more specific application of the present invention relates to programmable reticles or masks for use in conjunction with ultraviolet exposure systems in the photolithographic processes associated with semiconductor manufacturing.
  • such programmable reticles or masks utilize a liquid crystal micro-array of programmable pixels to define the desired opaque and transparent patterns of the reticles or masks.
  • Photolithographic pattern generation relies mostly on optical exposure systems which transfer fixed patterns, previously defined on masking devices, to photosensitive target surfaces in the fo ⁇ n of latent images. Such photolithographic pattern generation is widely used in the industry in large volume processes requiring pattern replication.
  • masking devices typically consist of glass or quartz substrates wherein the desired patterns are defined on hard surface films such as chrome or iron oxide. These films must be opaque to the ultra violet light required for the operation of the wafer exposure systems used in the microlithography of semiconductor wafers.
  • the masking devices are used in two distinct configurations. In the first configuration, known as a mask, the masking device comprises a large number of identical patterns, where each pattern corresponds to a semiconductor device or circuit In the second configuration, known as a reticle, the masking device typically comprises the patterns corresponding to one integrated circuit
  • Masks are used with wafer exposure systems which transfer the mask patterns to a wafer surface in a single operation. Reticles are used with wafer exposure systems known as wafer steppers which transfer the pattern on the reticle to a large number of sites on the wafer by sequentially stepping from site to site and repeating the exposure operation at each site.
  • these masks and reticles are typically fabricated with electron beam writing systems which, by means of photolithographic techniques, translate computer aided design (CAD) data into permanent patterns on the surface of the transparent substrate.
  • CAD computer aided design
  • the complete wafer fabrication process for each specific device or integrated circuit requires a set of masks and/or reticles which comprises all the patterning layers required by the specific fabrication process. Depending upon technology, the number of these layers may vary from a few, for very simple processes, to approximately 30 for very complex processes, with 12 to 16 being typical for most integrated circuit process technologies.
  • Masks and reticles currently range in cost from $400 to over $1,500 and typically take two weeks to obtain when ordered from commercial suppliers.
  • integrated circuit layouts are often revised, requiring the generation of new sets of masks and/or reticles with each revision.
  • wafer fabrication facilities are often burdened with substantial mask and reticle inventory costs.
  • the delays associated with the introduction of new masks and/or reticles delay the introduction of new products and product improvements, severely limiting potential profitability.
  • the masks and/or reticles are installed in exposure systems and must be frequently changed to accommodate the production requirements of a large combination of layers and products. These frequent changes result in substantial setup time penalties, causing a reduction in productivity of the associated exposure systems, which normally range in cost from $500,000 to over $1,000,000 each.
  • Direct electron beam writing systems can technically perform this task.
  • their costs are in the millions of dollars and their throughputs are limited to a few wafers per hour compared to 30 to 60 wafers per hour for ultra violet exposure systems.
  • These constraints make direct electron beam writing a cost ineffective technology for wafer manufacturing.
  • the practical use of such direct electron beam writing systems has been limited to research projects and to the commercial production of masks and reticles for use in conjunction with ultraviolet exposure systems.
  • Wafer scale integration is a technology outlined in further detail under the section covering the objects and advantages of the present invention.
  • the general object of the present invention is to provide electronically programmable high resolution masking devices.
  • Such programmable masking devices will use liquid crystal technology to define an electronically programmable micro array of pixels.
  • the optical resolution of these devices will be compatible with the specific requirements of each application.
  • the pixels can be individually programmed to be transparent or opaque to the light used in conjunction with each specific type of application of the present invention.
  • Driving circuitry will control the rows and columns of such micro array, providing the capability of applying the appropriate control voltage to each pixel as means of defining the desired patterns.
  • a bit map micro array memory will store the pattern data which is conveyed to the pixels via the driving circuitry.
  • Interface circuitry will be incorporated enabling computer systems to communicate with the micro array memory in both the read and write modes.
  • Another general object of the present invention is to provide electronically programmable high resolution masking devices for use in conjunction with image transfer systems, as means for implementing direct imaging of computer generated patterning data onto photosensitive substrates or surfaces.
  • Still another object of the present invention is to provide programmable reticles and masks which can be integrated into the ultraviolet exposure systems used in semiconductor manufacturing, for the purposes of implementing, in real time, direct imaging of pattern generation data onto the surface of semiconductor waters.
  • Wafer scale integration refers to the creation of a complete electronic system on a silicon wafer, involving the three fundamental technologies outlined below:
  • Additional objects of the present invention are to provide electronically programmable high resolution masking devices for use in visual display projection systems, real time holography, printing systems and other applications requiring the high resolution and programmability of the present invention. DESCRIPTION OF THE DRAWINGS
  • Fig. 1 is a simplified plan view depicting the principal components of a preferred embodiment of the present invention
  • Fig. 2 is a representational partial cross section taken along the line 2-2 in Fig. 1 depicting a portion of an active liquid crystal micro array and the peripheral circuitry associated with it;
  • Fig. 3 is a pictorial representation of the conductive coatings which serve as pixel electrodes for the active liquid crystal micro array shown in Fig. 1;
  • Fig. 4 is a representational partial top plan view illustrating the configuration of the active liquid crystal micro array shown in Fig. 1;
  • Fig. 5 is a representational partial cross section taken along the line 5-5 in Fig. 4 illustrating the configuration of one of the transistor switches used in the active liquid crystal micro array;
  • Fig. 6 is a pictorial representation of the micro array interconnection system comprising control lines, data lines, transistor switches and pixel electrodes in accordance with the present invention
  • Fig. 7 is a representational partial plan view depicting the common electrode, pixel electrodes, gate control lines and data lines of the preferred embodiment
  • Fig. 8 depicts two alternative configurations for the common electrode of Fig. 7 comprising (1) the addition of orthogonal metal traces to lower the sheet resistance of this electrode and (2) the addition of red (R), green (G) and blue (B) color filters for digital color imaging;
  • Fig. 9 is a representational partial cross section taken along the line 9-9 in Fig. 8, to further illustrate the orthogonal metal traces;
  • Fig. 10 is a representational partial top plan view similar to that shown in Fig. 4 with the exception of the transistor switches which are configured with redundant terminals, depicting an alternate embodiment of the present invention
  • Fig. 11 is a representational partial cross section taken along the line 11-11 in Fig. 10 showing a redundant field effect transistor switch with one source, two gates and two drains;
  • Fig. 12 is a representational partial top plan view illustrating a temporary interconnection system used for testing the integrity of the transistor switches associated with each of the pixels in the micro array;
  • Fig. 13A is a representational partial cross section illustrating a defect on the first layer metal of a redundant double layer metal interconnecting system
  • Fig. 13B is a representational partial cross section illustrating a defect on the second layer metal of a redundant double layer metal interconnecting system
  • Fig. 14A is a representational partial top plan view illustrating the principle for the dual layer interconnecting system according to one of the proposed embodiments of the present invention.
  • Fig. 14B is a representational partial top plan view illustrating a preferred configuration of the peripheral interconnect system comprising three layers of metalization;
  • Fig. 15 is a representational partial top plan view illustrating a contactless connector system used in accordance with the present invention and comprising infrared transmitters and receivers;
  • Fig. 16 is a representational partial cross section taken along the line 16-16 in Fig. 15 showing the configuration of the contactiess connector system illustrated in Fig. 15;
  • Fig. 17 is a simplified schematic diagram illustrating one of the preferred circuits used to control the voltage applied to each pixel as means of modulating its transparency;
  • Fig. 18 is a pictorial representation of a photolithographic exposure apparatus illustrating the use of the programmable masking device of the present invention to generate images on a photosensitive target surface from data provided by a computer system;
  • Fig. 19 is a pictorial representation illustrating the use of the programmable masking device of the present invention in a visual display projection system
  • Fig. 20 is a pictorial representation illustrating the use of the programmable masking device of the present invention in a three dimensional projection viewing system
  • Fig. 21 is a pictorial representation illustrating the use of the programmable masking device of the present invention in a holographic imaging apparatus
  • Fig. 22 is a pictorial representation illustrating the use of the programmable masking device of the present invention in a printing apparatus.
  • Fig. 1 is a simplified plan view depicting the most relevant elements comprised in the preferred embodiments of the present invention. These elements are not necessarily included in each of these embodiments but are incorporated in this figure for reference in the descriptions which follow.
  • This figure shows the active liquid crystal micro array 101 which is fully described in the first embodiment and represents the key element of the present invention. Within the micro array this figure shows the gate control lines 114 which must be sequentially enabled to provide a control voltage, via the data lines 115, to each pixel in the micro array.
  • the area surrounding the micro array provides space for the peripheral interconnect system 138 which is described in the fourth embodiment
  • This peripheral interconnect system comprises the integrated circuits in die form 143, other interconnections shown in further detail in Fig.
  • Fig. 2 is a representational partial cross section taken along line 2-2 in Fig. 1 depicting a portion of an active liquid crystal micro array and the peripheral circuitry associated with it
  • the structural elements of the peripheral interconnect system pertain to the fourth embodiment of the present invention and their description is covered in detail in that section.
  • This first embodiment of the present invention comprises a glass primary substrate 102 and a glass secondary substrate 103, both bonded to a thin perimeter spacer 109 which holds the substrates in close proximity and parallel to each other.
  • the volume delimited by these two parallel substrates and the perimeter spacer forms a sealed chamber containing a liquid crystal material 108.
  • Each of the substrates is coated, on the inner side of the chamber, with a thin conductive transparent film such as aluminum or indium tin oxide. These conductive films are used to define the electrodes necessary for the operation of the liquid crystal.
  • the coating On the primary substrate 102 the coating is patterned to form a micro array of discrete pixel electrodes 104 organized in rows and columns.
  • the coating On the secondary substrate 103 the coating is continuous and forms the common electrode 105. This electrode encompasses an area equivalent to the entire micro array area defined on the primary substrate 102.
  • the space between adjacent pixel electrodes is called the pixel gap 106.
  • the areas defined by the pixel gaps 106 are used to locate the transistor switches 107 by means of which the desired control voltages are applied to each of the pixel electrodes 104.
  • the primary substrate 102 and the secondary substrate 103 are both coated on the outer side of the chamber with a polarizing film shown in Fig. 2 as the primary substrate polarizer 202 and the secondary substrate polarizer 203. These polarizing films are oriented such that the polarization angle between them is 90 degrees, thereby insuring that no light can be transmitted through both polarizing films when the polarization angle is not rotated by the liquid crystal material 108.
  • Fig. 3 is a perspective representation of the conductive coatings which serve as pixel electrodes for the active liquid crystal micro array of Figs. 1 and 2. It shows the pixel electrodes 104, the common electrode 105 and the pixel gaps 106.
  • the area encompassed by the pixel gaps of the entire micro array forms a set of rows and columns with a width equal to the pixel gap 106. This area is used to locate the active electrical components and the interconnection system required for the operation of the liquid crystal micro array.
  • the interconnection system incorporates a set of conductive traces which are extended towards the periphery of the micro array and are shown in several of the figures herein as the conductive trace extensions 139 (see Fig. 1). These traces provide the electrical connections between the pixel electrodes 104 and the control circuitry.
  • the above configuration is similar to that found in some active matrix liquid crystal displays. However, it differs with regards to the pixel size, the pixel gap and other features applicable to the various embodiments of the present invention.
  • Fig. 4 is a representational partial top plan view illustrating the configuration of the active liquid crystal micro array shown in Fig. 1.
  • the active electrical components are MOS thin film transistors made of polycrystalline silicon, commonly known as polysilicon.
  • polysilicon commonly known as polysilicon.
  • other semiconductor materials and device structures could be used in different embodiments.
  • the polysilicon is patterned in rectangular islands 110 laying along the columns of pixel gaps 106.
  • the polysilicon could be patterned in long strips covering the entire length of the columns of pixel gaps 106.
  • the MOS transistors are configured with the control gate area 111 of each transistor in line with a row of pixel gaps 106. This configuration offers a simple layout where the gate control lines 114 are straight metal traces patterned over the rows of pixel gaps 106, thus creating a common gate electrode for all the MOS transistors in a row .
  • the other two electrodes of the MOS transistor, known as the source and the drain are patterned as a source contact 112 and a drain contact 113 to the polysilicon material.
  • the source contact is connected to the pixel tab 116 of an adjacent pixel electrode 104 and the drain contact is connected to a metal trace forming a data line 115 patterned over the column of pixel gaps in which the transistor is located.
  • Fig. 5 is a representational partial cross section taken along the line 5-5 in Fig. 4 illustrating the configuration of one of the transistor switches used in the active liquid crystal micro a ⁇ ay.
  • the cross section shows the structure of the MOS transistor with the source 118 and the drain 117 formed in the polysilicon island 110.
  • the pixel tab 116 is patterned over the source contact 112 and the data line 115 is connected to the drain contact 113.
  • the gate structure is formed by the oxide 119, which is thermally grown over the polysilicon island 110.
  • the cross section also shows that the data line 115 which runs over the polysilicon islands along the columns of pixel gaps is electrically isolated from the underlying structures by the dielectric 120.
  • Fig. 6 is a pictorial representation of the active matrix interconnection system comprising the control lines 114, the data lines 115, the transistor switches 121 and the pixel electrodes 104. It further illustrates, in schematic form, the configuration of the interconnection system through which control voltages are applied to the pixel electrodes.
  • the pixel tab 116 of each pixel electrode 104 is connected to a data line 115 via a simulated transistor switch 121.
  • the trace on a specific row is connected to the control gates of all the transistor switches 121 on that row and becomes a gate control line 114.
  • the trace on a specific column is connected to the other electrode of all the transistor switches 121 on that column and becomes a data line 115.
  • the pixel gaps 106 are also shown.
  • Fig. 7 is a representational partial plan view depicting the common electrode 105, the pixel electrodes 104, the gate control lines 114 and the data lines 115 which are shown with an interdigitated layout
  • the configuration described above offers a simple layout where the gate control lines 114 and the data lines 115 are straight metal traces patterned over the rows and columns of pixel gaps. Both of these sets of traces are extended beyond the edge of the micro array of pixels to an area where it is practical and feasible to create electrical connections to the drive circuitry which controls the electronic state of each pixel.
  • the data lines 115 are depicted with interdigitated extensions, whereas the gate control lines 114 are depicted with non interdigitated extensions.
  • the common electrode 105 deposited on the secondary substrate and shown on a higher plane, in this figure, is connected to a perimeter trace 122 which is patterned around the perimeter of the common electrode 105. In turn, this perimeter trace is connected to the electrical ground of the primary substrate interconnection system. Also shown in this figure, in a lower plane, are the pixel electrodes 104.
  • Fig. 8 depicts two alternative configurations for the common electrode 105 comprising (1) the addition of orthogonal metal traces to lower the sheet resistance of this electrode and (2) the addition of red (R), green (G) and blue (B) color filters for digital color imaging.
  • This figure shows the common electrode 105 and the perimeter trace 122 described above.
  • the first alternative configuration comprises a set of orthogonal metal traces 123 deposited over those areas which match the rows and columns of pixel gaps on the primary substrate. These orthogonal metal traces divide the common electrode 105 into pixel areas 124 which match the pixel electrodes on the primary substrate. As a result, the effective sheet resistance of the common electrode 105 will be substantially reduced causing the micro array to respond faster to the control signals which deteraiine the state of each pixel.
  • This first alternative configuration can be further modified to provide a precise edge definition of each pixel.
  • the complex structures built on the surface of the primary substrate may cause a minimum amount of pixel edge irregularities. Such irregularities will not be resolved by the image transfer optics of the exposure system and, therefore, will not impair the satisfactory operation of this device.
  • the second alternative configuration comprises further the deposition of red (R), green (G) and blue (B) color filters over the pixel areas 124, as shown in Fig. 8, for applications of the present invention requiring color imaging.
  • Fig. 9 is a representational partial cross section taken along the line 9-9 in Fig. 8 to further illustrate the orthogonal metal traces 123.
  • the conductive film which forms the common electrode 105 is deposited over the secondary substrate 103 and the orthogonal metal traces 123 are then deposited on the lower surface of the common electrode 105.
  • the space between the metal traces 123 comprises the pixel areas 124 described above. Since the sheet resistivity of these metal traces is orders of magnitude lower than that of the conductive film which forms the common electrode 105, the effective sheet resistance of the common electrode 105 is substantially reduced by the addition of these orthogonal metal traces 123.
  • any embodiment of the present invention must satisfy two fundamental conditions:
  • the pixel size in the micro array must be such that the resulting size of the pixel image on the target surface is compatible with the applicable pattern generation design rules. More specifically, the size of the pixel image on the target surface must be such that the minimum feature size dictated by the applicable pattern generation design rules will be equal to or will be a multiple of the size of the pixel image on the target surface.
  • the width of the pixel gap in the micro array must be less than the minimum size which can be resolved by the image transfer optics of the photolithographic exposure system. This condition will insure that the patterns imaged on the target surface are free of gaps between adjacent pixels.
  • the pixel size and the width of the pixel gap in any embodiment of the present invention, must be tailored to comply with the requirements dictated by the exposure system to be used and the minimum feature size to be produced.
  • 1 Pixels in the micro array may have a variety of different shapes such as circular,
  • 10 micro array may range from 100 million to over one billion. Such types of
  • Such micro array would comprise a total of 225 million pixels and encompass an
  • the first embodiment of the present invention would have a high probability of exhibiting at least one defect in the control gate of one of the transistor switches, and at least eleven defects in the interconnect system metal traces. Since these programmable masking devices must be defect free, the first embodiment, described above, are not recommended for applications requiring very high density micro arrays.
  • Connectivity also presents a technological difficulty.
  • the micro array would have two orthogonal sets of metal traces. Each set would comprise 15,000 traces, one micron wide, with four micron spaces between two adjacent traces. The connection of these traces to the drive circuitry via any type of cabling system would be clearly impractical if not impossible to implement, making the first embodiment of the present invention, described above, undoable for this type of application.
  • the second embodiment of the present invention is described with reference to figures 10, 11 and 12. This embodiment is configured with double transistor switches to address the gate area integrity problem discussed above.
  • Fig. 10 is a representational partial top plan view similar to that shown in Fig. 4 with the exception of the transistor switches which are configured with redundant gate and drain terminals. Like Fig. 4, this figure shows the pixel electrodes 104 connected to the source contact 112 of the transistor switch, via the pixel tab 116. However, the transistor switches in this second embodiment are configured with two control gates and two drain contacts shown in this figure as the primary control gate 125, the primary drain contact 126, the secondary control gate 127 and the secondary drain contact 128. As explained in further detail below, these secondary electrodes are used to replace the primary electrodes when the presence of a defect in the primary control gate causes the transistor switch to malfunction.
  • the secondary control gate 127 When required, due to a defective primary control gate 125, the secondary control gate 127 is connected to the gate control line 114 by a metalization patch shown as the secondary control gate connection 129.
  • the procedure for applying this metalization patch is described in detail under the special test and repair procedure at the end of this section. Also shown in this figure are the data lines 115, the pixel gaps 106 and the polysilicon islands 210, all of which have been explained with reference to Fig. 4.
  • Fig. 11 is a representational partial cross section taken along the line 11-11 in Fig. 10 showing a redundant field effect transistor switch with one source, two gates and two drains.
  • the cross section shows the structure of the redundant MOS transistor with the source 118, the primary drain 130 and the secondary drain 131 formed in the polysilicon island 210.
  • the pixel tab 116 is patterned over the source contact 112.
  • the data line 115 is shown connected to the secondary drain contact 128 rather than the primary drain contact 126.
  • This figure is intended to illustrate the secondary control gate connection 129 connecting the secondary control gate 127 to the gate control line 114. When the primary control gate 125 is found to be defective, this alternate connection is made in its place.
  • the cross section also shows the thermal oxide 119 and the dielectric 120 which have previously described with reference to Fig. 4.
  • Fig. 12 is a representational partial top plan view illustrating a temporary interconnection system used for testing the integrity of the transistor switches associated with each of the pixels in the micro array.
  • Each polysilicon island 210 has one source contact 112, a primary control gate 125, a primary drain contact 126, a secondary control gate 127 and a secondary drain contact 128.
  • the temporary interconnection system comprises a set of temporary source test lines 132 and a set of temporary drain test lines 133. Each temporary source test line 132 is connected to the source contact 112 of each of the transistor switches adjacent to that line and each temporary drain test line 133 is connected to the primary drain contact 126 of each of the transistor switches adjacent to that line.
  • each gate control line 114 is connected to the primary control gate 125 of each transistor in the row associated with that gate control line. With this temporary interconnection system every transistor switch in the micro array can be individually tested for functional integrity.
  • the secondary control gates 127 and the secondary drain contacts 128 are not connected during this test procedure. All gate control lines 114, temporary source test lines 132 and temporary drain test lines 133 are terminated on probing pads providing electrical access to these interconnections.
  • a primary control gate is found to be defective, as determined by test procedures such as those outlined at the end of this section, alternate connections are made in place of their primary counterparts.
  • the secondary control gate 127 is connected to the gate control line 114 via the alternate gate connection 227 and the secondary drain contact 128 is connected to the temporary drain test line 133 via the alternate drain connection 228.
  • Fig. 12 also depicts the defective gate area 225 and the primary drain link 226 explained with reference to an alternate interconnection procedure used to modify these metal interconnections which is outlined at the end of this section . This procedure is an integral part of the technology required for the production of the various embodiments of the present invention.
  • the third embodiment of the present invention is described with reference to figures 13A and 13B.
  • This embodiment is identical to either of the previously described embodiments except that it is configured with two layers of metal traces directly applied over each other as a means of circumventing the metal trace discontinuities generated by photolithographic defects.
  • Fig. 13A is a representational partial cross section illustrating a defect on the first layer metal of a redundant double layer metal interconnecting system. It depicts the second layer metal 135 directly superimposed over the first layer metal 134 and a typical defect on the first layer metal 136.
  • Fig. 13B is a representational partial cross section illustrating a defect on the second layer metal of a redundant double layer metal interconnecting system. It also depicts the second layer metal 135 directly superimposed over the first layer metal 134 and a typical defect on the second layer metal 135.
  • 11 metal may be removed by selectively removing the excess metal.
  • This embodiment is configured with a double layer
  • control lines and the data lines are extended beyond the periphery of the micro array to
  • Fig. 2 is a representational partial cross section taken
  • the second metalization traces 142 are isolated from the conductive trace extensions 139, by a dielectric isolation layer 141.
  • the intermetallization connection 140 establishes the electrical connection between the conductive trace extensions 139 and the second metalization 142. Also shown are the integrated circuits in die form 143 connected to the second metalization 142.
  • Fig. 14A is a representational partial top plan view illustrating the layout principle for the dual layer interconnecting system used in this fourth embodiment of the present invention. It depicts the conductive trace extensions 139, the second metalization traces 142, the intermetallization connections 140 and the circuit connecting pads 144.
  • the first set of pads labeled A 145 is connected, via the second metalization traces 142 and the inte ⁇ netalization connection 140, to the first group of traces 146 of the conductive trace extensions 139.
  • the second set of pads labeled B 147 is connected, via the second metalization traces 142 and the intermetalization connection 140, to the second group of traces 148 of the conductive trace extensions 139.
  • This configuration is continued with additional groups of traces connected to additional sets of pads located in the area extending towards the periphery of the primary substrate.
  • This layout overcomes potential spatial constraints and provides the necessary space for all of the conductive trace extensions 139 to be connected to the appropriate circuit connecting pads 144.
  • These circuit connecting pads 144 are used to accept the connection to the integrated circuits in die fo ⁇ n as shown in Fig. 2. Such pads may also be used as probing pads to test the integrity of the transistor switches in the micro array in accordance with the special test procedures outlined below.
  • Fig. 14B shows a variation of this embodiment configured with a three layer metalization system, where the first layer is formed by the conductive trace extensions 139, the second layer is formed by the second metalization traces 142 and the third layer comprises the circuit connecting pads 144.
  • the metal traces on the second layer lie on a plane which is separated by a layer of dielectric from the plane containing the circuit connecting pads.
  • the addition of the third metalization layer removes the constraint that the traces of the second metalization must be placed around the area covered by the circuit connecting pads. Such traces can now be routed in the areas beneath the circuit connecting pads, thus providing improved utilization of the space available for interconnections and increasing the packing density of the interconnect system.
  • This configuration further allows the circuit connecting pads to be extended to encompass a circuit connection area 244 and a probing area 344 as illustrated in Fig. 14B.
  • This three layer metalization will be specifically recommended for programmable masking devices with more than 256 million pixels which will require a higher packing density for the drive and interface circuitry.
  • the operation of the active matrix micro array which is the object of the present invention, relies upon the capability of establishing the required electrical connections between the conductive trace extensions and the drive circuitry and further between the drive circuitry and an external computer system.
  • the number of conductive trace extensions does not exceed 1000, direct ribbon cable connections, similar to those used in liquid crystal displays can be successfully implemented in manufacturing.
  • the number of conductive trace extensions substantially exceeds 1000, such connections would be very difficult if not impossible to successfully implement.
  • the fourth embodiment of the present invention provides a viable solution since it eliminates the requirement for such connections.
  • Fig. 15 is a representational partial top plan view illustrating a contactiess connector system comprising a set of collimated infrared transmitters and receivers.
  • Interconnect traces 153 patterned over the primary substrate 102, establish the electrical connection between the interface circuitry and dual sets of infrared transmitters 150 and infrared receivers 151.
  • Fig. 16 is a representational partial cross section taken along the line 16-16 in Fig. 15 showing the configuration of the contactiess connector system illustrated in Fig. 15. It shows the primary substrate 102 physically separated from the connector body 152, and shows their respective infrared transmitters 150 and infrared receivers 151.
  • the infrared transmitters and receivers When the programmable masking device is installed in an exposure system, the infrared transmitters and receivers will be aligned with a matching set of receivers and transmitters mounted in the exposure system. With this configuration, there is no physical contact between the two sets of transmitters and receivers and, as a result, the programmable masking device is provided with a stress free data communications infrared link. This feature will be significant in applications, such as semiconductor microlithography, where the alignment of the programmable masking device must be held within a fraction of a micron.
  • the fifth embodiment of the present invention is described with reference to figure 17.
  • This embodiment is substantially the same as the fourth embodiment described above with the addition of special circuitry to individually control the voltage level applied to each of the pixels in the micro array as means of modulating the relative transparency of each pixel.
  • Fig. 17 is a simplified schematic diagram illustrating one of the preferred circuits used to control the voltage applied to each pixel as means of modulating its transparency. It shows a group of N data lines 115 connected to the outputs of a 1 to N analog switch 158.
  • the input of the analog switch 158 is connected to the output of a digital-to-analog (DAC) converter 157 which generates the desired analog voltage to be applied to a specific pixel from digital data stored temporarily in an N word memory 156.
  • the DATA IN ports of this memory 156 are connected to a data bus 154 providing a data communications link to the computer system which controls the programmable micro array.
  • An address bus 155 carries the required address information to the SELECT ports of both the N word memory 156 and the analog switch 158.
  • the circuit of Fig. 17 is repeated for each group of N data lines as many times as necessary to cover all the data lines in the micro array.
  • the same data bus 154 and address bus 155 provide the required data and address information to all of these circuits in accordance with the configuration shown in Fig. 17.
  • any embodiment of the present invention must further comply with the following constraint:
  • the liquid crystal material, the two substrates and the conductive coatings must offer a combined level of transparency to ultraviolet light compatible with the requirements of the specific exposure system to be used in the photolithographic processes.
  • such substrates can be made of high quality glass of the type used for semiconductor photolithography masks.
  • such substrates need to be made of quartz because glass exhibits excessive ultraviolet light absorption in this region of the spectrum.
  • the referenced conductive coatings on the substrates must be sufficiently thin in order to comply with the transparency requirements outlined above.
  • the minimum conductive coating film thickness allowable in such coatings is determined by the maximum allowable sheet resistance of the film which in turn is dependent on the pixel surface area.
  • the mathematical relationship between these parameters is such that, for proper operation, the ratio between the pixel surface area and the film thickness must not exceed a certain value determined by the electrical time constant of the electronic equivalent of a pixel element. Since the typical pixel surface area to be used in most applications of the present invention will be only 10 to 500 square microns, the conductive coating film thickness used for such applications can be adjusted to comply with the requirements for transparency to ultra violet light.
  • test and repair procedure provides means for testing the integrity of every transistor switch in the micro array. It consists of the sequence of steps which are outlined below with reference to the figures indicated in parenthesis:
  • (b) Defining the first layer metalization comprising the following: 1. The gate control lines 114 (Fig. 12) within the micro array area; 2. The conductive trace extensions 139 (Fig. 2) of the gate control lines 114 (Fig. 10) within the peripheral metal interconnect system 138 (Fig. 1); 3. The conductive trace extensions 139 (Fig. 2) of the data lines 115 (Fig. 10) within the peripheral metal interconnection system 138 (Fig. 1); 4. The gate area of the secondary control gates 127 (Fig. 10);
  • the first set comprises the
  • the second set comprises the temporary drain test lines 133
  • 21 layers consists of depositing and patterning a dielectric isolation layer
  • 26 layers consists of defining the third layer metalization comprising the
  • the alternate interconnection procedure provides means for replacing every defective transistor switch in the micro array by an alternate transistor switch which is to operate in its place. It consists of the following sequence of steps applicable to each defective transistor switch:
  • Fig. 18 which illustrates the use of this device in direct imaging photolithographic applications.
  • Figs. 19, 20, 21 and 22 which illustrate the use of such embodiments in projection systems for visual display, three dimensional imaging, holographic imaging and printing systems, respectively.
  • Fig. 18 is a pictorial representation of a photolithographic exposure apparatus illustrating the use of the programmable masking device, which is the object of the present invention, to generate images on a photosensitive target surface directly from data provided by a computer system, a technology presently described as direct imaging.
  • This programmable masking device built entirely of solid state elements, operates in conjunction with exposure systems in a manner similar to conventional non programmable masking devices.
  • the apparatus of Fig. 18 comprises a light source 159 within a light housing 160 which is equipped with a light shutter 161.
  • the light generated by the light source 159 is directed by the illumination optics 162 onto the surface of a programmable masking device 164 where it provides uniform illumination 163.
  • a computer system 165 provides the pattern generation data necessary to generate the desired transparent images on the micro array of the programmable masking device 164. These images are then transfe ⁇ ed by means of the exposure optics 166 onto the photosensitive target surface 167. Under normal operating conditions, the computer system 165 can download to the programmable masking device 164 the desired patterning data while the photosensitive target surface 167 is being aligned to the exposure optics. Upon completion of the alignment, the shutter 161 is momentarily opened for a preset exposure time. This cycle is then repeated with the next photosensitive target surface or the next site on the same photosensitive target surface.
  • a computer system will be required for the use of this programmable masking device.
  • the computer system will fully support and control such programmable masking device by downloading the required pattern generation data to the micro a ⁇ ay memory.
  • this computer will also provide controls to refresh and modify the patterns generated.
  • these devices will provide means for repairing patterning defects on wafers, programming or altering the functionality of integrated circuits, cost effectively producing custom integrated circuits and generating complete systems on a single wafer.
  • the computer system controlling the programmable masking device should be interfaced to such wafer stepper to synchronize the pattern generation with the mechanical stepping motion of the stepper.
  • micro integrated systems comprising integrated circuits, in the die fo ⁇ n, interconnected on a micro substrate.
  • micro substrate will be produced by a technology similar to that used for the generation of the peripheral interconnect system of the programmable masking devices which are the subject of the present invention.
  • the manufacture of the programmable masking devices provides another important application for their use. As outlined in the section covering the description of the present invention, the fabrication of these programmable masking devices requires the use of programmable photolithography for performing repairs and making alternate interconnections. Such programmable photolithography can be implemented with the use of another programmable masking device specifically configured for such application.
  • Fig. 19 illustrates the operation of the present invention in a visual display projection system.
  • a visual display projection system comprises a light source 159 within a light housing 160.
  • the light generated by the light source 159 is directed by the illumination optics 162 onto the surface of the programmable masking device 164 where it provides uniform illumination 163.
  • a heat shield 168 is inserted in the light path to protect the programmable masking device 164 from the heat emitted by the light source 159.
  • a video signal processing system 169 provides the digital video image generation data necessary to generate the desired transparent images on the micro a ⁇ ay of the programmable masking device 164. These images are then transfe ⁇ ed by means of the projection optics 170 onto a visual projection screen 171.
  • the video signal processing system 169 continuously downloads to the programmable masking device 164 digital video imaging data at a rate compatible with video display imaging.
  • the fifth embodiment of the present invention with the color imaging feature described previously would provide the proper features for the implementation of projection color television and multiple page computer monitor projection display systems.
  • Fig. 20 illustrates an application similar to that of Fig. 19 with the addition of a polarizer 172 for three dimensional projection viewing. All the elements described with reference to Fig. 19 have identical functions with reference to Fig. 20 and need not be repeated.
  • the polarizer 172 is used in conjunction with polarizing glasses for three dimensional viewing. Under the control and synchronized by the video signal processing system 169, the polarizer 172 alternates the polarization of the light emerging from the programmable masking device 164 between two orthogonal planes, thus providing separate images for each one of the viewer's eyes.
  • Fig. 21 illustrates the use of this invention in holographic imaging applications.
  • a laser source 173 would emit a laser beam 174 which would be dispersed by the dispersion optics 175 to provide uniform laser illumination 176 over the surface of the programmable masking device 164.
  • holographic patterns would be generated on the programmable masking device 164 which could be observed by the viewer 178. Since the patterns on the programmable masking device 164 could be continuously changed, the system described could provide means for the implementation of digitally controlled holographic television and computer monitor holographic viewing systems.
  • Color holography could be implemented, as well, by the use of a laser source combining red, green and blue beams sequentially fired in synchronism with the viewing frames for each color generated by the holographic signal processing system 177.
  • Fig. 22 illustrates still another potential application for the present invention as a printing apparatus. It presumes that the imaging data is available in digital format such as that generated directly by a computer system or otherwise generated by digitizing a real image.
  • Such apparatus would comprise a light source 159 within a light housing 160 equipped with a light shutter 161. The light generated by the light source 159 would be directed by the Elimination optics 162 onto the surface of the programmable masking device 164 where it would provide uniform illumination 163.
  • An image processing system 179 would provide the digitized imaging data necessary to generate the desired transparent images on the micro array of the programmable masking device 164.
  • Fig. 22 depicts the photosensitive reproducing device 180 in a planar configuration.
  • a cylindrical configuration such as the conventional drum of most modern office printing machines could also be used provided the projection optics would be equipped with a scanning device synchronized with the movement of such drum.
  • the electronically programmable masking device * which is the subject of the present invention, introduces a new level of flexibility in the industrial use of photolithography by providing the capability for translating computer aided design (CAD) data, directly into images produced on a photosensitive target surface.
  • CAD computer aided design
  • it opens new opportunities in the fields of high definition projection color television, multiple page computer monitor projection display systems, holographic television, holographic computer monitor systems and printing devices.
  • this electronically programmable masking device could be used in the printed circuit board industry to perform direct imaging from printed circuit layout data provided by computer systems.

Abstract

Dispositif de masquage programmable électroniquement (162) destiné à des applications photolithographiques, comprenant un microréseau actif à cristaux liquides, de pixels programmables (101), un système d'interconnexion (138) ainsi que, dans la plupart des modes de réalisation, un ensemble de circuits d'attaque et d'interface. Les pixels programmables (101) peuvent être commandés électroniquement de façon à être opaques ou transparents à la lumière d'exposition utiisée dans les systèmes d'exposition photolithographiques. La taille des pixels (124) doit être telle que lorsque l'on représente par une image le pixel (124) sur la surface cible, la taille résultante est compatible avec la résolution des formes requise sur la surface cible. L'espace entre les pixels (124), appelé intervalles entre pixels (106), doit être d'une dimension telle qu'il ne puisse pas être résolu au moyen des optiques (162, 166) du système d'exposition. Une liaison de communication permet le téléchargement direct de données de formes vers le dispositif depuis des sources externes telles que des systèmes de conception assistée par ordinateur (CAO).
PCT/US1990/007331 1989-12-22 1990-12-12 Appareil de masquage programmable WO1991010170A1 (fr)

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US45599489A 1989-12-22 1989-12-22
US455,994 1989-12-22

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WO1995022787A1 (fr) * 1994-02-21 1995-08-24 Luellau Friedrich Procede et dispositif de production photomecanique de surfaces structurees, plus particulierement pour l'exposition a la lumiere de plaques offset
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EP0632330A3 (fr) * 1993-06-21 1996-09-18 Nec Corp Procédé de formation d'un matériau photosensible et un appareil d'exposition utilisé pour le procédé.
WO1995022787A1 (fr) * 1994-02-21 1995-08-24 Luellau Friedrich Procede et dispositif de production photomecanique de surfaces structurees, plus particulierement pour l'exposition a la lumiere de plaques offset
GB2289983B (en) * 1994-06-01 1996-10-16 Simage Oy Imaging devices,systems and methods
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EP2325696A1 (fr) * 2009-11-19 2011-05-25 Amphenol-tuchel Electronics GmbH Masque à matrice pouvant être commandé électroniquement
FR2959025A1 (fr) * 2010-04-20 2011-10-21 St Microelectronics Rousset Procede et dispositif de photolithographie
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WO2023004493A1 (fr) * 2021-07-26 2023-02-02 Technologies Digitho Inc. Masque de photolithographie et système de photolithographie comprenant ledit masque de photolithographie
US11934091B1 (en) 2021-07-26 2024-03-19 Technologies Digitho Inc. Photolithography mask and photolithography system comprising said photolithography mask

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