WO1989000346A1 - Interconnexion crenelee en plastique galvanise pour composants electriques - Google Patents

Interconnexion crenelee en plastique galvanise pour composants electriques Download PDF

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Publication number
WO1989000346A1
WO1989000346A1 PCT/US1988/002210 US8802210W WO8900346A1 WO 1989000346 A1 WO1989000346 A1 WO 1989000346A1 US 8802210 W US8802210 W US 8802210W WO 8900346 A1 WO8900346 A1 WO 8900346A1
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WO
WIPO (PCT)
Prior art keywords
substrate
castellations
plated
electrical
spaced apart
Prior art date
Application number
PCT/US1988/002210
Other languages
English (en)
Inventor
Timothy P. Patterson
Carl E. Hoge
Joseph Baia
Original Assignee
Western Digital Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Digital Corporation filed Critical Western Digital Corporation
Publication of WO1989000346A1 publication Critical patent/WO1989000346A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/712—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit
    • H01R12/716—Coupling device provided on the PCB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/09181—Notches in edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates to a plated plastic castellated interconnect used as an interface for interconnecting electrical components.
  • Interconnects There are a variety of electrical interconnect techniques used for providing connections between electrical components. Interconnects vary widely in their use and function as do the variety of electrical components being connected. Electrical components can be interconnected by soldering, wire bonding. Tape Automated Bonding (TAB), or metal strips, for example. Plated ceramic interconnects also can be used for forming interconnects. These and other interconnect techniques can be used to interconnect a variety of integrated circuit (IC) components, and one example includes the techniques used for packaging of integrated circuit chips and surface mounting them on printed circuit boards (PCB's). The following background description relates to the prior art of forming electrical interconnects used in the packaging of integrated circuit chips and the mounting of IC packages on PCB's.
  • IC integrated circuit
  • a metal leadframe is used to make electrical connections between an integrated circuit and a PCB.
  • Metal leadframes are stamped or etched from a thin, flat strip of metal to form outwardly extending pin-like members or leads.
  • the metal leadframe is embedded in a molded plastic body or is otherwise affixed in a ceramic or plastic body with the leads extending out from the sides between the top and bottom surfaces of the body.
  • the leads are typically bent downward along the sides of the body to what is commonly referred to as a J-shape, or a wing shape, or straight down to what has been referred to as a butt end, for allowing the packages to be surface mounted on the PCB.
  • Surface mounting is an arrangement in which the leads are soldered to the surface of the PCB, as opposed to an arrangement in which the leads extend through plated thru- holes in the PCB before soldering.
  • the body has a castellated edge which extends downwardly around the bottom side of the body. Separate leads are bent in an S-shape around the raised castellations. This provides a spacing between the bottom of the IC package and the PCB.
  • U.S. Patent 4,012,766 to Phillips, et al. discloses a semiconductor package and a method of manufacturing of the general type which includes J-shaped leads.
  • a leadframe has disadvantages. For example, as input/outputs (I/O's) have increased in number, the spacing between leads has decreased so as to prevent the IC packages from becoming excessively large. As a result, the leadframes have been forced to become thinner. For these reasons, normal testing, shipping and handling procedures have become very difficult because of the need to avoid bending the external leads. Any bending of the metal leads can cause a lateral misalignment which can prevent the bent leads from matching up with corresponding contacts on a PCB. Bending of the leads can also cause a non-planar misalignment of the leads at the bottom of the IC package, and, as a result, some of the leads may not be connected to a corresponding contact on the PCB .
  • Another arrangement for surface mounting of IC packages comprises a printed wiring board in the form of a thin plastic base on which metalized leads are formed in a pattern.
  • the metalized leads are typically formed by laminating copper to the board with an epoxy resin and etching away to form the metalized leads. Holes are drilled in "picture frame" arrays through the thin dimension of the base, from the top to the bottom, and, subsequently, the holes are plated with metal such as copper or gold.
  • the printed metal leads on the top side of the base are then plated with gold or the like to form a pattern of printed leads which fan out from a rectangular central portion of the carrier to the plated thru-holes. Small metalized leads are also formed on the bottom side of the base below the plated thru-holes.
  • An IC chip is then mounted within a cavity in the central portion of the base, and fine conductive wires are bonded between the chip and the ends of the metal leads.
  • the top of the base is then covered with a plastic lid, or potted with epoxy resin.
  • the resulting assembly is placed on a PC board, with the bottom side of the base resting against the top face of the board. Flow soldering techniques are used to form electrical connections between each etched metal lead on the bottom side of the base and a corresponding contact on the PCB.
  • the plastic IC package with the etched metal traces is useful because there are no self-supporting metal wires or leads which can be bent, inasmuch as the etched metal leads are affixed firmly to the surface of the base and, therefore, do not move.
  • Ceramic leadless IC packages have also been used in the past for mounting integrated circuits to a PCB.
  • One prior art ceramic leadless IC package is disclosed in U.S. Patent 4,525,597 to Abe, in which circuit patterns are printed on a ceramic green sheet with a metalizing paste. An insulating layer is then placed over the metalized pattern on the top surface. The green sheet is then hot pressed to make the top surface concave and the bottom surface convex around a peripheral rim of the ceramic body. The green sheet is then fired. After firing, the ceramic is plated with a conductive metal at positions corresponding to the exposed metal circuit patterns remaining on the ceramic. The step of hot pressing the ceramic body forms a series of spaced apart depressions around the periphery in the top surface, with corresponding stand-off pads on the bottom surface of the ceramic body.
  • This ceramic IC carrier has several disadvantages. It is limited in its ability to provide fine lead pitches, because the steps involved in forming a ceramic carrier by casting in green sheets, applying a metal paste, hot pressing, firing, and subsequent metal plating techniques limit resolution. These techniques therefore are not adaptable to producing an IC carrier with the geometries necessary to produce a fine lead pitch.
  • surface mounted ceramic IC packages can be unreliable because thermal transients can develop shear forces at the solder joints and produce fatigue and resulting poor electrical connections. As lead pitches become finer, these problems with ceramic IC packages become magnified. The more reliable ceramic IC packages to date have the self-supporting metal leads which have the disadvantages of the leadframe approach described above.
  • the prior art has provided a variety of electronic interconnect techniques for a wide variety of electrical components, including the previously described techniques for surface mounting of IC packages. All of these interconnect techniques have disadvantages or limitations which are overcome by the present invention.
  • the interconnect includes a first electrical component comprising a substrate made from a molded polymeric material.
  • the molded plastic substrate has first and second surfaces substantially parallel to each other, and a plurality of separate mutually spaced apart molded projections or castellations extending from the second surface to a substantially common plane spaced from the second surface of the substrate.
  • Multiple electrically separated metal conductors are plated to the substrate.
  • the plated conductors extend continuously from the first surface, around or through the substrate, tr the common plane on corresponding castellations on the second surface of the substrate.
  • the plated castellations are adapted for connection (mechanical adhesion and electrical correction) to corresponding electrical contacts, leads, terminals, or other conductors on a second electrical component to which the first component is surface mounted.
  • the plated plastic castellations are made from polymeric materials that result in castellations which are individually compliant, at least on a microscopic Ievel.
  • the compliancy of the individual castellations allows a certain level of flexibility in the individual connections to a second component such as a PCB or other support base. This provides more effective mechanical adhesion and electrical connections than with other prior art surface mount techniques such as solder joints or surface mounted ceramic IC carriers.
  • the plated plastic castellated interconnect has other advantages when compared with the prior art of surface mounting IC packages.
  • the molded plastic substrate in combination with the plated metal conductors on the castellations allows for much finer lead pitches and resulting higher lead counts than the metal leadframe, printed wiring board, or ceramic IC carrier techniques.
  • the invention also eliminates the additional expense of using metal leadframe techniques, while providing other advantages such as allowing for thorough cleaning of fluxes and contaminants from between an IC package and a PCB.
  • the plastic substrate can be molded in a variety of geometric configurations for increasing lead pitch densities. These techniques include forming multiple rows of spaced projections along the bottom of the substrate, adjacent alternating recessed areas in multiple rows spaced apart along the edges of the substrate. These and other similar arrangements can increase substantially the lead pitch densities provided by the molded plastic module.
  • the higher lead pitch densities achieved by the plated plastic interconnect of this invention are not achievable by ceramic IC carriers, especially when compared with the complex configurations into which the module of this invention can be molded to facilitate such higher lead counts.
  • the molded plastic substrate does not undergo the same firing shrinkage problems characteristic of ceramic IC carriers during fabrication since the mold itself dictates the package dimensions and tolerances. Therefore, much higher precision is achievable for attaining fine pitches.
  • FIG. 1 is a fragmentary semi-schematic side elevation view illustrating a plated plastic castellated interconnect according to principles of this invention
  • FIG. 2 is a perspective view illustrating use of the plated plastic castellated interconnect in an integrated circuit chip (IC) carrier;
  • IC integrated circuit chip
  • FIG. 3 is a top plan view illustrating metal plated conductors on a top surface of a substrate base portion of the IC carrier;
  • FIG. 4 is a side elevation view, partly in cross- section, taken along line 4-4 of FIG. 2;
  • FIG. 5 is a bottom plan view taken on line 5-5 of FIG. 4;
  • FIG. 6 is a semi-schematic partly cross-sectional view illustrating use of the plated plastic castellated interconnect in an alternative technique for mounting an integrated circuit chip to the IC carrier;
  • FIG. 7 is a top plan view illustrating a molded sub- strate base portion of an IC carrier during a preliminary step in a process for manufacturing the IC carrier;
  • FIG. 8 is a bottom plan view of the opposite side of the substrate shown in FIG. 7;
  • FIG. 9 is an enlarged fragmentary side elevation view illustrating a portion of the IC carrier mounted to a printed circuit board
  • FIG. 10 is a fragmentary top plan view illustrating an alternative embodiment of the invention in which lead pitch density of an IC carrier is increased;
  • FIG. 11 is a fragmentary top plan view illustrating a portion of the alternative IC carrier shown in FIG. 10;
  • FIG. 12 is a fragmentary perspective view illustrating a bottom portion of the alternative IC carrier
  • FIG. 13 is a fragmentary top plan view illustrating use of the plated plastic castellated interconnect in an alternative IC carrier with plated thru-holes in contact with castellations on the bottom of the carrier
  • FIG. 14 is a cross-sectional view of the embodiment of FIG. 13;
  • FIG. 15 is a fragmentary cross-sectional view illustrating use of the plated plastic castellated interconnect for the surface connection of an electrical socket to a PCB according to principles of this invention
  • FIG. 16 is a fragmentary cross-sectional view illustrating an alternate embodiment of a plated plastic castellated interconnect in which an electrical socket is mounted to a PCB; and
  • FIG. 17 is a fragmentary cross-sectional view illustrating a further use of the invention for surface mounting a pin grid to a PCB.
  • FIG. 1 illustrates general principles of the invention in which the interconnect forms an interface between a first electrical component 2 and a flat upper surface 3 of a second electrical component 4 to which the first component 2 is surface mounted.
  • the first electrical component 2 can be any of a variety of electrical components; and in the illustrated embodiment, the first electrical component 2 comprises a structure or substrate 5 made from a molded polymeric material.
  • the substrate has first and second surfaces 6 and 7 respectively, extending substantially parallel to each other.
  • a plurality of separate mutually spaced apart molded plastic projections or castellations 8 project downward from the second surface toward, the flat upper surface 3 of the second electrical component 4.
  • the remote ends of the castellations are preferably in a substantially common plane spaced from and parallel to the second surface of the substrate.
  • Multiple electrically isolated metal surfaces 9 are plated to the substrate.
  • Each plated metal conductor extends continuously from the first surface of the substrate, around a side edge 10 of the substrate, to a common plane on a corresponding one of the castellations on the second surface of the substrate.
  • the plated conductive surfaces could extend from the first surface of the substrate through a thru- hole or via hole (not shown) in the substrate, to the bottoms of the castellations.
  • the non-conductive unplated spaces 11 left on the side edge of the plastic substrate between the plated edge surfaces electrically isolate the row of individually plated metal surfaces.
  • FIG. 1 illustrates one example of a means for electrically interconnecting the first electrical component to the second component.
  • the castellations on the first component can be connected to separate electrical terminals, contacts, leads, lands, or other electrical conductors on the second component. These connections may be made by separate solder joints 13 (shown in dotted lines in FIG. 1), electrically conductive resins, or the like.
  • the substrate is preferably made from a polymeric material capable of being molded into the castellated configuration such as by injection molding techniques.
  • a presently preferred polymeric material is polyetherimide, although other polymeric materials can be used.
  • Injection molding techniques are desirable because they can be adapted to providing individually narrow and closely spaced castellations to provide controlled fine pitch densities along the rows of plated plastic castellations.
  • the molded plastic material also produces individual castellations which are compliant, on a microscopic level, in the sense that the individual castellations are able to flex or move relative to one another during use.
  • the substrate is made from a thermoplastic material which enhances compliancy, although certain thermoset materials also are suitable.
  • the plastic castellated arrangement makes the resulting interconnect between the first electrical component and the second component compliant in three directions. That is, the castellations are able to flex or move (on a microscopic level) vertically, laterally (parallel to the row of castellations) and inwardly or outwardly at each surface connection.
  • the surface connections are therefore elastic and, as a result, they are able to compensate for thermal expansion during use.
  • the castellations on the substrate and the second component itself can both be made from a plastic material having the same thermal expansion properties, which voids thermal stresses in the solder joints during use.
  • FIGS. 2 through 5 illustrate one embodiment of the plated plastic castellated interconnect used for mounting an integrated circuit (IC) chip to a printed circuit board (PCB).
  • FIG. 2 is a perspective view illustrating basic components of an IC carrier 20 which includes a thin, generally parallelepiped shaped molded plastic base or substrate 22 and a molded plastic lid 24 mounted to the substrate.
  • the carrier encases an IC chip 26 mounted within a housing formed by the molded substrate 22 and lid 24.
  • the carrier plated plastic castellated interconnect surface mounts the IC carrier to a PCB as described below.
  • FIGS. 3 through 5 illustrate the detailed construction of one embodiment of the molded plastic substrate 22.
  • the IC chip 26 can optionally be mounted in a cavity in the center of the substrate 22 and then elec- trically connected to conductive elements on the substrate; or the IC chip can be mounted in a cavity in the underside of the lid and hen connected to conductive elements on the adjoining substrate base.
  • the combination integrated circuit mounting and packaging assembly is referred to as a "cavity-up" configuration, and in latter instance the assembly is referred to as a "cavity-down" configuration.
  • the embodiment illustrated in FIGS. 3 through 5 comprises a cavity-up configuration of the molded plastic substrate 22; a cavity-down configuration is illustrated in FIG. 6. Both configurations are considered within the scope of this invention.
  • the molded plastic substrate has a small generally rectangular-shaped cavity 28 extending downwardly into a central region of a flat upper surface 30 of the substrate.
  • the integrated circuit chip 26 has a rectangular configuration that matches the shape of the cavity, and the chip is mounted within the cavity as shown in FIG. 3.
  • the substrate also has separate rows of individual castellations 32 mutually spaced apart from one another and extending downwardly from a flat undersurface 34 of the substrate.
  • the rows of castellations 32 extend downwardly along the perimeter portion of the flat undersurface of the substrate.
  • the castellations are uniformly spaced apart along each edge of the rectangular-shaped substrate, and the castellations in each row are aligned on a common axis.
  • the projections also are of uniform size and shape and all extend from the bottom face of the substrate to a common plane 36 shown in FIG. 4. This arrangement forms uniformly spaced gaps 38 between adjacent castellations around the rectangular perimeter of the substrate.
  • each castellation 32 is each located immediately inboard from each corresponding recess 40 so that the surface of each recess continues uninterrupted around the outer surface of each corresponding castellation located behind and below it.
  • the maximum width of each castellation thus matches the maximum width of each recess (as shown in FIG. 4).
  • Each castellation also has downwardly tapered side walls 42 best shown in FIG. 4.
  • the bottom surface 44 of each castellation 32 is rounded, preferably in a semicircular configuration as shown best in the side view portion of
  • FIG. 3 As mentioned previously, the rounded bottom portions of the castellations lie in the common plane 36.
  • the individual recesses 40 spaced apart along each outer edge of the substrate are separated by corresponding castellations 45 intervening in the spaces between adjacent recesses.
  • a plurality of separate metal conductors 46 are plated on the flat top surface of the substrate.
  • the conductors are arranged in four groups which fan outwardly from the vicinity of each of the four sides of the rectangular cavity 28 toward corresponding outer edges of the rectangular substrate.
  • Each metal conductor plated to the substrate extends to a corresponding recess 40 formed in the outer edge of the substrate.
  • the carrier has 84 conductors, 21 per side.
  • the metal conductors are plated to the substrate so that they are directly bonded to its surface.
  • the conductors are preferably applied to the surface by a combination of electroless plating and electroplating techniques described below. These techniques plate the molded plastic substrate with one or more layers of essentially pure deposited metal while the resulting metal layer is being bonded directly to the substrate.
  • a combination of copper, nickel and gold is preferably used to form the plated metal conductors, although other metals capable of being plated to the surface of the molded plastic substrate can be used.
  • the plated conductors are applied in thin layers and therefore are referred to herein as conductive metal circuit traces.
  • the circuit traces 46 extend continuously from the top surface of the substrate, around the upright faces of the recesses 40, and then around the rounded bottom surfaces 44 of the castellations 32.
  • the bottom surfaces of the castellations, at least in the plane 36 are plated with the electrically conductive metal traces .
  • each conductive trace on the substrate forms a continuous electrical lead from the substrate top surface, around the edge of the substrate, to the bottom portion of a corresponding castellation 32 on the bottom of the substrate.
  • the circuit traces which are plated to the upright semicircular faces of the recesses 40 are elec- trically insulated from one another by the corresponding castellations 45 that separate the recesses along the outer edges of the substrate.
  • the electrically conductive traces on the curved bottom portions of the castellations 32 are electrically insulated from one another by the space gaps 38 that separate the individual castellations along the substrate bottom surface.
  • the integrated circuit carrier can be surface mounted on a PCB having its top surface in the plane 36 shown in FIG. 4. This leaves the space gaps 38 between the bottom surface 34 of the substrate and the top of the printed circuit board, as well as the open gaps between conductive surfaces on adjacent bottom castellations 32. Further details relating to mounting of the integrated circuit carrier to a printed circuit board are described below.
  • the integrated circuit carrier also includes means for mounting the integrated circuit chip 26 within the housing formed by the carrier.
  • the conductive metal traces 46 are electrically connected to the integrated circuit chip 26 by corresponding fine wire leads 50.
  • These fine wire leads are metallurgically bonded between individual spaced bonding pads 52 on the integrated circuit and corresponding bonding points 54 on the individual conductive metal traces 46.
  • the fine wire leads from the integrated circuit are separately connected to certain of the metal traces and need not be connected to all of the conductive metal traces.
  • the connections between the integrated circuit and the conductive metal traces illustrated at FIG. 3 are simply an example showing connection between the integrated circuit and any desired number of the electrically conductive traces.
  • a separate electrical circuit is formed between each lead from the integrated circuit chip across the integrated circuit carrier surface and to the bottom surface of the carrier to a separate one of the bottom castellations 32 which, in turn, are bonded to corresponding contacts on the printed circuit board.
  • FIGS. 3 through 5 illustrate the cavity-up configuration in which the integrated circuit chip is mounted to the substrate and connected directly to corresponding electrically conductive traces on the substrate.
  • an integrated circuit chip 56 can be mounted in the cavity-down configuration.
  • the integrated circuit chip 56 is affixed to a spreader 57 carried on a package 58.
  • the spreader has a downwardly facing surface 60 having metal traces (not shown) fanning outwardly from the integrated circuit chip in a manner similar to the top surface 30 of the substrate 32.
  • the molded plastic substrate 62 includes a large central cavity 64 to provide space for the downwardly projecting integrated circuit chip 56.
  • Separate fine wire leads 66 electrically connect wire bonding pads on the integrated circuit to corresponding conductive metal traces on the spreader 57.
  • the electrically conductive traces on the spreader are soldered, cemented, or otherwise electrically connected to corresponding electrically conductive traces on the top side 68 of the substrate 62. Electrical contact is achieved between the spreader and the substrace by means of the adhesive, solder or cement which form discrete, electrically isolated lands between the two surfaces.
  • the molded plastic substrate 62 includes the spaced apart castellations 70 extending along the outer periphery of the bottom surface of the substrate. Corresponding spaced apart recessed regions (not shown in FIG. 6) extend along the outer side walls 72 of the substrate, in vertical alignment with the bottom castellations. As with the embodiment illustrated in FIGS. 3 through 5, the upright faces of the recesses and the bottom castellations 70 are plated with the electrically conductive metal circuit traces to provide individual continuous electrically conductive paths from the bottoms of the castellations 70 to the fine wire leads 66 of the integrated circuit 56.
  • FIGS. 7 and 8 illustrate one embodiment of a method for making the substrate base portion of the integrated circuit carrier.
  • the substrate is preferably made by injection molding techniques in order to first form a molded plastic base 80 of thin, parallelepiped shape.
  • the molded plastic base has a flat top surface 82 with a shallow rectangular shaped recess 84 in its center.
  • Four rows of holes 86 extend through the depth of the base 80. The rows of holes are uniformly spaced outwardly from the four sides of the central recess. The four rows of holes are also uniformly spaced inwardly from the four outer edges 88 of the base.
  • the upper surface 82 of the base 80 also includes three shallow recesses 90 which register with three corresponding alignment pins on the underside of the lid when the lid 24 is mounted to the integrated circuit carrier.
  • the molded plastic base 80 further includes four rows of spaced apart castellations 92 extending from a flat bottom face 94 of the base 80.
  • the rows of molded bottom castellations 92 are immediately inboard from the holes 86, and the configuration of the castellations 92 and their positioning with respect to the holes is identical to the castellations 32 on the substrate illustrated in FIGS. 3 through 5.
  • the bottom face of the base 80 also includes a peripheral surface 96 which is raised slightly from the shallow recessed face 94 on which the castellations are formed. This raised outer peripheral surface 96 provides a flat surface in the same plane as the bottoms of the castellations 92.
  • the molded plastic base 80 shown in FIGS. 7 and 8 can be made from a variety of plastic materials capable of forming the base by injection molding techniques. Injection molding techniques are preferred because the entire topography of the base 80 shown in FIGS. 7 and 8 can be injection molded as a single integral unit, with retractable pins (not shown) used in the mold for forming the rows of spaced apart holes 86. Injection molding techniques also result in producing a desired configuration of the bottom castellations 92. The castellations also can be molded so they are individually narrow and closely spaced to provide a fine pitch density of castellations along the rows of corresponding holes. The injection molded plastic material also results in the individual castellations being compliant, on a microscopic level, as described previously.
  • the surfaces of the base are activated by a suitable sizing material to enhance bonding of the electrically conductive metal plating to the base 80.
  • a conductive metal such as copper is first plated onto all surfaces of the base.
  • a continuous film of electroless copper is first plated on the base, preferably in a film thickness of about ten micro-inches. The copper is then patterned using lithographic techniques and etched followed by depositing a one mil thick film of electrolytic copper.
  • electroless plating comprises applying a coating of metal from an electrolytic solution of a salt containing ions of the metal being deposited.
  • the coating is deposited without applying electrical current but by chemical reduction.
  • Electroplating comprises applying the coating of metal by passing an electric current through an electrolytic solution of a salt containing ions of the metal being deposited.
  • Metal sputtering techniques also can be used and these include applying the coating in a vacuum tube having metal ions emanating from a cathode and deposited as a film on the object contained within the tube. Three phases of this technique comprise generating a metal vapor, diffusion of the vapor, and condensation.
  • Vacuum metalizing techniques also can be used and these include applying a coating of metal by evaporating the metal under high vacuum and condensing it on the surface of the base material.
  • Applicable electroplating, electroless plating, and sputtering techniques are described in MODERN PLASTICS ENCYCLOPEDIA, 1986-1987, pp. 370-371; and 1984-1985, pp. 372-374.
  • Applicable vacuum metalizing techniques are described in MODERN PLASTICS ENCYCLOPEDIA, 1986-1987, pp. 381-382.
  • Plastics injection molding techniques are described in MODERN PLASTICS ENCYCLOPEDIA, 1983-1984, pp. 248-271; and 1984-85, pp. 258-281. These disclosures are incorporated herein by this reference.
  • plating techniques for forming a thin metal film on the substrate are referred to herein as "plating” techniques in the sense that they deposit on the base a thin film or layer, or multiple layers, of essentially pure metal which is bonded directly to the surface of the base.
  • the metal layer which is plated to the base is continuous and covers the top and bottom surfaces, the side edges, and the entire upright face of the holes 86 in the base.
  • the plated metal film is applied in a thin film thickness which allows etching away to effectively form the electrically separated metal circuit traces.
  • the plating techniques allow etching away to form conductive traces which are individually narrow and closely spaced apart in a high pitch density. Conductive traces with a width as low as about six mils and an on-center spacing as low as about ten mils can be formed by such plating and etching techniques .
  • the base is severed along straight lines extending through the centers of each row of the holes 86.
  • One of the lines along which the base is severed is shown at 98 in FIG. 7. This produces the rectangularly-shaped (square) substrate shown in FIGS. 3 through 5 in which the metal plated semi-circular recessed regions are spaced apart along each side edge of the substrate.
  • injection molding techniques can be used to produce integrally molded plastic interconnect modules with any desired topography, including geometries that can provide a fine pitch density of the conductive metal traces.
  • the combination of injection molding in a desired configuration, with metal plating and subsequent removal of the metal in the desired areas, allows the fine pitch density to be provided effectively from the top surface, through the recessed portions of the substrate, to the castellations on the bottom of the module.
  • the result is a leaded castellated interconnect module without the disadvantages resulting from use of a separate metal leadframe.
  • These techniques also are advantageous in providing an IC carrier with castellations in a desired pattern to match the footprint pattern of the contacts on the PCB to which the carrier may be mounted.
  • the IC chip 26 is mounted to the recess in the carrier, and the chip is wire bonded to the conductive metal traces.
  • the plastic lid 24 is then placed on the carrier and bonded to it with a resin such as an epoxy resin.
  • the lid-glue combination encapsulates the IC chip.
  • FIG. 9 schematically illustrates surface mounting of the IC carrier to a PCB.
  • the castellations 32 at the base of the substrate 22 project downwardly from the bottom. surface 34 of the substrate for electrical connection to corresponding electrical contacts 99 on a top surface 100 of a printed circuit board 102.
  • the bottoms of the castellations are electrically connected to the contacts on the board by separate solder joints 104 or electrically conductive resins which are electrically separated from one another.
  • FIG. 9 illustrates that each plated electrical conductor is electrically separated from the adjacent conductor and, due to its placement on the cor- responding castellation, it is spaced away from the bottom side of the base.
  • the carrier including the base
  • the carrier can be mounted to the PCB and soldered or glued to the contacts 99 on the board, while leaving the gap 106 between the bottom of the base and the top of the board. This gap allows cleaning under the base and makes it easier to avoid electrical shorts between the plated electrical leads.
  • the surface-mounted integrated circuit carrier illustrated in FIG. 9 depicts dimensions of a typical castellated plastic interconnect module that can be produced according to principles of this invention.
  • the projecting contacts 32 are spaced apart by an on-center dimension a of 0.025 inch.
  • the lateral distance b between adjacent castellations is 0.010 inch.
  • the lateral spacing c between adjacent soldered joints 104 is about 0.007 inch.
  • the width d of each castellation is about 0.015 inch.
  • the spacing e between the bottom surface of the integrated circuit carrier 22 and the top surface of the printed circuit board is about 0.020 inch.
  • the IC carrier of this invention can be produced with its metal leads in a fine pitch density in the sense that conductors 46 can be spaced apart by an on-center spacing of about 25 mils or less, with a spacing between conductors of about ten mils or less.
  • FIGS. 10 through 12 illustrate an alternative embodiment in which the carrier can be molded with a more intricate configuration in order to increase lead densities.
  • FIGS. 10 through 12 there are two rows of alternating, recessed conductive surfaces extending along each side edge of an IC carrier substrate 110.
  • the recessed conductive surfaces face outwardly along each edge and alternate from one row to the next so as to form spaced apart castellation: 11 2 extending laterally outwardly from each edge of the substrate.
  • the outer faces of these castellations are preferably recessed and are aligned in a common plane to form a first outer row of spaced apart conductive surfaces.
  • the gaps 114 left between the adjacent castellations also have recessed conductive surfaces to form a second inner row of spaced apart conductive surfaces.
  • Plated conductive metal traces (schematically illustrated at 116 in FIG. 10) fan outwardly in a pattern from the vicinity of a central cavity 118 on the top surface of the substrate toward the first and second rows of alternating recessed faces along each edge of the substrate. Only a portion of the fan shaped pattern of plated conductors is shown in FIG . 10 for simplicity.
  • FIGS. 11 and 12 illustrate castellations on a bottom surface of the substrate shown in FIG. 10.
  • alternating castellations 120 project downwardly from the underside of the first row of castellations 112, and a second row of castellations 122 project downwardly from the second row of conductive surfaces 114.
  • two parallel rows of alternating castellations are formed along the bottom periphery of the integrated circuit carrier, and all castellations extend to a common plane.
  • the electrically conductive traces 116 are plated on the lower portions of the first and second rows of alternating castellations, and the plating on each of the castellations is electrically separated from the plating on the other castellations.
  • the rear edges of the castellations can either be concave as shown in FIG.
  • FIGS. 10 through 12 provide a means for increasing the lead pitch density of the integrated circuit carrier inasmuch as additional conductive traces are plated in spaces normally occupied by wider electrically insulative surfaces separating a single row of castellations.
  • FIGS. 13 and 14 schematically illustrate a further embodiment of the invention in which the plated plastic castellated interconnect is formed by plated thru-holes or via holes 124 in a plastic substrate 126.
  • the thru-holes are arranged in any desired pattern around the outer periphery of the substrate.
  • the plated thru-holes alternate between two parallel rows inboard from each edge of the substrate.
  • Bottom castellations in the form of separate spaced apart integrally molded pads 128 are formed at the base of each of the plated thru-holes.
  • the thru-holes open through a rounded bottom portion of each molded pad.
  • the pads hold the substrate 126 spaced above the top surface of a second component such as a printed circuit board 130.
  • the pads 128 are bonded to contacts on the board.
  • Separate plated conductive metal traces 132 on the upper surface of the substrate form continuous electrical conductors spaced apart from one another and extending through corresponding plated thru-holes to the bottoms of the stand-off pads.
  • the bottom surfaces of the pads 128 can be plated, the separate solder joints 132 at the bottom of each plated thru-hole provide an electrical connection between the interior of each plated thru-hole and the corresponding contact on the board.
  • FIGS. 15 through 17 illustrate further embodiments of the invention.
  • the plated plastic castellated interconnect can provide surface connections of other electrical components to a support base such as a PCB or a housing, for example.
  • FIG. 15 illustrates use of the invention as an interface for an electrical socket 134 surface mounted to a PCB 136.
  • the socket is made from a molded plastic material and forms an upwardly facing cavity having a flat base 137 and a peripheral side wall 138. Rows of plastic castellations 140, similar to those described in the previous embodiments , project downwardly from the underside of the socket.
  • a separate integrally molded plastic spring 142 (in the form of an inwardly projecting leaf spring type contact) is biased into spring contact with an IC package 144 carrying an IC chip 146.
  • Spaced apart plated metal circuit traces 148 on the package 144 make contact with corresponding continuous plated metal circuit traces 150 extending from the bottoms of the castellations 140 to the exterior of the spring contact 142.
  • FIG. 16 illustrates an alternative form of a surface mounted castallated plastic interconnect socket 152.
  • This socket has rows of integrally molded plastic castellations 154 surface mounted to a PCB 156.
  • the socket also includes and upwardly facing cavity 158 for receiving an IC package 160 carrying an IC chip 162.
  • separate metal springs 162 are connected by pins 164 to plated thru-holes 166 in corresponding castellations 154.
  • the springs include inwardly projecting contacts 168 for making a spring-biased electrical contact with corresponding plated metal circuit traces 170 on the IC package 160.
  • the plated thru-holes 166 provide electrical contact from the solder joints at the bottoms of the castellations, through the plated thru- holes, to the pins 164 and to spring contacts 168, to the electrical circuit traces 170 on the IC package.
  • FIG. 17 shows a further alternate embodiment of the plated plastic castellated interconnect in the form of a carrier 172 for a pin grid 174.
  • the carrier 172 has integrally molded castellations 176 with plated metal circuit traces 178 electrically connected to a PCB 180.
  • the pin grid 174 includes a plurality of downwardly facing pins 182 extending into corresponding plated thru-holes 184 in the castellations. Electrical connections from an IC chip 186 on the carrier 174 are made through the corresponding pins 182 to the surface mount connections of the castellations to the contacts on the PCB.
  • the plated plastic castellated interconnect of this invention provides for fine lead pitches and resulting higher lead counts than other prior art IC carriers such as those using the metal leadframe, printed wiring board, and ceramic IC carrier techniques.
  • the invention also eliminates the additional expense of using metal leadframe techniques or the additional manufacturing costs and problems associated with ceramic IC carriers.
  • the polymeric substrate can be molded in various geometries which can increase lead pitch densities, including the multiple rows- of spaced apart castellations at the bottom of the molded substrate.
  • the molded plastic castellations also can be formed in a geometry and made from a substance which can allow for a certain level of compliancy in surface mount connections while ensuring good contact to a PCB to enhance reliability of the electrical connections.
  • the module maintains alignment and planarity through standard IC testing, shipping and handling. The module also allows for thorough cleaning of fluxes and contaminants between the bottom of the module and the PCB in order to provide reliable connections without electrical failures of the assembled PCB.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Interconnexion (20) crénelée en plastique galvanisé, comprenant un substrat (22) réalisé à partir d'une matière polymère moulée, dont les surfaces supérieure et inférieure (30, 34) comportent une pluralité de crénelures (32) moulées d'une pièce dans le substrat (22), et faisant saillie à partir de la surface (34) du substrat (22). On peut mouler une pluralité de régions cannelées séparées et espacées dans un bord du substrat (22), et alignées avec les crénelures (32). Une pluralité de conducteurs (46) métalliques sont métallisés par électrolyse sur le substrat (22) sous forme de tracés (48) de circuits conducteurs séparés, de sorte que chaque tracé (48) de circuit s'étende de manière continue à partir de la surface supérieure (30) le long de la surface d'une cannelure (40) correspondante, et jusqu'à un plan commun situé sur une crénelure (32) respective, au bas (34) du substrat (22). Les crénelures métalliques galvanisées sont agencées pour permettre une soudure ou un collage aux contacts (99) situés sur une carte de circuits imprimés (102), afin d'établir une connexion électrique avec un composant électrique tel qu'une puce (26) de CI, reliée aux tracés (48) de circuits situés sur le substrat (22). Les crénelures en plastique galvanisé situées sur un composant permettent des densités de fils élevés, des configurations complexes, et la conformation de connexions électriques à un second composant électrique, ainsi que d'autres avantages.
PCT/US1988/002210 1987-07-01 1988-06-28 Interconnexion crenelee en plastique galvanise pour composants electriques WO1989000346A1 (fr)

Applications Claiming Priority (4)

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US159,692 1980-06-16
US6942587A 1987-07-01 1987-07-01
US069,425 1987-07-01
US15969288A 1988-02-24 1988-02-24

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GB2248345A (en) * 1990-09-27 1992-04-01 Stc Plc Edge soldering of electronic components
WO1997015078A1 (fr) * 1995-10-16 1997-04-24 Siemens N.V. Ensemble grille a bossage polymere
WO1997015077A1 (fr) * 1995-10-16 1997-04-24 Siemens N.V. Boitier de matrice a bossage polymere pour circuits a micro-ondes
US5929516A (en) * 1994-09-23 1999-07-27 Siemens N.V. Polymer stud grid array
DE10059178A1 (de) * 2000-11-29 2002-06-13 Siemens Production & Logistics Verfahren zur Herstellung von Halbleitermodulen sowie nach dem Verfahren hergestelltes Modul
DE10048489C1 (de) * 2000-09-29 2002-08-08 Siemens Ag Polymer Stud Grid Array und Verfahren zur Herstellung eines derartigen Polymer Stud Grid Arrays
DE10059176C2 (de) * 2000-11-29 2002-10-24 Siemens Ag Zwischenträger für ein Halbleitermodul, unter Verwendung eines derartigen Zwischenträgers hergestelltes Halbleitermodul sowie Verfahren zur Herstellung eines derartigen Halbleitermoduls
US6485999B1 (en) 1998-07-10 2002-11-26 Siemens Aktiengesellschaft Wiring arrangements having electrically conductive cross connections and method for producing same
US6870251B2 (en) * 2002-05-29 2005-03-22 Intel Corporation High-power LGA socket
DE102013100197A1 (de) * 2013-01-10 2014-07-10 Continental Automotive Gmbh Sensoreinheit für ein Kraftfahrzeug zur Montage auf einer Leiterplatte und Mitteln zum Dämpfen der Übertragung hochfrequenter Störungen
US11404805B2 (en) 2018-04-19 2022-08-02 The Research Foundation For The State University Of New York Solderless circuit connector
CN115015100A (zh) * 2022-06-06 2022-09-06 上海大学 一种适用于电镀层检测的丝束电极工艺及其制备方法

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GB8812330D0 (en) * 1988-05-25 1988-06-29 Thomas & Betts Corp Connector for printed circuit boards

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Publication number Priority date Publication date Assignee Title
GB2248345A (en) * 1990-09-27 1992-04-01 Stc Plc Edge soldering of electronic components
GB2248345B (en) * 1990-09-27 1994-06-22 Stc Plc Edge soldering of electronic components
US5929516A (en) * 1994-09-23 1999-07-27 Siemens N.V. Polymer stud grid array
EP0782765B1 (fr) * 1994-09-23 2000-06-28 Siemens N.V. Emballage de matrice a projections en polymeres
WO1997015078A1 (fr) * 1995-10-16 1997-04-24 Siemens N.V. Ensemble grille a bossage polymere
WO1997015077A1 (fr) * 1995-10-16 1997-04-24 Siemens N.V. Boitier de matrice a bossage polymere pour circuits a micro-ondes
US6122172A (en) * 1995-10-16 2000-09-19 Siemens Nv Polymer stud grid array
US6130478A (en) * 1995-10-16 2000-10-10 Siemens N.V. Polymer stud grid array for microwave circuit arrangements
US6485999B1 (en) 1998-07-10 2002-11-26 Siemens Aktiengesellschaft Wiring arrangements having electrically conductive cross connections and method for producing same
DE10048489C1 (de) * 2000-09-29 2002-08-08 Siemens Ag Polymer Stud Grid Array und Verfahren zur Herstellung eines derartigen Polymer Stud Grid Arrays
DE10059176C2 (de) * 2000-11-29 2002-10-24 Siemens Ag Zwischenträger für ein Halbleitermodul, unter Verwendung eines derartigen Zwischenträgers hergestelltes Halbleitermodul sowie Verfahren zur Herstellung eines derartigen Halbleitermoduls
DE10059178C2 (de) * 2000-11-29 2002-11-07 Siemens Production & Logistics Verfahren zur Herstellung von Halbleitermodulen sowie nach dem Verfahren hergestelltes Modul
DE10059178A1 (de) * 2000-11-29 2002-06-13 Siemens Production & Logistics Verfahren zur Herstellung von Halbleitermodulen sowie nach dem Verfahren hergestelltes Modul
US6781215B2 (en) 2000-11-29 2004-08-24 Siemens Aktiengesellschaft Intermediate base for a semiconductor module and a semiconductor module using the intermediate base
US6870251B2 (en) * 2002-05-29 2005-03-22 Intel Corporation High-power LGA socket
US7402182B2 (en) 2002-05-29 2008-07-22 Intel Corporation High-power LGA socket
DE102013100197A1 (de) * 2013-01-10 2014-07-10 Continental Automotive Gmbh Sensoreinheit für ein Kraftfahrzeug zur Montage auf einer Leiterplatte und Mitteln zum Dämpfen der Übertragung hochfrequenter Störungen
US11404805B2 (en) 2018-04-19 2022-08-02 The Research Foundation For The State University Of New York Solderless circuit connector
CN115015100A (zh) * 2022-06-06 2022-09-06 上海大学 一种适用于电镀层检测的丝束电极工艺及其制备方法

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CA1293544C (fr) 1991-12-24
AU2073088A (en) 1989-01-30

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