WO1981000928A1 - Circuit echantillonneur-bloqueur avec annulation du decalage - Google Patents

Circuit echantillonneur-bloqueur avec annulation du decalage Download PDF

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Publication number
WO1981000928A1
WO1981000928A1 PCT/US1980/001130 US8001130W WO8100928A1 WO 1981000928 A1 WO1981000928 A1 WO 1981000928A1 US 8001130 W US8001130 W US 8001130W WO 8100928 A1 WO8100928 A1 WO 8100928A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
capacitor
lead
sample
operational amplifier
Prior art date
Application number
PCT/US1980/001130
Other languages
English (en)
Inventor
Y Haque
R Mao
Original Assignee
American Micro Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Micro Syst filed Critical American Micro Syst
Priority to DE19803049671 priority Critical patent/DE3049671A1/de
Publication of WO1981000928A1 publication Critical patent/WO1981000928A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier

Definitions

  • This invention relates to operational amplifiers, and more particularly, to an improved operational amplifier voltage driven sample and hold circuit that can be imple ⁇ mented as an integrated monolithic circuit with no external components.
  • Sample and hold type operational amplifier circuits are used in data acquisition and data conversion (digital to analog or analog to digital conversion) systems where there is a need to sample a signal voltage and hold that voltage for a certain period of time.
  • a problem which arose with such circuits concerned the inherent offset voltage of the conventional sample and hold circuit and the variation of that offset voltage with temperature. Offset voltage may be defined as the value of the output voltage when sampling zero input voltage at a stated ! temperature.
  • Another object of the present invention is to provide an operational amplifier sample and hold circuit that:
  • Another object of the present invention is to provide an operational amplifier sample and hold circuit that is made to work with zero common mode input voltage, thereby simplifying its design requirements.
  • Yet another object of the present invention is to provide an operational amplifier sample and hold circuit that is particularly adaptable for implementation as an
  • the present invention provides an opera ⁇ tional amplifier sample and hold circuit that is comprised of an amplifier having a bias section, a constant current source for a differential amplifier section and an output stage, all connected between common power leads supplying V DD and V ss power levels.
  • the input lead to the negative terminal of the opera ⁇ tional amplifier is first connected through a first tran-
  • O sistor whose gate is connected to a "sample” clock source. Connected between this switching transistor and the negative input terminal is a capacitor. A feedback lead from the output of the operational amplifier is connected in parallel to second and third transistors. This second transistor is connected to the input lead between the capacitor and the negative input terminal for the operational amplifier, and its gate is also connected to the "sample” clock source. The third transistor is connected to the input lead between the first transistor and the capacitor and its gate is connected to the "hold” clock source. When the "sample” clock is supplied to turn on the first and second transistors, the offset voltage through the output feedback of the operational amplifier is stored on the node between the capacitor and its negative input terminal.
  • the input signal Vin is present on the outer node between the capacitor and the first transistor.
  • the hold signal is applied to the gate of the third transistor and at the outer node the output voltage is forced to the value of Vin.
  • Vin is sampled and held and the operational amplifier's offset has been cancelled.
  • the offset caused by switch feed through i.e., when the second transistor goes off
  • Such an amplifier forced to work with zero common mode voltage, provides important advantages when implemented as an MOS integrated operational amplifier by easing the design requirements on the operational amplifier.
  • the first, second and third transistors can be replaced with complementary devices, i.e., each transistor being replaced by a P-channel and an N-channel transistor tied in parallel to each other. This provides the device with a large signal handling capability because the comple ⁇ mentary devices are capable of handling bipolar signals.
  • Fig. 1 is a schematic block diagram of an operational amplifier based sample and hold device according to the present invention
  • Fig. 2 is a voltage- iming diagram showing wave forms for the three control transistors for the circuit of Fig. 1A;
  • Fig. 3 is a detailed circuit diagram for the device of Fig. 1.
  • Fig. 1 shows an opera ⁇ tional amplifier based sample and hold circuit 10 embody ⁇ ing principles of the present invention.
  • it comprises an operational amplifier 11 having a positive input terminal connected by a lead 12 to ground potential, a negative input terminal connected to a lead 14 and an output lead 16.
  • An input lead 15 providing a signal voltage from a voltage driven signal source Vin is con ⁇ nected to the source of a first transistor 18 whose drain is connected to one side of a capacitor 20. The other side of this capacitor is connected to the negative input terminal of the operational amplifier.
  • a feedback lead 22 extends from the output lead 16 and is connected to the drain terminal of a second tran ⁇ sistor 24 and also to the drain terminal of a third tran ⁇ sistor 26 in parallel.
  • the other source terminal of the transistor 24 is connected to a node 28 in the lead 14, ' between the capacitor and the negative input terminal, and the source terminal of the third transistor 26 is con ⁇ nected to a node 30 between the first transistor and the capacitor.
  • a voltage V 2 , supplied to the third transistor 26, turns on when ⁇ 7. is turned off and this connects the output to node 30, thereby forcing the output voltage to the value of Vin at node 30 (before V., went off).
  • Vin is sampled and held and the operational amplifier's offset has been cancelled.
  • Some residual offset does remain, due to capacitive feed through from V 3 through the parasitic gate overlap capacitance of transistor 24.
  • this value is minimized by using a P-channel and an N-channel tran ⁇ sistor with complementary clock drives, and by using a relatively large value capacitor 20.
  • a full circuit diagram for the sample and hold type circuit 10 is shown in greater detail, including all of the elements of a particular operational amplifier 10 comprised of complementary MOS elements.
  • the operational amplifier 10 is comprised of a differential amplifier 32, connected to a biasing network 34, and an intermediate level shift stage 36, connected to an output stage 38.
  • the differential ampli ⁇ bomb typically includes an input stage 40 and a constant current source 42.
  • the bias network 34 which assures that the appropriate MOSFET devices of the circuit operate in the proper saturation region, comprises two MOSFET devices 44 and 46, each having source, drain and gate electrodes.
  • the source electrode of transistor 44 is connected to a positive voltage supply V DD via a power lead 48 and the source of transistor 46 is connected by a lead 50 to a negative power supply gg .
  • the drain and gate electrodes of transistor 44 are connected to a junctio 52 and the drain and gate electrodes of transistor 46 are connected to a junction 54. These junctions 52 and 54 are interconnected by a lead 56, and a lead 58, from the junction 54 provides the biasing voltage for the circuit.
  • the constant current source 42 comprises a MOSFET device 60, whose gate is connected to the biasing voltage lead 58.
  • the source of transistor 60 is connected to the negative power lead 50 and its drain is connected to the input stage 40 of the differential amplifier.
  • This input stage comprises a pair of MOSFET devices 62 and 64, whose respective source electrodes are con ⁇ nected to a common lead 66, which is also connected to the drain of transistor 60.
  • a drain electrode of the device 62 is connected to a junction 68 of the differential amplifier and the drain electrode of device 64 is con ⁇ nected to a junction 70 of the differential amplifier.
  • the gate of input device 62 is connected to a negative input terminal of the operational amplifier and the gate of device 64 is connected to ground.
  • the load section of the differential amplifier 32 [ comprises a pair of MOSFET devices 72 and 74, whose source ', terminals are both connected to the positive power lead 48.
  • the gates of these devices are interconnected by a j lead 76 which is also connected by a lead 78 to the I junction 68.
  • the intermediate level shift stage 36 of the opera- - tional amplifier 11 comprises a pair of MOSFET devices 80 ; and 82, connected in series between the positive and negative power leads.
  • the drain of device 80 is connected to the positive power lead 48 and the source of device 82 : is connected to the negative power lead 50.
  • the source of device 80 is connected by a lead 84 to
  • a second junction 94 in the lead 86 is
  • the output stage 38 comprises the MOSFET device 92, whose source is connected to the positive power lead 48 and a second MOSFET device 100 whose source is connected to the negative power lead 50.
  • the drain electrodes of these two transistors are interconnected by a common lead
  • MOSFET 100 is connected by a lead 104 to a junction 106 in the lead 84 between the devices 80 and 82.
  • a second portion of the output stage is preferably provided in the form of an NPN transistor 108 whose emitter
  • terminal is connected by a lead 110 to an N-channel MOS transistor 112.
  • the collector of device 108 is connected to V n line 48 and the source of transistor 112 is con ⁇ nected to V c ⁇ line 50.
  • the base of transistor 108 is connected by a lead 114 to the interconnecting lead 102 and the gate of device 112 is connected to the lead 104 ⁇ from the level shift section.
  • a frequency compensation means for the operational : amplifier is preferably provided between the differential amplifier section 32 and the output stage 38. It comprises a capacitor 116 (C 2 ) having one side connected to a junctio j 118 in the output side of the differential amplifier 32. The other side of this capacitor is connected by a lead
  • MOSFET ' 124 is connected to power lead 48 and the gate of MOSFET .126 is connected to lead 50.
  • a capacitor 129 which is used to frequency compensate the output stage.
  • the operational amplifier 11 functions in the con-
  • CMOS transistor elements and compatible NPN type transistors
  • the circuit 10 may be readily included as one of several building blocks of much larger integrated circuits re-

Landscapes

  • Amplifiers (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

Circuit echantillonneur-bloqueur utilisant un amplificateur operationnel adapte pour la mise en application en tant que circuit integre comprenant des elements de transistor MOS. L'amplificateur operationnel (11) possede un terminal positif (+) connecte a la masse et un fil negatif d'entree connecte a une extremite d'un condensateur (20), l'autre extremite duquel est connectee a un premier transistor MOS (18) dont la porte est commandee par des signaux d'horloge (V1). Un fil de retroaction (22) venant de la sortie (16) de l'amplificateur operationnel est connecte en parallele au deuxieme (24) et au troisieme (26) transistors. Le deuxieme transistor (24) est connecte au fil d'entree entre le condensateur et l'amplificateur operationnels et le troisieme transistor (26) est connecte au fil d'entree entre le condensateur et le premier transistor. Les portes du deuxieme et du troisieme transistors sont connectees a des sources separees (V3, V2) de signaux d'horloge. La synchronisation des signaux d'horloge aux trois transistors est telle que le signal (V) a l'entree est echantillonne et bloque et que le decalage de l'amplificateur operationnel est annule.
PCT/US1980/001130 1979-09-27 1980-09-02 Circuit echantillonneur-bloqueur avec annulation du decalage WO1981000928A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19803049671 DE3049671A1 (en) 1979-09-27 1980-09-02 Sample and hold circuit with offset cancellation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7933979A 1979-09-27 1979-09-27
US79339 1979-09-27

Publications (1)

Publication Number Publication Date
WO1981000928A1 true WO1981000928A1 (fr) 1981-04-02

Family

ID=22149901

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1980/001130 WO1981000928A1 (fr) 1979-09-27 1980-09-02 Circuit echantillonneur-bloqueur avec annulation du decalage

Country Status (7)

Country Link
JP (1) JPS56501223A (fr)
DE (1) DE3049671A1 (fr)
FR (1) FR2466838A1 (fr)
GB (1) GB2075781A (fr)
NL (1) NL8020352A (fr)
SE (1) SE8103279L (fr)
WO (1) WO1981000928A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0205201A1 (fr) * 1985-05-24 1986-12-17 Koninklijke Philips Electronics N.V. Agencement de circuit d'échantillonnage et de maintien
US4691125A (en) * 1986-10-03 1987-09-01 Motorola, Inc. One hundred percent duty cycle sample-and-hold circuit
US4916507A (en) * 1982-10-07 1990-04-10 Bull S.A. Polysilicon resistor implanted with rare gas
US5376841A (en) * 1990-01-26 1994-12-27 Kabushiki Kaisha Toshiba Sample-and-hold circuit device
KR100557501B1 (ko) * 2003-06-30 2006-03-07 엘지.필립스 엘시디 주식회사 아날로그 버퍼 및 그 구동방법

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2214018A (en) * 1987-12-23 1989-08-23 Philips Electronic Associated Current mirror circuit arrangement
JP2777302B2 (ja) * 1992-01-16 1998-07-16 株式会社東芝 オフセット検出回路、出力回路および半導体集積回路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4066919A (en) * 1976-04-01 1978-01-03 Motorola, Inc. Sample and hold circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3441913A (en) * 1966-04-12 1969-04-29 James J Pastoriza Multiple signal sampling and storage elements sequentially discharged through an operational amplifier
FR96064E (fr) * 1968-10-31 1972-05-19 Ferrieu Gilbert Dispositif échantillonneur a mémoire de signaux analogiques.

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4066919A (en) * 1976-04-01 1978-01-03 Motorola, Inc. Sample and hold circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916507A (en) * 1982-10-07 1990-04-10 Bull S.A. Polysilicon resistor implanted with rare gas
EP0205201A1 (fr) * 1985-05-24 1986-12-17 Koninklijke Philips Electronics N.V. Agencement de circuit d'échantillonnage et de maintien
US4691125A (en) * 1986-10-03 1987-09-01 Motorola, Inc. One hundred percent duty cycle sample-and-hold circuit
US5376841A (en) * 1990-01-26 1994-12-27 Kabushiki Kaisha Toshiba Sample-and-hold circuit device
KR100557501B1 (ko) * 2003-06-30 2006-03-07 엘지.필립스 엘시디 주식회사 아날로그 버퍼 및 그 구동방법

Also Published As

Publication number Publication date
DE3049671A1 (en) 1982-02-25
SE8103279L (sv) 1981-05-25
JPS56501223A (fr) 1981-08-27
FR2466838A1 (fr) 1981-04-10
NL8020352A (nl) 1981-07-01
GB2075781A (en) 1981-11-18

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