US20100171536A1 - Voltage selecting circuit, voltage providing circuit utilizing the voltage selecting circuit, and signal delaying system utilizing the voltage providing circuit - Google Patents

Voltage selecting circuit, voltage providing circuit utilizing the voltage selecting circuit, and signal delaying system utilizing the voltage providing circuit Download PDF

Info

Publication number
US20100171536A1
US20100171536A1 US12/357,376 US35737609A US2010171536A1 US 20100171536 A1 US20100171536 A1 US 20100171536A1 US 35737609 A US35737609 A US 35737609A US 2010171536 A1 US2010171536 A1 US 2010171536A1
Authority
US
United States
Prior art keywords
voltage
circuit
providing
mode
providing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US12/357,376
Other versions
US7746165B1 (en
Inventor
Chih-Jen Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Assigned to NANYA TECHNOLOGY CORP. reassignment NANYA TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, CHIH-JEN
Priority to US12/779,937 priority Critical patent/US7821332B2/en
Application granted granted Critical
Publication of US7746165B1 publication Critical patent/US7746165B1/en
Publication of US20100171536A1 publication Critical patent/US20100171536A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4065—Low level details of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

Definitions

  • the present invention relates to a voltage selecting circuit and a voltage providing circuit utilizing this voltage selecting circuit, and more particularly, to a signal delaying system utilizing the aforementioned voltage selecting circuit and voltage providing circuit.
  • a delayed lock loop (DLL) circuit is generally utilized to provide a required clock signal.
  • the memory can be operated in a normal mode, a self refresh mode, or a power down mode.
  • the normal mode is that the memory is normally accessed and the DLL operates normally for delaying an input signal (usually a clock signal) to generate a delayed signal.
  • the self refresh mode is that the memory executes self refreshing without any help from an external circuit.
  • the power down mode is that the memory is in a stand-by mode without performing any data access.
  • the DLL circuit In the normal mode of the memory, the DLL circuit is provided with a DLL voltage (V DLL , it can also be viewed as a control voltage) to control delay time of the DLL circuit.
  • V DLL DLL voltage
  • a stand-by voltage is provided to the DLL circuit while the DLL voltage provided to the DLL circuit is stopped.
  • FIG. 1 illustrates a conventional relationship between the control voltage and standby voltage provided to a DLL circuit according to the prior art. As shown in FIG. 1 , the control voltage is usually higher than the stand-by voltage.
  • one objective of the present invention is to provide an adjusting mechanism to solve the aforementioned time delay problem resulted from the control voltage and stand-by voltage in the prior art.
  • a voltage providing circuit comprises: a first voltage providing circuit, for generating a first voltage; a switch element, for receiving the first voltage; a control circuit, for controlling the switch element and the second voltage providing circuit, wherein in a first mode, the control circuit turns off the switch element for allowing a target apparatus to receive the second voltage, and in a second mode, the control circuit turns on the switch element and stops the second voltage providing circuit from providing the second voltage, thereby providing the first voltage to the target apparatus; and an adjusting circuit, coupled to the first voltage providing circuit and the second voltage providing circuit, for providing a reference voltage to the first voltage providing circuit according to the first voltage and the second voltage for altering the first voltage, thereby making the first voltage substantially equal to the second voltage.
  • a signal delaying system comprises: a delay locked loop (DLL) circuit, for delaying an input signal to generate a delay signal; and a voltage providing circuit, for providing a control voltage to the DLL circuit to determine a delay time of the DLL circuit when the DLL circuit operates in a first mode; and for providing a stand-by voltage to the DLL circuit, wherein the voltage providing circuit further adjust the stand-by voltage to make the stand-by voltage substantially equal to the control voltage.
  • DLL delay locked loop
  • a voltage selecting system comprises: a comparator, for comparing a first voltage and a second voltage to generate a comparison result; a counter, coupled to the comparator, for generating a counting signal according to the comparison result; and a multiplexer, coupled to the counter, for receiving a plurality of candidate voltages and selecting one of the candidate voltages as an output voltage according to the counting result.
  • the time delay problem resulted from the difference between the control voltage and the stand-by voltage in the prior art design can be compensated and solved.
  • FIG. 1 is a diagram illustrating a relationship between a control voltage and a stand-by voltage provided to a DLL circuit according to the prior art.
  • FIG. 2 is a diagram illustrating a signal delay system according to the present invention.
  • FIG. 3 is a diagram illustrating a preferred embodiment of an adjusting circuit shown in FIG. 2 .
  • FIG. 2 illustrates a signal delaying system 200 according to an embodiment of the present invention.
  • the signal delaying system 200 comprises a DLL circuit 201 and a voltage providing circuit 203 .
  • the DLL circuit 201 delays an input signal S in to generate a delayed signal S out .
  • the voltage providing circuit 203 provides a control voltage V DLL to the DLL circuit 201 for determining a delay time of the DLL circuit 201 when the DLL circuit 201 operates in a first mode, and provides a stand-by voltage V sb to the DLL circuit 201 when the DLL circuit 201 operates in a second mode.
  • the voltage providing circuit 203 further adjusts the stand-by voltage V sb to make the stand-by voltage V sb equal to the control voltage V DLL .
  • a memory e.g., a Dynamic Random Access Memory, DRAM
  • the first mode represents that the memory operates in a normal mode
  • the second mode represents that the memory operates in a self refresh mode or a power down mode.
  • the voltage providing circuit 203 comprises a stand-by voltage providing circuit 205 , a switch element 207 (e.g., a PMOS transistor in this embodiment), a control circuit 209 , a control voltage providing circuit 211 , and an adjusting circuit 213 .
  • the stand-by voltage providing circuit 205 is configured for generating the stand-by voltage V sb .
  • the switch element 207 is configured for receiving the stand-by voltage V sb .
  • the control circuit 209 is configured for controlling the switch element 207 and the control voltage providing circuit 211 .
  • the control voltage 211 is configured for providing the control voltage V DLL .
  • the control circuit 209 controls the control voltage providing circuit 211 to provide the control voltage V DLL and makes the switch element 207 not conduct when the DLL circuit 201 is in the first mode.
  • the control circuit 209 stops the control voltage providing circuit 211 from providing the control voltage V DLL to the DLL circuit 201 , and makes the switch element 207 conduct to provide the stand-by voltage V sb to the DLL circuit 201 .
  • the adjusting circuit 213 provides a reference voltage V ref to the stand-by voltage providing circuit 205 according to the stand-by voltage V sb and the control voltage V DLL , thereby making the stand-by voltage providing circuit 205 alter the stand-by voltage V sb .
  • the stand-by voltage V sb is substantially equal to the control voltage V DLL .
  • the voltage providing circuit 203 is not limited to providing a voltage to the DLL circuit 201 ; in other words, the voltage providing circuit 203 can be configured for providing a voltage to other electronic apparatus as well.
  • the operation of the voltage providing circuit 203 can be as follows: providing a first voltage for a target apparatus when the target apparatus is in a first mode; providing a second voltage for the target apparatus and adjusting the first and the second voltage to make them substantially equal to each other when the target apparatus is in a second mode.
  • FIG. 3 illustrates a preferred embodiment of the adjusting circuit 213 shown in FIG. 2 .
  • the circuit architecture shown in FIG. 3 is for illustrative purposes only, and it is not meant to be a limitation to the scope of this invention.
  • the adjusting circuit 213 comprises a comparator 301 , a counter 303 , and a multiplexer 305 .
  • the comparator 301 compares the stand-by voltage V sb with the control voltage V DLL to generate a comparison result.
  • the counter 303 generates a counting signal CVS according to the comparison result.
  • the multiplexer 305 receives a plurality of candidate voltages V ref1 -V refn , and selects one of the candidate voltages V ref1 -V refn as the reference voltage V ref according to the counting signal CVS.
  • the control voltage V DLL when the control voltage V DLL is higher than the stand-by voltage V sb , the counter 303 counts once, for example, to make a 4-bit signal “ 1000 ” become “ 1001 ”. Therefore, the selected reference voltage V ref will be different.
  • a higher reference voltage V ref is selected; otherwise, a lower reference voltage V ref is selected.
  • the selection principle is not meant to be a limitation to the present invention.
  • the circuit shown in FIG. 3 can be utilized in an architecture other than the one shown in FIG. 2 .
  • the comparator 301 compares a first voltage with a second voltage to generate a comparison result
  • the counter 303 generates a counting signal CVS according to the comparison result
  • the multiplexer 305 receives a plurality of candidate voltages V ref1 -V refn and selects one of the candidate voltages V ref1 -V refn as the reference voltage V ref according to the counting signal CVS.
  • the adjusting circuit 213 shown in FIG. 3 can also be viewed as a voltage selecting circuit.
  • the time delay problem resulted from the difference between the control voltage and the stand-by voltage in the prior art design can be compensated and solved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)

Abstract

A voltage providing circuit includes: a first voltage providing circuit, for generating a first voltage; a switch device, for receiving a first voltage; a second voltage providing circuit, for providing a second voltage; a control circuit, for controlling the switch device and the second voltage providing circuit, wherein in a first mode, the control circuit turns off the switch device for allowing a target device to receive the second voltage, and in a second mode, the control circuit turns on the switch device and stops the second voltage providing circuit from providing the second voltage such that the target device can receive the first voltage; and an adjusting circuit, for providing a reference voltage to the first voltage providing circuit according to the first voltage and the second voltage for changing the first voltage, thereby making the first voltage substantially equal to the second voltage.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a voltage selecting circuit and a voltage providing circuit utilizing this voltage selecting circuit, and more particularly, to a signal delaying system utilizing the aforementioned voltage selecting circuit and voltage providing circuit.
  • 2. Description of the Prior Art
  • In a typical memory control system, a delayed lock loop (DLL) circuit is generally utilized to provide a required clock signal. The memory can be operated in a normal mode, a self refresh mode, or a power down mode. The normal mode is that the memory is normally accessed and the DLL operates normally for delaying an input signal (usually a clock signal) to generate a delayed signal. The self refresh mode is that the memory executes self refreshing without any help from an external circuit. The power down mode is that the memory is in a stand-by mode without performing any data access.
  • In the normal mode of the memory, the DLL circuit is provided with a DLL voltage (VDLL, it can also be viewed as a control voltage) to control delay time of the DLL circuit. In the self refresh mode or the power down mode of the memory, a stand-by voltage is provided to the DLL circuit while the DLL voltage provided to the DLL circuit is stopped. However, there exist some problems in this conventional mechanism. FIG. 1 illustrates a conventional relationship between the control voltage and standby voltage provided to a DLL circuit according to the prior art. As shown in FIG. 1, the control voltage is usually higher than the stand-by voltage. Therefore, after providing a stand-by voltage to the DLL circuit while stopping providing the DLL voltage to the DLL circuit, a specific time td is required to raise the voltage if the DLL circuit intends to go back in the normal mode, which leads to a delay in time as well as a drawback in the overall circuit system.
    • SUMMARY OF THE INVENTION
  • Therefore, one objective of the present invention is to provide an adjusting mechanism to solve the aforementioned time delay problem resulted from the control voltage and stand-by voltage in the prior art.
  • According to one embodiment of the present invention, a voltage providing circuit is disclosed. The voltage providing circuit comprises: a first voltage providing circuit, for generating a first voltage; a switch element, for receiving the first voltage; a control circuit, for controlling the switch element and the second voltage providing circuit, wherein in a first mode, the control circuit turns off the switch element for allowing a target apparatus to receive the second voltage, and in a second mode, the control circuit turns on the switch element and stops the second voltage providing circuit from providing the second voltage, thereby providing the first voltage to the target apparatus; and an adjusting circuit, coupled to the first voltage providing circuit and the second voltage providing circuit, for providing a reference voltage to the first voltage providing circuit according to the first voltage and the second voltage for altering the first voltage, thereby making the first voltage substantially equal to the second voltage.
  • According to another embodiment of the present invention, a signal delaying system is disclosed. The signal delaying system comprises: a delay locked loop (DLL) circuit, for delaying an input signal to generate a delay signal; and a voltage providing circuit, for providing a control voltage to the DLL circuit to determine a delay time of the DLL circuit when the DLL circuit operates in a first mode; and for providing a stand-by voltage to the DLL circuit, wherein the voltage providing circuit further adjust the stand-by voltage to make the stand-by voltage substantially equal to the control voltage.
  • According to yet another embodiment of the present invention, a voltage selecting system is disclosed. The voltage selecting system comprises: a comparator, for comparing a first voltage and a second voltage to generate a comparison result; a counter, coupled to the comparator, for generating a counting signal according to the comparison result; and a multiplexer, coupled to the counter, for receiving a plurality of candidate voltages and selecting one of the candidate voltages as an output voltage according to the counting result.
  • According to the aforementioned embodiments, the time delay problem resulted from the difference between the control voltage and the stand-by voltage in the prior art design can be compensated and solved.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram illustrating a relationship between a control voltage and a stand-by voltage provided to a DLL circuit according to the prior art.
  • FIG. 2 is a diagram illustrating a signal delay system according to the present invention.
  • FIG. 3 is a diagram illustrating a preferred embodiment of an adjusting circuit shown in FIG. 2.
    •  DETAILED DESCRIPTION
  • Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Besides, the term “couple” is used here to refer any kind of direct or indirect electrical connection. Therefore, if a first apparatus is coupled to a second apparatus in the description, it means that the first apparatus is directly electrically connected to the second apparatus or indirectly connected to the second apparatus through other apparatus or method.
  • FIG. 2 illustrates a signal delaying system 200 according to an embodiment of the present invention. As shown in FIG. 2, the signal delaying system 200 comprises a DLL circuit 201 and a voltage providing circuit 203. The DLL circuit 201 delays an input signal Sin to generate a delayed signal Sout. The voltage providing circuit 203 provides a control voltage VDLL to the DLL circuit 201 for determining a delay time of the DLL circuit 201 when the DLL circuit 201 operates in a first mode, and provides a stand-by voltage Vsb to the DLL circuit 201 when the DLL circuit 201 operates in a second mode. The voltage providing circuit 203 further adjusts the stand-by voltage Vsb to make the stand-by voltage Vsb equal to the control voltage VDLL. In this way, the aforementioned problem in the prior art can be avoided. When the circuit architecture shown in FIG. 2 is utilized in a memory (e.g., a Dynamic Random Access Memory, DRAM), i.e., the delayed signal Sout is provided to a memory, the first mode represents that the memory operates in a normal mode, and the second mode represents that the memory operates in a self refresh mode or a power down mode.
  • In one exemplary embodiment, the voltage providing circuit 203 comprises a stand-by voltage providing circuit 205, a switch element 207 (e.g., a PMOS transistor in this embodiment), a control circuit 209, a control voltage providing circuit 211, and an adjusting circuit 213. The stand-by voltage providing circuit 205 is configured for generating the stand-by voltage Vsb. The switch element 207 is configured for receiving the stand-by voltage Vsb. The control circuit 209 is configured for controlling the switch element 207 and the control voltage providing circuit 211. The control voltage 211 is configured for providing the control voltage VDLL.
  • The control circuit 209 controls the control voltage providing circuit 211 to provide the control voltage VDLL and makes the switch element 207 not conduct when the DLL circuit 201 is in the first mode. When the DLL circuit 201 enters the second mode, the control circuit 209 stops the control voltage providing circuit 211 from providing the control voltage VDLL to the DLL circuit 201, and makes the switch element 207 conduct to provide the stand-by voltage Vsb to the DLL circuit 201. The adjusting circuit 213 provides a reference voltage Vref to the stand-by voltage providing circuit 205 according to the stand-by voltage Vsb and the control voltage VDLL, thereby making the stand-by voltage providing circuit 205 alter the stand-by voltage Vsb. As a result, the stand-by voltage Vsb is substantially equal to the control voltage VDLL. It should be noted that the voltage providing circuit 203 is not limited to providing a voltage to the DLL circuit 201; in other words, the voltage providing circuit 203 can be configured for providing a voltage to other electronic apparatus as well. In this case, the operation of the voltage providing circuit 203 can be as follows: providing a first voltage for a target apparatus when the target apparatus is in a first mode; providing a second voltage for the target apparatus and adjusting the first and the second voltage to make them substantially equal to each other when the target apparatus is in a second mode.
  • FIG. 3 illustrates a preferred embodiment of the adjusting circuit 213 shown in FIG. 2. It should be noted that the circuit architecture shown in FIG. 3 is for illustrative purposes only, and it is not meant to be a limitation to the scope of this invention. As shown in FIG. 3, the adjusting circuit 213 comprises a comparator 301, a counter 303, and a multiplexer 305. The comparator 301 compares the stand-by voltage Vsb with the control voltage VDLL to generate a comparison result. The counter 303 generates a counting signal CVS according to the comparison result. The multiplexer 305 receives a plurality of candidate voltages Vref1-Vrefn, and selects one of the candidate voltages Vref1-Vrefn as the reference voltage Vref according to the counting signal CVS. In one exemplary embodiment, when the control voltage VDLL is higher than the stand-by voltage Vsb, the counter 303 counts once, for example, to make a 4-bit signal “1000” become “1001”. Therefore, the selected reference voltage Vref will be different. In another exemplary embodiment, when the control voltage VDLL is higher than the stand-by voltage Vsb, a higher reference voltage Vref is selected; otherwise, a lower reference voltage Vref is selected. The selection principle is not meant to be a limitation to the present invention. It should be noted that the circuit shown in FIG. 3 can be utilized in an architecture other than the one shown in FIG. 2. In this case, the comparator 301 compares a first voltage with a second voltage to generate a comparison result, the counter 303 generates a counting signal CVS according to the comparison result, and the multiplexer 305 receives a plurality of candidate voltages Vref1-Vrefn and selects one of the candidate voltages Vref1-Vrefn as the reference voltage Vref according to the counting signal CVS. In addition, the adjusting circuit 213 shown in FIG. 3 can also be viewed as a voltage selecting circuit.
  • According to the aforementioned exemplary embodiments, the time delay problem resulted from the difference between the control voltage and the stand-by voltage in the prior art design can be compensated and solved.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (7)

1. A voltage providing circuit, comprising:
a first voltage providing circuit, for providing a first voltage;
a switch element, for receiving the first voltage;
a second voltage providing circuit, for providing a second voltage;
a control circuit, for controlling the switch element and the second voltage providing circuit, wherein in a first mode, the control circuit turns off the switch element for allowing a target apparatus to receive the second voltage, and in a second mode, the control circuit turns on the switch element, and stops the second voltage providing circuit from providing the second voltage to therefore provide the first voltage to the target apparatus; and
an adjusting circuit, coupled to the first voltage providing circuit and the second voltage providing circuit, for providing a reference voltage to the first voltage providing circuit for altering the first voltage, according to the first voltage and the second voltage, thereby making the first voltage substantially equal to the second voltage.
2. The voltage providing circuit of claim 1, wherein the target apparatus is a delay locked loop circuit, and the second voltage is for controlling a delay time of the delay locked loop circuit.
3. The voltage providing circuit of claim 2, wherein the delay locked loop circuit is utilized in a memory, the first mode corresponds to a normal mode in which the memory operates, and the second mode corresponds to a power down mode or a self refresh mode in which the memory operates.
4. The voltage providing circuit of claim 1, wherein the adjusting circuit provides a higher reference voltage when the first voltage is higher than the second voltage.
5. The voltage providing circuit of claim 4, wherein the adjusting circuit provides a lower reference voltage when the first voltage is lower than the second voltage.
6. The voltage providing circuit of claim 1, wherein the adjusting circuit comprises:
a comparator, for comparing the first voltage and the second voltage to generate a comparison result;
a counter, coupled to the comparator, for generating a counting signal according to the comparison result; and
a multiplexer, coupled to the counter, for receiving a plurality of candidate voltages and selecting one of the candidate voltages as the reference voltage according to the counting signal.
7-13. (canceled)
US12/357,376 2009-01-05 2009-01-21 Voltage selecting circuit, voltage providing circuit utilizing the voltage selecting circuit, and signal delaying system utilizing the voltage providing circuit Active US7746165B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/779,937 US7821332B2 (en) 2009-01-05 2010-05-13 Signal delaying system utilizing voltage providing circuit

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
TW098100095 2009-01-05
TW98100095A 2009-01-05
TW098100095A TWI401693B (en) 2009-01-05 2009-01-05 Voltage providing circuit, and signal delaying system utilizing the voltage providing circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/779,937 Division US7821332B2 (en) 2009-01-05 2010-05-13 Signal delaying system utilizing voltage providing circuit

Publications (2)

Publication Number Publication Date
US7746165B1 US7746165B1 (en) 2010-06-29
US20100171536A1 true US20100171536A1 (en) 2010-07-08

Family

ID=42271203

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/357,376 Active US7746165B1 (en) 2009-01-05 2009-01-21 Voltage selecting circuit, voltage providing circuit utilizing the voltage selecting circuit, and signal delaying system utilizing the voltage providing circuit
US12/779,937 Active US7821332B2 (en) 2009-01-05 2010-05-13 Signal delaying system utilizing voltage providing circuit

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/779,937 Active US7821332B2 (en) 2009-01-05 2010-05-13 Signal delaying system utilizing voltage providing circuit

Country Status (2)

Country Link
US (2) US7746165B1 (en)
TW (1) TWI401693B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090284290A1 (en) * 2008-05-16 2009-11-19 Elpida Memory, Inc. Dll circuit adapted to semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101062743B1 (en) * 2009-04-15 2011-09-06 주식회사 하이닉스반도체 Semiconductor integrated circuit and control method thereof

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5815028A (en) * 1996-09-16 1998-09-29 Analog Devices, Inc. Method and apparatus for frequency controlled bias current
US5973528A (en) * 1998-04-16 1999-10-26 Motorola, Inc. Control circuit and method for a temperature sensitive device
US6366155B1 (en) * 1999-07-13 2002-04-02 Samsung Electronics Co., Ltd. Reference voltage generators and methods including supplementary current generation, and integrated circuits including the same
US6906576B2 (en) * 2003-10-07 2005-06-14 Atmel Corporation High precision digital-to-analog converter with optimized power consumption
US7436246B2 (en) * 2007-02-26 2008-10-14 Ana Semiconductor Pin number reduction circuit and methodology for mixed-signal IC, memory IC, and SOC
US7551020B2 (en) * 2007-05-31 2009-06-23 Agere Systems Inc. Enhanced output impedance compensation
US20090212853A1 (en) * 2008-02-25 2009-08-27 Hynix Semiconductor Inc. Apparatus for supplying power in semiconductor integrated circuit and input impedance control method of the same
US7583034B2 (en) * 2006-09-26 2009-09-01 Semiconductor Components Industries, L.L.C. LED controller and method therefor
US20090237152A1 (en) * 2005-09-29 2009-09-24 Chang-Ho Do Internal voltage generator
US20100026380A1 (en) * 2008-07-30 2010-02-04 Memocom Corp. Reference Generating Apparatus and Sampling Apparatus Thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422572B1 (en) * 2001-06-30 2004-03-12 주식회사 하이닉스반도체 Register controlled delay locked loop and semiconductor device having the same
US6909320B2 (en) * 2003-06-19 2005-06-21 Freescale Semiconductor, Inc. Method and apparatus for dual output voltage regulation
KR100546135B1 (en) * 2004-05-17 2006-01-24 주식회사 하이닉스반도체 Memory device with delay lock loop
US7126370B2 (en) * 2004-10-28 2006-10-24 International Business Machines Corporation Power gating techniques able to have data retention and variability immunity properties
KR100753100B1 (en) * 2005-09-29 2007-08-31 주식회사 하이닉스반도체 Delay locked loop in semiconductor memory device
KR100733465B1 (en) * 2005-09-29 2007-06-29 주식회사 하이닉스반도체 Delay locked loop circuit
JP4911988B2 (en) * 2006-02-24 2012-04-04 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4772733B2 (en) * 2007-04-13 2011-09-14 株式会社東芝 DLL circuit

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5815028A (en) * 1996-09-16 1998-09-29 Analog Devices, Inc. Method and apparatus for frequency controlled bias current
US5973528A (en) * 1998-04-16 1999-10-26 Motorola, Inc. Control circuit and method for a temperature sensitive device
US6366155B1 (en) * 1999-07-13 2002-04-02 Samsung Electronics Co., Ltd. Reference voltage generators and methods including supplementary current generation, and integrated circuits including the same
US6906576B2 (en) * 2003-10-07 2005-06-14 Atmel Corporation High precision digital-to-analog converter with optimized power consumption
US20090237152A1 (en) * 2005-09-29 2009-09-24 Chang-Ho Do Internal voltage generator
US7583034B2 (en) * 2006-09-26 2009-09-01 Semiconductor Components Industries, L.L.C. LED controller and method therefor
US7436246B2 (en) * 2007-02-26 2008-10-14 Ana Semiconductor Pin number reduction circuit and methodology for mixed-signal IC, memory IC, and SOC
US7551020B2 (en) * 2007-05-31 2009-06-23 Agere Systems Inc. Enhanced output impedance compensation
US20090212853A1 (en) * 2008-02-25 2009-08-27 Hynix Semiconductor Inc. Apparatus for supplying power in semiconductor integrated circuit and input impedance control method of the same
US20100026380A1 (en) * 2008-07-30 2010-02-04 Memocom Corp. Reference Generating Apparatus and Sampling Apparatus Thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090284290A1 (en) * 2008-05-16 2009-11-19 Elpida Memory, Inc. Dll circuit adapted to semiconductor device
US8013645B2 (en) * 2008-05-16 2011-09-06 Elpida Memory, Inc. DLL circuit adapted to semiconductor device
USRE45604E1 (en) * 2008-05-16 2015-07-07 Ps4 Luxco S.A.R.L. DLL circuit adapted to semiconductor device

Also Published As

Publication number Publication date
US7746165B1 (en) 2010-06-29
TWI401693B (en) 2013-07-11
US20100219868A1 (en) 2010-09-02
TW201027549A (en) 2010-07-16
US7821332B2 (en) 2010-10-26

Similar Documents

Publication Publication Date Title
US7605622B2 (en) Delay locked loop circuit
US6605969B2 (en) Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers
US7352218B2 (en) DLL circuit and method of controlling the same
US7759998B2 (en) Timing adjustment circuit
US7414446B2 (en) DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus
US7821308B2 (en) Delay locked loop and method of controlling the same
US20120081160A1 (en) Delay locked loop circuit of semiconductor memory apparatus
US7612587B2 (en) Semiconductor circuits
JP2012123862A (en) Semiconductor device and method of controlling the same
US7372760B2 (en) Semiconductor device and entry into test mode without use of unnecessary terminal
US7746165B1 (en) Voltage selecting circuit, voltage providing circuit utilizing the voltage selecting circuit, and signal delaying system utilizing the voltage providing circuit
US6765836B2 (en) Semiconductor memory with a clock synchronization device having a temperature controlled delay circuit
US10515670B1 (en) Memory apparatus and voltage control method thereof
US7795936B2 (en) Data center tracking circuit and semiconductor integrated circuit including the same
US7705634B2 (en) Input circuit of semiconductor integrated circuit
US20090160542A1 (en) Stable voltage generating circuit for a delay locked loop and semiconductor memory device including the same and method of generating a stable voltage for a delay locked loop
CN101783161B (en) Voltage selection circuit, voltage supply circuit and signal delay system
KR20180047209A (en) Reference selecting circuit
US7633832B2 (en) Circuit for outputting data of semiconductor memory apparatus
US8804456B1 (en) Delay locked loop (DLL) system for a memory device with wide operating frequency via a variable supply applied to a delay line
US11868153B2 (en) Semiconductor integrated circuit device capable of compensating for current leakage and method of operating the same
US9007115B2 (en) Integrated circuit
US7995416B2 (en) Semiconductor memory device and operation method thereof
US20080100353A1 (en) Delay locked loop
KR20140124713A (en) Clock synchronization circuit and semiconductor memory device comprising thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: NANYA TECHNOLOGY CORP.,TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, CHIH-JEN;REEL/FRAME:022135/0508

Effective date: 20090120

Owner name: NANYA TECHNOLOGY CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, CHIH-JEN;REEL/FRAME:022135/0508

Effective date: 20090120

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12