USRE40990E1 - Data transmission across asynchronous time domains using phase-shifted data packet - Google Patents
Data transmission across asynchronous time domains using phase-shifted data packet Download PDFInfo
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- USRE40990E1 USRE40990E1 US11/805,866 US80586607A USRE40990E US RE40990 E1 USRE40990 E1 US RE40990E1 US 80586607 A US80586607 A US 80586607A US RE40990 E USRE40990 E US RE40990E
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
Definitions
- the present invention generally relates to the field of electronic circuits. More specifically, the present invention relates to a method and apparatus for passing data across an asynchronous clock boundary.
- Such devices are being networked together.
- Such devices are often first coupled to a local area network, such as an Ethernet based office/home network.
- the local area networks are interconnected together through wide area networks, such as ATM networks, Frame Relays, and the TCP/IP based global inter-networks, Internet.
- data typically flows through one or more devices functioning e.g. as a network bridge or router.
- a network bridge or router During the transition between such devices, and even between components within a single device, data will often be driven by multiple asynchronous clock signals regulating the respective traffic flows.
- FIG. 1 is a timing diagram generated in accordance with the prior art illustrating the relationship between two asynchronous clock signals and a data signal to be passed from the first time domain to the second.
- the data transitions at point ( 10 b- 10 b)( 10 b- 14 b ) corresponding to the rising edges ( 10 a- 14 a) of CLOCK A. Between each of these transition points the data is considered to be stable and valid.
- Clock B represents a clock signal from a second time domain operating asynchronously to CLOCK A.
- Each rising edge of clock signal B defines one of the eight time intervals indicated by dotted lines in FIG. 1 . That is, each of the time intervals corresponds to one period of CLOCK B.
- FIG. 1 is a timing diagram generated in accordance with the prior art illustrating the relationship between two asynchronous clock signals and a data signal to be passed from the first time domain to the second;
- FIG. 2 is a block diagram illustrating an overview of the present invention
- FIG. 3 illustrates a more detailed view of stability logic 200 in accordance with one embodiment of the invention
- FIG. 4 is a timing diagram illustrating phase relationships between various input signals of selection logic 300 , in accordance with one embodiment
- FIG. 5 illustrates a detailed view of one embodiment of selection logic 300 ;
- FIG. 6 is a timing diagram illustrating an additional bus signal to be used for identifying duplicative output data.
- FIG. 7 illustrates an alternative embodiment of the selection logic of the present invention including additional valid data selection logic.
- FIG. 2 is a block diagram illustrating an overview of the present invention.
- stability logic 200 of the present invention is coupled between data source 210 and data sink 220 by way of communication channels 205 and 215 , respectively.
- Data source 210 represents any of a wide variety of digital computing devices and/or components to supply data and timing signals associated with a first time domain to stability logic 200 .
- data sink 220 represents any of a wide variety of digital computing devices and/or components to receive or consume data from stability logic 200 based upon a provided timing signal associated with a second time domain.
- Communication channels 205 and 215 each represent any of a wide variety of signaling transports to transmit data and timing signals between stability logic 200 , and either data source 210 or data sink 220 , respectively.
- data source 210 may represent a network interface and data sink 220 may represent a microprocessor, while communication channels 205 and 215 may each represent a multi-bit bus architecture such as a universal serial bus (USB), a peripheral component interconnect (PCI) bus, an industry standard architecture (ISA) bus, and so forth.
- data source 210 and data sink 220 may represent independent devices interconnected with stability logic 200 by way of separate wire line and/or wireless network segments, each operating asynchronously with respect to the other.
- communication channel 205 represents an Ethernet based network segment
- communication channel 215 represents a synchronous optical network (SONET) segment.
- SONET synchronous optical network
- stability logic 200 and data sink 220 are depicted as separate devices and/or components, data source 210 and/or data sink 220 may instead be embodied with the functionality of stability logic 200 .
- stability logic 200 is implemented as an integrated circuit within data sink 220 .
- Data source 210 is shown including clock signal 206 having a first frequency (f 1 ), and data signal 208 having been sampled by clock signal 206 .
- Data signal 208 illustrates valid data segments as well as data transition points that correspond to the rising edges of clock signal 206 .
- Each transition point indicates a point in time, including an amount of time preceding and following each transition (i.e. set up and hold times), when the value of the sampled data may change with the value of the clock. During these transitions, the data is considered to be unpredictable and may possibly be invalid. In contrast, between each transition of the sampling clock (e.g. between each rising clock edge), data signal 208 is considered to be valid.
- Data sink 220 is shown including clock signal 216 having a second frequency of (f 2 ) where f 2 >f 1 .
- clock signal 216 is the sole operational clock utilized by data sink 220
- clock signal 216 is one of multiple clock signals generated and/or provided by data sink 220 .
- stability logic 200 causes data (e.g. data signal 208 ) associated with a first time domain (e.g. clock signal 206 ) to be sampled with respect to a second time domain (e.g. clock signal 216 ) such that the transition of the sampling clock signal does not coincide with a data transition point, thereby avoiding stability concerns, associated with the prior art.
- stability logic 200 aligns and samples data signal 208 based upon output clock 216 such that any given transition (e.g. rising edge) of clock signal 216 causes valid data to be sampled.
- FIG. 3 illustrates a more detailed view of stability logic 200 in accordance with one embodiment of the invention.
- stability logic 200 includes delay circuit 302 , delay circuit 304 , and selection logic 300 .
- Delay circuits 302 and 304 represent readily available analog and/or digital circuitry configured to output a phase-shifted version of a supplied input signal.
- ASIC application specific integrated circuit
- one or more inverters may be used to impart a delay on an input signal
- signal traces having increased lengths may be used to impart a delay on an input signal.
- delay circuit 302 is equipped to receive an input reference signal 306 having e.g.
- delay circuit 304 is equipped to receive a multi-bit (and by inference, a single bit) data signal having a reference phase of +2 and to generate an output data signal (DATA′) having a shifted phase of ⁇ 2 ⁇ 2N degrees.
- delay circuit 304 generates an output data signal that is approximately 180 degrees out of phase (i.e.
- 2N 180) measured with respect to the input data signal (see e.g. FIG. 4 ).
- the illustrated embodiment depicts two separate delay circuits ( 302 and 304 ), the present invention may likewise be practiced with a fewer or greater number of delay circuits.
- Selection logic 300 is equipped to receive the above-referenced output signal (SEL) from delay circuit 302 , the input data signal (DATA), and the output data signal from delay circuit 304 (DATA′). Additionally, selection logic is equipped to receive an output clock signal that is asynchronous with respect to reference signal 306 . In accordance with the teachings of the present invention, selection logic 300 samples both DATA and DATA′ based on the output clock and selects one of the data lines such that during each transition of the output clock, valid data is present on the selected data line. In one embodiment, selection logic 300 selects between data lines (DATA, DATA′) based at least in part upon the output of delay circuit 302 (SEL).
- FIG. 4 is a timing diagram illustrating phase relationships between various input signals of selection logic 300 , in accordance with one embodiment.
- reference signal 306 is represented by a first clock signal (CLOCK A) associated with a first time domain of frequency f 1 .
- CLOCK A first clock signal
- delay circuit 302 utilizes a phase-shifted version of CLOCK A to generate the SEL signal.
- delay circuit 302 generates an output signal that is phase shifted by up to 90 degrees measured with respect to CLOCK A.
- FIG. 4 additionally illustrates an input data signal (DATA) and its relationship to CLOCK A. The input data signal transitions at intervals corresponding to the transitioning of CLOCK A as shown.
- DATA input data signal
- sampling of the input data is triggered on the rising edge of CLOCK A, however, the input data sampling may also be negative edge triggered and level sensitive for example. Accordingly, the input data is valid for a period roughly equivalent to 1/f 1 of CLOCK A, depending e.g. upon the set-up and hold times of the sampling circuitry (to be further described below).
- the input data signal is further routed through delay circuit 304 to generate a phase-shifted version of the data identified e.g. in FIG. 4 as DATA′.
- delay circuit 304 generates an output signal that is phase-shifted by up to 180 degrees measured with respect to the input data signal (DATA).
- the DATA and DATA′ signals are phase shifted such that at any given transition of DATA′ (e.g. 402 a), the DATA signal will be valid (e.g. 402 b), and at any given transition of DATA (e.g. 404 a), the DATA′ signal will be valid (e.g. 404 b).
- FIG. 4 also includes an output clock signal (CLOCK B) associated with a second time domain of frequency f 2 .
- CLOCK B output clock signal associated with a second time domain of frequency f 2 .
- one of the input data signal (DATA) and the phase-shifted version of the input data signal (DATA′) is selected such that at any given transition of CLOCK B, valid data is selected (i.e. to generate DATA OUT).
- CLOCK B selects one of the DATA and DATA′ signals based upon the state of the SEL signal. Due to the novel relationship between the SEL, DATA and DATA′ signals of the present invention, valid data may be obtained even when SEL is transitioning.
- each of the DATA and DATA′ signals are alternatingly selected such that CLOCK B does not select the same data (i.e. DATA, DATA′) signal two or more consecutive times (to be described more fully below with respect to FIG. 6 ).
- FIG. 5 illustrates a detailed view of one embodiment of selection logic 300 .
- Selection logic 300 includes registers 510 - 515 and multiplexer (MUX) 520 coupled together as shown.
- Register 510 receives the DATA signal
- register 511 receives the DATA′ signal
- register 512 receives the SEL signal (e.g. from FIGS. 3 and 4 ).
- Each of register 510 - 515 sample these input signals based upon input from CLOCK B. That is, each of registers 510 - 515 sample the input data signals (e.g. DATA, DATA′) and the SEL signal based upon a clock signal that is asynchronous to the one or more clock signals used to generate the input signals.
- MUX multiplexer
- MUX 520 selects one of resampled input signals 517 and 518 to pass as output data from e.g. stability logic 200 based upon the state of the SEL signal.
- registers 510 - 515 are implemented as edge triggered D flip-flops, however, in other embodiments, registers 510 - 515 may be implemented through various other types of flip-flops and/or latches known in the art. Together, registers 510 - 515 operate to further reduce potential metastability concerns with stability logic 300 by providing an additional stage of resolution before being propagated to MUX 520 .
- SEL, DATA and DATA′ signals facilitates the selection of valid data from one of DATA and DATA′ regardless of whether SEL is transitioning or is stable.
- data that is actually selected in accordance with the present invention will be valid, there is a chance that the same data may be selected two or more consecutive times due to the phase lag (or lead) of DATA′.
- an extra signal (VALID SELECT) is added to e.g. the data bus that echoes the input clock (CLOCK A) at half the frequency of the clock.
- VALID SELECT may be a single-bit or multi-bit signal.
- FIG. 6 is a timing diagram illustrating such a valid select signal and its relationship to CLOCK A.
- FIG. 7 illustrates an alternative embodiment of the selection logic of the present invention including additional valid data selection logic.
- selection logic 700 includes all the elements of FIG. 5 as described above, in addition to new logic elements coupled together as shown.
- MUX 720 represents a data selector to select between the VALID SELECT and VALID SELECT′ input signals based upon the state of the SEL signal. Thus, if MUX 520 selects the DATA input signal to pass through as output data, MUX 720 will select the corresponding VALID SELECT signal to pass through as VS OUT. Conversely, if MUX 520 selects the DATA′ input signal, MUX 720 will select the corresponding VALID SELECT′ signal to pass through as VS OUT.
- VS OUT is then used as input signal into XOR gate 724 and register 722 .
- the output of register 722 is fed into XOR gate 724 , which ultimately supplies an input signal for register 723 .
- Both registers 722 - 723 (along with the remaining registers) are commonly triggered by CLOCK B.
- Such a novel configuration for the selection logic of the present invention facilitates the output of a VALID DATA signal which, when used in conjunction with DATA OUT, will indicate to down-line logic blocks whether duplicative data has been selected.
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Abstract
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US11/805,866 USRE40990E1 (en) | 2001-08-27 | 2007-05-23 | Data transmission across asynchronous time domains using phase-shifted data packet |
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US09/940,315 US6904537B1 (en) | 2001-08-27 | 2001-08-27 | Data transmission across asynchronous time domains using phase-shifted data packet |
US11/805,866 USRE40990E1 (en) | 2001-08-27 | 2007-05-23 | Data transmission across asynchronous time domains using phase-shifted data packet |
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US11/805,866 Expired - Lifetime USRE40990E1 (en) | 2001-08-27 | 2007-05-23 | Data transmission across asynchronous time domains using phase-shifted data packet |
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Families Citing this family (15)
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US6961369B1 (en) | 1999-11-09 | 2005-11-01 | Aware, Inc. | System and method for scrambling the phase of the carriers in a multicarrier communications system |
EP1245093B1 (en) | 2000-01-07 | 2006-10-25 | Aware, Inc. | Diagnostic methods and systems for multicarrier modems |
EP1433277B1 (en) | 2001-10-05 | 2012-07-25 | Aware, Inc. | Systems and methods for multi-pair atm over dsl |
WO2005086405A2 (en) | 2004-03-03 | 2005-09-15 | Aware, Inc. | Impulse noise management |
KR20100035665A (en) | 2004-09-25 | 2010-04-05 | 어웨어, 인크. | Crc counter normalization |
CA2909150C (en) | 2004-10-12 | 2017-11-07 | Tq Delta, Llc | Resource sharing in a telecommunications environment |
CN101040480B (en) | 2004-10-15 | 2011-08-31 | 阿瓦雷公司 | Dmt symbol repetition in the presence of impulse noise |
US8881233B2 (en) * | 2005-05-23 | 2014-11-04 | Microsoft Corporation | Resource management via periodic distributed time |
US20060294275A1 (en) * | 2005-06-23 | 2006-12-28 | Emil Lambrache | Fast two wire interface and protocol for transferring data |
BRPI0709871B1 (en) | 2006-04-12 | 2019-10-15 | Tq Delta, Llc. | PACKAGE RETRANSMISSION AND MEMORY SHARING |
US8176352B2 (en) * | 2008-04-16 | 2012-05-08 | Adavanced Micro Devices, Inc. | Clock domain data transfer device and methods thereof |
US8760325B2 (en) * | 2012-03-23 | 2014-06-24 | Analog Devices, Inc. | Scheme for balancing skew between lanes of high-speed serial digital interface |
CN103324597B (en) * | 2012-03-23 | 2016-06-01 | 美国亚德诺半导体公司 | The scheme of crooked distortion is balanced between the passage of high speed serial digital interface |
US9100035B2 (en) * | 2013-03-01 | 2015-08-04 | Texas Instruments Incorporated | Asynchronous sampling using a dynamically adustable snapback range |
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