USRE34245E - Two stage coding method - Google Patents
Two stage coding method Download PDFInfo
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- USRE34245E USRE34245E US07/578,178 US57817890A USRE34245E US RE34245 E USRE34245 E US RE34245E US 57817890 A US57817890 A US 57817890A US RE34245 E USRE34245 E US RE34245E
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
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- the present invention relates to a two stage coding method having a high burst error correction ability and also a random error correction ability equivalent to that of the prior art when an error correction code such as a Reed Solomon code (hereinafter referred to as "RS code”) is used in order to correct data errors which arise in reproducing data recorded in a recording material such as a magnetic disk.
- an error correction code such as a Reed Solomon code (hereinafter referred to as "RS code”
- RS code Reed Solomon code
- a data error may arise dependent on the state of the recording material.
- a data error may be a burst error caused by a signal drop out .[.on.]. .Iadd.or .Iaddend.a random error caused by a deterioration in SN ratio.
- a two stage coded error correction code is used.
- a two stage encoder is shown in FIG. 3. In FIG.
- reference numeral 1 designates an input terminal
- reference numeral 2 designates a C 2 encoder
- reference numeral 3 designates an interleaving circuit
- reference numeral 4 designates a C 1 encoder
- the reference numeral 5 designates an output terminal.
- C 2 encoding is performed on the original data, interleaving is executed thereto, and thereafter C 1 encoding is conducted, and the resulting code signal is output to the output terminal.
- a two stage decoder is shown in FIG. 4.
- reference numeral 6 designates an input terminal
- reference numeral 7 designates a C 1 decoder
- reference numeral 8 designates a deinterleaving circuit
- reference numeral 9 designates a C 2 decoder
- reference numeral 10 designates an output terminal.
- ⁇ is a root of a primary polynomial (for example, such as x 8 +x 4 +x 3 +x 2 +1 on GF (2 8 )).
- the generated check codes are arranged at the positions corresponding to the a 33 -th, a 34 -th, . . . , a 36 -th data.
- a 1 is set as follows:
- C 1 encoding is conducted on the data of n 2 digits in each column arranged in the first direction as shown in FIG. 2 with the use of the following generation polynomial of C 1 code ##EQU3##
- the generated check code is added to the end portion of the data and the encoding is repeated k 2 times.
- the sent out data are arranged in a column in the first direction by 40 digits successively.
- the C 2 code is concerned with burst error correction ability
- the C 1 and C 2 codes are concerned with random error correction ability.
- the h In the stage of conducting C 2 encoding the h must be made large in order to enhance the burst error correction ability, and h is set as follows:
- k 2 /n 2 does not equal an integer, thereby resulting in deterioration of error correction capability.
- the present invention is directed to solve the problems pointed out above and an object is to provide a two stage coding method in which the above-described deterioration in a burst error correction ability is improved and a higher burst error correction ability than that of the prior art device is obtained.
- .Iadd.n 2 -k 1 .Iaddend. is produced by establishing a 1 at an arbitrary data number word, and establishing h 1 , h 2 , . . . , h n2-1 such that they become a repetition of a combination satisfying the condition that [k.sub. 2 /n 2 ] and [k 2 /n 2 ]+1 may be
- l 1 +l 2 n 2 (l 1 , 1 2 : integer) and a 2 to a n2 exceeding n 2 ⁇ k 2 are obtained by subtracting n 2 ⁇ k 2 therefrom) for a 2 to a n2 as in the following: ##EQU4## when numbering is conducted successively in the first direction on the data of n 2 words in the first direction and k 2 words in the second direction, and this is repeated k 2 words in the second direction, and thereafter C 1 encoding of each n 2 ⁇ q digits in the first direction .[.into a.]..Iadd., forming an C 1 C 2 encoded data matrix having a total .Iaddend.code length n 1 is conducted.
- C 2 codes are constructed to be effective for error correction at the portion of n 2 -k 1 in the first direction and at the portion of k 2 in the second direction against the data obtained by arranging k 1 digits in the first direction and k 2 digits in the second direction, as shown in FIG. 1.
- FIG. 1 is a diagram showing a data arrangement for conducting a C 2 encoding method as one embodiment of the present invention
- FIG. 2 is a diagram showing a data arrangement for conducting a prior art two stage coding method and a C 1 encoding method as an embodiment of the present invention
- FIG. 3 is a block diagram showing a two stage encoding circuit
- FIG. 4 is a block diagram showing a two stage decoding circuit
- FIG. 5 is a diagram showing a data arrangement for conducting the C 2 encoding method of the prior art two stage coding method.
- a 2 to a 36 become ##EQU5## and, C 2 encoding is performed on the data corresponding to the a 1 -th, a 2 -th, . . . , and a 32 -th data with the use of the generation polynomial of the C 2 code ##EQU6##
- ⁇ is a root of a primary polynomial.
- the generated check codes are arranged at the positions corresponding to the a 33 -th, a 34 -th, . . . , a 36 -th data.
- a 1 is set as follows
- C 1 encoding is performed on the data of n 2 words in each column arranged in the first direction as shown in FIG. 2 with the use of the generation polynomial of C 1 code ##EQU7##
- the generated check codes are added to the data, and the encoding is repeated k 2 times.
- the data format reproduction is conducted by arranging the sent out data by 40 words successively in a column in the first direction.
- the C 2 code is concerned with burst error correction ability and both C 1 and C 2 codes are concerned with random error correction ability.
- C 2 codes of n 2 -k 1 in the first direction and k 2 in the second direction can be used effectively for the error correction of the data arranged in a matrix of k 1 in the first direction and k 2 in the second direction.
- h A , h B a repetition pattern of (h A , h B ) is adopted for h 1 , h 2 , . . . , h n2-1 , but other combinations using h A and h B such as (h B , h A ) or (h A , h B , h B ) can be used if they comply with the following conditions
- an RS code on GF (2 q ) is used as an error correction code, but another code such as a BCH code can be used as an error correction code.
- the number of data, the construction of information lengths in the first and second directions, and the C 2 and C 1 code lengths can be arbitrarily established.
- the region occupied by the check codes of the C 2 code and the C 1 code is shown in FIG. 2, but this occupied region can be arbitrarily established by establishing a 1 at an arbitrary number.
- the present invention is applicable not only to a magnetic disk apparatus but also to an optical recording and reproducing apparatus, and an optical magnetic recording and reproducing apparatus.
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Abstract
Errors which arise in recording and reproducing data in a recording material are corrected with the use of an error correction code such as an RS (Reed-Solomon) code, and a two stage C2 and C1 coding method is conducted at an interval of repetition of a combination of [k2 /n2 ] and [k2 /n2 ]+1 on digital data having a two dimensional arrangement of k1 in the first direction and k2 in the second direction, whereby burst error correction ability is enhanced by the enhancement of error correction capacity.
Description
The present invention relates to a two stage coding method having a high burst error correction ability and also a random error correction ability equivalent to that of the prior art when an error correction code such as a Reed Solomon code (hereinafter referred to as "RS code") is used in order to correct data errors which arise in reproducing data recorded in a recording material such as a magnetic disk.
Generally, in recording and reproducing data into and from a recording material such as a magnetic disk a data error may arise dependent on the state of the recording material. A data error may be a burst error caused by a signal drop out .[.on.]. .Iadd.or .Iaddend.a random error caused by a deterioration in SN ratio. In order to correct these errors a two stage coded error correction code is used. As an example, a two stage code using RS codes on a GF .[.(28).]. (.Iadd.2q) .Iaddend.where q=8 will be considered. A two stage encoder is shown in FIG. 3. In FIG. 3, reference numeral 1 designates an input terminal, reference numeral 2 designates a C2 encoder, reference numeral 3 designates an interleaving circuit, reference numeral 4 designates a C1 encoder, the reference numeral 5 designates an output terminal. First of all, C2 encoding is performed on the original data, interleaving is executed thereto, and thereafter C1 encoding is conducted, and the resulting code signal is output to the output terminal. A two stage decoder is shown in FIG. 4. In FIG. 4, reference numeral 6 designates an input terminal, reference numeral 7 designates a C1 decoder, reference numeral 8 designates a deinterleaving circuit, reference numeral 9 designates a C2 decoder, and reference numeral 10 designates an output terminal. In this decoder deinterleaving is executed after the C1 decoding, and thereafter C2 decoding is conducted. There is a prior art two stage coding method which, assuming that data obtained by arranging .[.k1 ×9.]. .Iadd.k1 ×q .Iaddend.digits in a first direction and k2 digits (k1 <k2) in a second direction as shown in FIG. 5 is arranged into 8 .[.data.]. .Iadd.digit .Iaddend.words in the first direction, consists of adding a first check code of n2 -k1 digits, and thereafter adding a second check code of n1 -n2 digits as shown in FIG. 2, (n2, k1) RS code is used as the C2 code, and (n1, n2) RS code is used as the C1 code.
A specific coding example will be described with reference to FIGS. 5 and 2. When it is established that k1 =32, k2 =128, n1 =40, n2 =36, and h1 =h2 = . . . =h35 =h=3, the data region comprising the data and the first check code becomes data of n2 ×k2 =4608 digits as shown in FIG. 5, and when a1 is set to 1, a2 to a36 become as follows: ##EQU1## and C2 encoding is conducted on the data corresponding to the a1 -th, a2 -th, . . . , a32 -th data .Iadd.selected .Iaddend.with use of the following generation polynomial of C2 code ##EQU2## where α is a root of a primary polynomial (for example, such as x8 +x4 +x3 +x2 +1 on GF (28)). The generated check codes are arranged at the positions corresponding to the a33 -th, a34 -th, . . . , a36 -th data. Next, a1 is set as follows:
a.sub.1 =a.sub.1 +n.sub.2 =a.sub.1 +36,
and similarly check codes are added to the data successively. Herein, if the calculated result of a2 to a36 exceeds n2 ×k2 =4608, a number obtained by subtracting 4608 therefrom is made the result. The encoding is repeated k2 times thereby to conclude the C2 encoding.
Next, C1 encoding is conducted on the data of n2 digits in each column arranged in the first direction as shown in FIG. 2 with the use of the following generation polynomial of C1 code ##EQU3## The generated check code is added to the end portion of the data and the encoding is repeated k2 times. In the recording of the data onto the recording material data of n1 =40 digits arranged in the first direction is sent out k2 times successively. In the reproduction of the same the sent out data are arranged in a column in the first direction by 40 digits successively.
In the prior art two stage coding method with such a construction, the C2 code is concerned with burst error correction ability, and the C1 and C2 codes are concerned with random error correction ability. In the stage of conducting C2 encoding the h must be made large in order to enhance the burst error correction ability, and h is set as follows:
h=[k.sub.2 /n.sub.2 ]=[128/36]=3
.Iadd.where [A] denotes an integer which does not exceed A .Iaddend.The C2 codes are gathered at the right end portion of the data region in FIG. 5, and the C2 and the C1 code are arranged adjacent to each other in the first direction subsequent to the data of k1 =32 digits when the C1 encoding is completed.
The prior art two stage coding method is constructed in such a manner, and the error correction ability by one code amounts to n2 -k1 digits when forfeiture correction is conducted by the C2 decoding. Accordingly, the burst error correction ability becomes as follows for data of n2 ×k2 =4608 digits comprising all the data and the C2 code
(n.sub.2 -k.sub.1)×n.sub.2 ×h=432,
but h becomes as follows:
h=[k.sub.2 /n.sub.2 ]=[128/36]=3<128/36,
and k2 /n2 does not equal an integer, thereby resulting in deterioration of error correction capability.
The present invention is directed to solve the problems pointed out above and an object is to provide a two stage coding method in which the above-described deterioration in a burst error correction ability is improved and a higher burst error correction ability than that of the prior art device is obtained.
According to the coding method of the present invention, assuming that data of k1 ×8×k2 digits are arranged in a matrix of k1 ×8 digits in a first direction and k2 digits(s) in a second direction and the data is divided into words of 8 digit(s) in the first direction, in conducting C2 encoding by taking out n2 data words from the data of .[.n2 .]. .Iadd.n2 -k1 .Iaddend.words in the first direction and k2 words in the second direction with no duplication of data in either of the first and second directions, a C2 code of .[.code.]. length .[.n2 .]. .Iadd.n2 -k1 .Iaddend.is produced by establishing a1 at an arbitrary data number word, and establishing h1, h2, . . . , hn2-1 such that they become a repetition of a combination satisfying the condition that [k.sub. 2 /n2 ] and [k2 /n2 ]+1 may be
[k.sub.2 /n.sub.2 ]×1.sub.1 +([k.sub.2 /n.sub.2 ]+1)×1.sub.2 ≦k.sub.2
(herein, l1 +l2 =n2 (l1, 12 : integer) and a2 to an2 exceeding n2 ×k2 are obtained by subtracting n2 ×k2 therefrom) for a2 to an2 as in the following: ##EQU4## when numbering is conducted successively in the first direction on the data of n2 words in the first direction and k2 words in the second direction, and this is repeated k2 words in the second direction, and thereafter C1 encoding of each n2 ×q digits in the first direction .[.into a.]..Iadd., forming an C1 C2 encoded data matrix having a total .Iaddend.code length n1 is conducted.
In the two stage coding method of the present invention, C2 codes are constructed to be effective for error correction at the portion of n2 -k1 in the first direction and at the portion of k2 in the second direction against the data obtained by arranging k1 digits in the first direction and k2 digits in the second direction, as shown in FIG. 1. According to the present invention, the burst error correction ability against the data of n2 ×k2 =4608 digits comprising all the data, and the C2 codes becomes
(n.sub.2 -k.sub.1)×n.sub.2 ×(h.sub.4 +h.sub.B)/2=504.
and this exceeds 432 which is the burst error correction ability of the prior art device against the same number of data and the same number of check codes.
In this way, it is possible to conduct a two stage coding having a higher burst error correction ability than that of the prior art, and having a random error correction ability equivalent to that of the prior art due to the C1 and C2 codes.
FIG. 1 is a diagram showing a data arrangement for conducting a C2 encoding method as one embodiment of the present invention;
FIG. 2 is a diagram showing a data arrangement for conducting a prior art two stage coding method and a C1 encoding method as an embodiment of the present invention;
FIG. 3 is a block diagram showing a two stage encoding circuit;
FIG. 4 is a block diagram showing a two stage decoding circuit; and
FIG. 5 is a diagram showing a data arrangement for conducting the C2 encoding method of the prior art two stage coding method.
Embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 and 2, the constants are established that q=8, k1 =32, k2 =128, n1 =40, n2 =36, and data are divided into words of 8 digits in the first direction. FIG. 1 shows a C2 encoding method. Data of k1 ×k2 =4096 data words are arranged sequentially in the first direction and in a matrix of k1 =32 words in the first direction and k2 =128 words in the second direction, and when h2i-1 and h2i are set as follows
h.sub.2i-1 =h.sub.A =]k.sub.2 /n.sub.2 ]=3
h.sub.2i =h.sub.B =[k.sub.2 /n.sub.2 ]+1=4,
(i: integer, 1≦i≦(n2 -1)/2)
and a1 is set 1, a2 to a36 become ##EQU5## and, C2 encoding is performed on the data corresponding to the a1 -th, a2 -th, . . . , and a32 -th data with the use of the generation polynomial of the C2 code ##EQU6## Herein, α is a root of a primary polynomial. The generated check codes are arranged at the positions corresponding to the a33 -th, a34 -th, . . . , a36 -th data. Next, a1 is set as follows
a.sub.1 =a.sub.1 +n.sub.2 =a.sub.1 +36
and similarly inspection codes are added to the data successively. a2 to a36 exceeding n2 ×k2 =4608 are made by subtracting 4608 therefrom. When this encoding operation is repeated k2 times the C2 encoding is completed.
Next, C1 encoding is performed on the data of n2 words in each column arranged in the first direction as shown in FIG. 2 with the use of the generation polynomial of C1 code ##EQU7## The generated check codes are added to the data, and the encoding is repeated k2 times. The recording of the data on a recording material is conducted by sending out data of n1 =40 words arranged in the first direction successively k2 times. The data format reproduction is conducted by arranging the sent out data by 40 words successively in a column in the first direction.
In the two stage coding method of the present invention, the C2 code is concerned with burst error correction ability and both C1 and C2 codes are concerned with random error correction ability. In conducting the C2 encoding, C2 codes of n2 -k1 in the first direction and k2 in the second direction can be used effectively for the error correction of the data arranged in a matrix of k1 in the first direction and k2 in the second direction.
In the above-illustrated embodiment a repetition pattern of (hA, hB) is adopted for h1, h2, . . . , hn2-1, but other combinations using hA and hB such as (hB, hA) or (hA, hB, hB) can be used if they comply with the following conditions
h.sub.A ×l.sub.1 +h.sub.B ×l.sub.2 ≦k.sub.2
l.sub.1 +l.sub.2 =n.sub.2
Furthermore, an RS code on GF (2q) is used as an error correction code, but another code such as a BCH code can be used as an error correction code. Furthermore, the number of data, the construction of information lengths in the first and second directions, and the C2 and C1 code lengths can be arbitrarily established. Furthermore, in the illustrated embodiment the region occupied by the check codes of the C2 code and the C1 code is shown in FIG. 2, but this occupied region can be arbitrarily established by establishing a1 at an arbitrary number.
Furthermore, it is possible to add the additional information of k3 ×q digits in the second direction k2 times precedent to the C1 encoding, and thereafter to conduct C1 encoding on GF (2q) having the (n1 +k3)×q digits in the first direction, and to conduct a coding k2 times repeatedly in the second direction.
The present invention is applicable not only to a magnetic disk apparatus but also to an optical recording and reproducing apparatus, and an optical magnetic recording and reproducing apparatus.
Claims (4)
1. A two stage coding system for encoding digital information arranged in a matrix of k1 ×q digits in a first direction, and k2 digits in a second direction orthogonal to the first direction, wherein
K1, q, and k2 are integers,
K1 <k2 ; q=the number of digits per data word, and
K1, K2 =the number of data words in said first and second directions respectively, comprising:
C2 encoder means for encoding said digital information with a C2 code on a Galois Field GF (2q), including means for .[.numbering.]. .Iadd.selecting .Iaddend.data words in said matrix diagonally from an arbitrary data word a1 and establishing a2 to an2, wherein n2 is the length of .[.code.]. .Iadd.the .Iaddend.C2 encoded data, such that ##EQU8## wherein h1 to hn2-1 satisfy the following
h.sub.2i-1 =[K.sub.2 /n.sub.2 ]
h.sub.2i =[k.sub.2 /n.sub.2 ]+1 1≦i≦(n.sub.2 -1)/.Badd.2
.Iadd.said C2 encode means including .Iaddend.means for C2 encoding said .[.numbered.]. .Iadd.selected .Iaddend.data words, and means for adding the obtained C2 code to an end of said matrix in said first direction; and
C1 encoder means for encoding said C2 encoded matrix with a C1 code having a .Iadd.predetermined .Iaddend.length .[.of n1 .]. on a GF (2q) for each row of data words in said first direction, and adding the obtained C1 code to an end of said matrix in said first direction. .Iadd.
2. The two stage coding system of claim 1 wherein said means for C2 encoding further encodes said selected data words in each said diagonal;
said means for adding a C2 code to the end of each said diagonal to form a C2 code field at the end of said matrix in said first direction. .Iaddend. .Iadd.3. The two stage coding system of claim 2 wherein said C2 encoder means subtracts n2 ×k2 from any initially calculated value of a2 to an2 that exceed n2 ×k2 to select data words in said matrix diagonally. .Iaddend. .Iadd.4. The two stage coding system of claim 1 wherein said C2 encoder means subtracts n2 ×k2 from any initially calculated value of a2 to an2 that exceed n2 ×k2 to select data words in said matrix diagonally. .Iaddend. .Iadd.5. The two stage coding system of claim 1 wherein additional data added to said rows of data words in said first direction prior to encoding of said C2 encoded matrix with a C1 code is also encoded with this C1 code by said C1 encoder means. .Iaddend. .Iadd.6. A two stage coding system for encoding digital information arranged in an information matrix of k1 ×q digits in a first direction, and k2 digits in a second direction orthogonal to the first direction, wherein
k1, q, and k2 are integers,
k1 <k2 ; q=the number of digits per data word, and
k1, k2 =the number of data words in said first and second directions respectively, comprising:
C2 encoder means for encoding said digital information with a C2 code on a Galois field GF(22), said C2 encoder means selecting data words in said information matrix diagonally from an arbitrary data word a1 and including a2 to an2, wherein n2 is the length of the C2 encoded data, such that
a.sub.2 =a.sub.1 +n.sub.2 ×h.sub.1 +1
a.sub.3 =a.sub.2 +n.sub.2 ×h.sub.2 +1
:
a.sub.k1 =a.sub.k1-1 +n.sub.2 ×h.sub.k1-1 +1
:
a.sub.n2 =a.sub.n2-1 +n.sub.2 ×h.sub.n2-1 +1,
h1 to h2n-1 each being selected from one of hA and hB, wherein,
h.sub.A =[k.sub.2 /n.sub.2 ],
h.sub.B =[k.sub.2 /n.sub.2 ]+1, and
h.sub.A ×l.sub.1 +h.sub.B ×l.sub.2 ≦k.sub.2, where
l.sub.1 +l.sub.2 =n.sub.2
said C2 encoder means forming said C2 code from said selected data words and adding the obtained C2 code to an end of said information matrix in said first direction thereby forming a C2 encoded matrix; and
C1 encoder means for encoding each line in said first direction of said C2 encoded matrix with a C1 code having a predetermined length on a GF(2q), and adding the obtained C1 code to an end of each said line of said matrix in said first direction to form a C2
C1 encoded matrix. .Iaddend. .Iadd.7. The two stage coding system of claim 6 wherein a group of two or more adjacent lines h1, h2, . . . utilize a repetition pattern having at least one of each of hA and hB contained therein, said selection of data words a1 to an by said C2 encoder means utilizing said repetition pattern for selection of all said data words (a) in said information matrix. .Iaddend. .Iadd.8. The two stage coding system of claim 7 wherein said repetition pattern is selected from the group consisting of hA, hB ; hB, hA ; and hA, hB, hB. .Iaddend. .Iadd.9. The two stage coding system of claim 6 wherein:
h.sub.2i-1 =h.sub.A,
h.sub.2i =h.sub.B,
where 1<i<(n2 -1)/2. .Iaddend. .Iadd.10. The two stage coding system of claim 6 wherein:
h.sub.2i-1 =h.sub.B,
h.sub.2i =h.sub.A,
where 1<i<(n2 -1)/2. .Iaddend. .Iadd.11. The two stage coding system of claim 6 wherein said C2 encoder means repeatedly selects data words in said information matrix from an arbitrary data word a1 and including a2 to an2, said C2 encoder means repeatedly forming said C2 code and adding said C2 to the end of the matrix, each repetition starting from a different arbitrary data word a1. .Iaddend. .Iadd.12. The two stage coding system of claim 11 wherein said C2 encoder means selects k2 arbitrary data words from which to perform selecting, forming and adding to thereby form a complete C2 encoded matrix. .Iaddend. .Iadd.13. The two stage coding system of claim 6 wherein said means for C2 encoding further encodes said selected data words in each said diagonal;
said means for adding a C2 code to the end of each said diagonal to form a C2 code field at the end of said information matrix in said first direction. .Iaddend. .Iadd.14. The two stage coding system of claim 6 wherein additional data added to said rows of data words in said first direction prior to encoding of said C2 encoded matrix with a C1 code is also encoded with this C1 code by said C1 encoder means to thereby form said C2 C1 encoded matrix. .Iaddend. .Iadd.15. The two stage coding system of claim 14 wherein the length of said C2 C1 encoded data matrix in the first direction is (n1 +k3)×q digits, where k3 is an integer. .Iaddend. .Iadd.16. The two stage coding system of claim 6 wherein said C2 encoder means subtracts n2 ×k2 from any initially calculated value of a2 to an2 that exceed n2 ×k2 to select data words in said matrix diagonally. .Iaddend. .Iadd.17. The two stage coding system of claim 6 wherein the length of said C2 C1 encoded data matrix in the first direction is n1 ×q digits. .Iaddend. .Iadd.18. A two stage coding system for encoding digital information arranged in an information matrix of k1 ×q digits in a first direction, and k2 digits in a second direction orthogonal to the first direction, wherein
k1, q, and k2 are integers,
k1 <kq ; q=the number of digits per data word, and
k1, k2 =the number of data words in said first and second directions respectively,
said system further single stage coding additional information of k3 ×q digits in the first direction, where k3 is an integer and k2 digits in the second direction, comprising:
C2 encoder means for encoding said digital information with a C2 code on a Galois field GF(2q), said C2 encoder means selecting data words in said information matrix diagonally from an arbitrary data word a1 and including a2 to an2, wherein n2 is the length of the C2 encoded data, such that
a.sub.2 =a.sub.1 +n.sub.2 ×h.sub.1 +1
a.sub.3 =a.sub.2 +n.sub.2 ×h.sub.2 +1
:
a.sub.k1 =a.sub.k1-1 +n.sub.2 ×h.sub.k1-1 +1
:
a.sub.n2 =a.sub.n2-1 +n.sub.2 ×h.sub.n2-1 +1
h1 to hn2-1 each being selected from one of hA and hB, wherein,
h.sub.A =[k.sub.2 /n.sub.2 ],
h.sub.B =[k.sub.2 /n.sub.2 ]+1, and
h.sub.A ×l.sub.1 +h.sub.B ×l.sub.2 ≦k.sub.2, where
l.sub.1 +l.sub.2 =n.sub.2
said C2 encoder means forming said C2 code from said selected data words and adding the obtained C2 code to an end of said information matrix in said first direction to form a C2 encoded matrix; and
said additional data of k3 words and said C2 encoded matrix collectively forming an added data matrix having k2 lines;
C1 encoder means for encoding each of said k2 lines extending in said first direction of said added data matrix with a C1 code having a predetermined length on a GF(2q), and adding the obtained C1 code to an end of each said line of said added data matrix in said first
direction to form a C2 C1 encoded matrix. .Iaddend. .Iadd.19. The two stage coding system of claim 18 wherein a group of two or more adjacent lines h1, h2, . . . utilize a repetition pattern having at least one of each of hA and hB contained therein, said selection of data words a1 to an by said C2 encoder means utilizing said repetition pattern for selection of all said data words (a) in said information matrix. .Iaddend. .Iadd.20. The two stage coding system of claim 19 wherein said repetition pattern is selected from the group consisting of hA, hB ; hB, hA ; and hA, hB, hB. .Iaddend. .Iadd.21. The two stage coding system of claim 18 wherein:
h.sub.2i-1 =h.sub.A,
h.sub.2i =h.sub.B,
where 1<i<(n2 -1)/2. .Iaddend. .Iadd.22. The two stage coding system of claim 18 wherein:
h.sub.2i-1 =h.sub.B,
h.sub.2i =h.sub.A,
where 1<i<(n2 -1)/2. .Iaddend. .Iadd.23. The two stage coding system of claim 18 wherein said C2 encoder means repeatedly selects data words in said information matrix from an arbitrary data word a1 and including a2 to an2, said C2 encoder means repeatedly forming said C2 code and adding said C2 to the end of the matrix, each repetition starting from a different arbitrary data word a1. .Iaddend. .Iadd.24. The two stage coding system of claim 23 wherein said C2 encoder means selects k2 arbitrary data words from which to perform selecting, forming and adding to thereby form a complete C2 encoded matrix. .Iaddend. .Iadd.25. The two stage coding system of claim 18 wherein said means for C2 encoding further encodes said selected data words in each said diagonal;
said means for adding a C2 code to the end of each said diagonal to form a C2 code field at the end of said information matrix in said first direction. .Iaddend. .Iadd.26. The two stage coding system of claim 18 wherein said C2 encoder means subtracts n2 ×k2 from any initially calculated value of a2 to an2 that exceed n2 ×k2 to select data words in said information matrix diagonally. .Iaddend. .Iadd.27. The two stage coding system of claim 18 wherein the length of said C2 C1 encoded matrix in the first direction is (n1 +k3)×q digits. .Iaddend.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59-280163 | 1984-12-26 | ||
JP59280163A JPS61154227A (en) | 1984-12-26 | 1984-12-26 | Two-stage coding method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06905313 Reissue | 1985-12-19 |
Publications (1)
Publication Number | Publication Date |
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USRE34245E true USRE34245E (en) | 1993-05-11 |
Family
ID=17621187
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/905,313 Ceased US4769819A (en) | 1984-12-26 | 1985-12-19 | Two stage coding method |
US07/578,178 Expired - Lifetime USRE34245E (en) | 1984-12-26 | 1990-09-06 | Two stage coding method |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/905,313 Ceased US4769819A (en) | 1984-12-26 | 1985-12-19 | Two stage coding method |
Country Status (5)
Country | Link |
---|---|
US (2) | US4769819A (en) |
JP (1) | JPS61154227A (en) |
DE (2) | DE3590661T (en) |
GB (1) | GB2180966B (en) |
WO (1) | WO1986003911A1 (en) |
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Also Published As
Publication number | Publication date |
---|---|
JPS61154227A (en) | 1986-07-12 |
DE3590661C2 (en) | 1989-09-14 |
GB2180966A (en) | 1987-04-08 |
US4769819A (en) | 1988-09-06 |
WO1986003911A1 (en) | 1986-07-03 |
JPH0152940B2 (en) | 1989-11-10 |
DE3590661T (en) | 1987-02-19 |
GB8619805D0 (en) | 1986-09-24 |
GB2180966B (en) | 1988-09-14 |
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