USRE27394E - Closed loop logic gate multiple phase clock signal generator - Google Patents

Abstract

OUTPUT SIGNALS FROM THE LOGIC GATES OF AN OSCILLATOR CIRCUIT REPRESENT SEQUENTIAL DIGITAL STATES (STAGES). OUTPUT SIGNALS HAVING CERTAIN RELATED INTERVALS ARE COMBINED AS INPUT TO THE LOGIC GATES TO PRODUCE MULTIPLE PHASE CLOCK SIGNALS HAVING A DESIRED SYMMETRY AND RELATIONSHIP WITHOUT THE NECESSITY FOR DECODE LOGIC AT THE OUTPUT OF THE OSCILLATOR.

Description

June 20, 1972 G. L. HEIMBIGNER 27,394

CLOSED LOOP LOGIC GATE MULTIPLE PHASE CLOCK SIGNAL GENERATOR Original Filed Dec. 30, 1968 2 Sheets-Sheet l FIG. I

INVENTOR GARY L HEIMBIGNER BYQMJ. PW

ATTORNEY June 20, 1972 G. L. HEIMBIGNER 27394 CLOSED LOOP LOGIC GATE MULTIPLE PHASE CLOCK SIGNAL GENERATOR Original Filed Dec. C50, 1968 2 Sheets-Sheet 2 Ql 35 5K FIG.2

INVENTOR GARY L. HEIMBIGNER ATTORNEY 27,394 CLOSED LOOP LOGIC GATE MULTIPLE PHASE CLOCK SIGNAL GENERATOR Gary L. Heimbigner, Anaheim, Calif., assignor to North American Rockwell Corporation Original No. 3,539,938, dated Nov. 10, 1970, Ser. No. 787,719, Dec. 30, 1968. Application for reissue May 27, 1971, Ser. No. 147,556

Int. Cl. H03k 3/02 US. Cl. 331-57 10 Claims Matter enclosed in heavy brackets [II appears in the original patent but forms no part of this reissue specification; matter printed in italics indicates the additions made by reissue.

ABSTRACT OF THE DISCLOSURE Output signals from the logic gates of an oscillator circuit represent sequential digital states [stagtes]. Output signals having certain related intervals are combined as inputs to the logic gates to produce multiple phase clock signals having a desired symmetry and relationship without the necessity for decode logic at the output of the oscillator.

BACKGROUND OF THE INVENTION Field of the invention The invention relates to a multiple phase clock signal generator and more particularly to such a generator in which certain signals of the generator are selectively combined within the generator to produce the multiple phase clock signals without the necessity for decode logic.

Description of prior art true intervals which overlap symmetrically.

While a counter with decode logic provides usable clock signals, such a system requires more logic gates than necessary and, therefore, utilizes more space and consumes more power than would be preferred. In a preferred system, the outputs of gates used in generating signals representing sequential and recurring logic states would be used to produce the desired clock signals without the necessity for decode logic. The number of gates, including their inputs and output connections, would be a function of the type of clock signals required.

SUMMARY OF THE INVENTION Briefly, the invention comprises a multiphase clock generator having a plurality of logic gates forming an oscillator for generating signals each of which has sequential and recurring intervals representing true and false logic states. The corresponding logic states of each signal have different beginning and ending phase times. The outputs of certain of the logic gates are connected as inputs United States Patent ice to others of the logic gates for controlling the phase spacing and overlap between the signals.

Therefore, it is an object of this invention to provide an improved multi-phase clock signal generator.

It is another object of this invention is produce clock signals directly from logic gates forming an oscillator without the necessity for decode logic.

Another object of the invention is to generate clock signals having a predetermined phase relationship and symmetry directly from gates of an oscillator which are gated by signals generated within said oscillator.

It is still another object of this invention to provide a number of gates interconnected to form an oscillator as a function of required output signals from said gates.

Still another object of this invention is to provide multiple phase clock signals directly from an oscillator circuit having the required phase spacing and overlap.

These and other objects will become more apparent when taken in connection with the description of drawings, a brief description of which follows.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 represents one embodiment of a clock signal generator for producing clock signals having a phase separation of one bit time, a true interval of three bit times, and an overlapping interval of one bit time.

FIG. 2 represents a second embodiment of a clock signal generator for producing clock signals having a phase separation of one bit time, a true interval of seven bit times, and an overlapping interval of three bit times.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 illustrates a simple embodiment of a closed loop logic gate multiple phase clock signal generator comprising NOR gates A thru D and S for generating clock signals conforming to the following bit pattern and logic equation.

As indicated by the bit pattern, the output clock signal from NOR gate A has a true interval of three bit times and a false interval of five bit times. The A and C true intervals are separated by one bit time as are the B and D true intervals. The A & B, B & C, C & D, and D & A signals overlap by one bit time.

The S NOR gate is used to establish initial output conlitions on NOR gates B and C for generating the required it pattern. After the initial conditions are set, the gen- :rator runs freely as an oscillator.

In the usual case, prior to implementing a bit pattern generator, the required characteristics of a set of clock .ignals are determined. For example, the above bit patern and corresponding logic were developed for a twophase clocking scheme in which it was required that :ertain of the'signals have a one bit spacing. In order to )I'OVlClB signals having a one bit spacing, it was necessary lS shown, to reduce the ON interval, or true time of he signals by one bit. As a result, the clock signals are )n for three bit times and off for five bit times.

Generally, multiphase clock signals used in gating nultiphase logic should have a phase relationship includng an isolation or separation period to prevent race :onditions from occurring. If an isolation interval is not arovided, it would be possible to gate information through I combination of gates without the required delay. In )ther words, information may arrive at an output terminal :rom multiphase logic gates prior to the time it is reuired. As a result, errors could occur.

The phase relationship between signals should also proride for an overlap between adjacent phases of the clock :ignals so that capacitors comprising a logic circuit can Je properly charged and discharged at a relatively high ate of speed. Without the overlap, time would be lost aetween the true time of one clock signal and the true i'me of an adjacent clock signal used in gating the same .ogic circuit. Charge splitting is also prevented by using iverlapped clock signals. The overlap period is determined aomewhat by the characteristics of the circuit being gated. [11 some circuits, a large overlap is required; while in )thers, a small overlap is acceptable. [Obviously, the :lock signals should have symmetrical true intervals and symmetrical false intervals] After the number of clock signals and their logical re- .ationship have been determined, gates for implementing die logic can be produced and interconnected as required. The resulting combination of gates produces an oscillator :ircuit which generates signals corresponding to a bit pattern as a function of the requirements of the output clock signals.

As shown in FIG. 1, four NOR gates (plus a starting NOR gate) are required to implement the logic and bit pattern shown in Table I. The output signals from each of the gates have sequential intervals representing two logical states (true and false) represented by the ones and zeros shown. Corresponding logic states of each output signal have different beginning and ending phase times although the intervals of the corresponding logic states are equal.

The phase relationship (spacing and overlap) of the output signals is determined by the input signals. For example, since the output from NOR gate A goes true one bit time after the outputs from NOR gates C and B are both false, those output signals can be used to drive the A NOR gate output true. One bit after the C and B outputs are no longer both false, the A gate is driven false. Similarly, since the B gate goes true one bit time after both the D and C outputs are false, those outputs can be used to drive NOR gate B true. NOR gate B remains true until both of the signals are not false, i.e., three bit times later. Other relationships should be obvious from the logic and bit pattern shown in Table I.

The FIG. 1 scheme could be used for a 4 scheme, although it would not be as useful because of the small overlap between signals.

A more practical multiphase clock signal generator, useful for high speed gating, is shown in FIG. 2. The bit pattern produced by the FIG. 2 embodiment is set forth below as is the logic implemented by the NOR gates identified as 1, 1 C1 1, 1 9 12 2a fist and 41- TABLE II Mi 1 (ps4 1 1m A1 TABLE II on C1 4m B1 4% 1 4 12 HHCQQOQQQOQHHHHH HHHHOQQQOOQOGHHH HHHHHHOOOOOOOOOH HHHHl-HHDOOOQQQO OOOHi-H-ur-HHOOOCOQ QOOOOHHHPHHHQOCO OOOOOOOHHHHHb-H-OQ ocoeccooct-u-u-u-n-n-u- As indicated above, the phase separation between clock signals and and between and p is one bit time. The ON or true interval of each clock signal is seven bit times and the overlap period between clock signals p 4 and 5 is three bit times. The subscripts are intended to represent adjacent intervals during which the output clock signals from the gates are true. 'For example, 15 represents a signal that is true during 1 and 2 phase times. Therefore, a signal which is also true during 2 and 3 phase times will overlap the signal which is true during 1 and 2 phase time. Clock signals from the gates designated as A through D are necessary inputs to the other gates in order to generate output clock signals having the desired relationship, i.e., 1 bit separation and 3 bit overlap.

After the characteristics of required clock signals have been determined, as described in the previous paragraph, it may be necessary to add gates to the gates which pro duce the necessary clock signals in order to implement a generator having a capability for producing signals having a necessary bit pattern relationship. Gates represented A through D were added to produce the required bit configuration for generating clock signals 5 m For example, 4: and 11 have true periods which are separated by one bit. In order to produce the required bit separation, it was necessary that the clock signals have a bit pattern difference of two bits. In other words, 4: and A have logical intervals which have a phase displacement of two logic states. By inspecting the bit pattern, it can be seen that 5 becomes true one interval (bit time) and p and B are false and that it remains true for one interval after B becomes true. Therefore, e and B can be used as inputs to the gate to produce a signal which becomes false one bit before (p goes true for producing the required isolation. That is, when both inputs to [NO] NOR gate are false, one bit time later the output of goes true and remains true until both inputs are not false. When that occurs, the output goes false.

The output from the S gate is necessary to establish initial conditions for the clock generator. Thereafter, the

generator produces signals which repersent a recurring bit pattern having a configuration as a function of the desired clock signals. The S gate receives inputs from gates qb A B and as shown.

6 OFF), thru overlap intervals between adjacent signals, and one interval of separation between alternate signals. Based on that information, a bit pattern for major clock signals would be derived afterwards and the number of Although NOR gates e through e5 were the neces- 5 additional gates generating signals having similar charsary gates for a particular gating system, it is possible to acteristics could be added to complete this bit pattern decode the bit pattern represented by the output signals for the generator. Although the invention has been deto produce, or generate, other clock signals. Examples scribed and illustrated in detail, it is to be understood of decode gates are represented by the 1: and 4: NOR that the same is by way of illustration and example only, gates. It should be pointed out, however that the major 10 and is not to be taken by way of limitation; the spirit and clock signals, e through 5 are produced without the scope of this invention being limited only by the terms necessity for decode logic. of the appended claims.

Although the FIG. 2 system is the preferred embodi- What is claimed is: ment since it is the most practical embodiment, oscillator 1. A closed loop logic gate multiple phase clock signal circuits generating signals representing additional patterns 15 generator comprising two two-input logic gates and three may also be implemented. However, using the method dethree-input logic gates, scribed in connection with FIGS. 1 and 2 for overlaps in a first of said two-input logic gates providing inputs to excess of three, the system becomes impractical to prothe second of said two-input logic gates, to a first duce. An example of bit patterns produced by a genand a second of said three-input logic gates. erator having four major gates (m 5 5 4 said second two-input logic gate providing inputs to with an 0N" time of 11 intervals and a bit time separasaid second and a third of said three-input logic tion of one bit is shown by the following table and logic. gates,

Decode logic for the clock signals designated as minors said first three-input logic gate providing inputs to said (rp rp is also .shown. second and third three-input logic gates,

TABLE III Hh G; 1541M Fr e IHM Dd e dmM Bb A. 12M

dmvr= m I 34M+EO+ I B =EB+Fr+SI 2sM=Fr+41M+SI c=4lM+GJ+Sn Da=G.v+ b+S. a4M=Hh+i2M+S| B IZM+A Fi=An+Bh nM= b+2sM J=23M+ u h= e+ d w onoccocosoo oiw HHHI-II-IHQOOQQOOQOOOQQHHHHH HHHHHHI-HOOQQQQQQDQQQOHHH Hn-u-n-u-n-n pn-uoo occo QHHHHHHHHHHHQQQOQOOOQOOO QOQHHHFHHHI-HHHQOOCOQQQQO OOOOOHHI-Hp-AHH FCQO Q GOOOQOHb- HHH HH HQ O QQ QOOOQOQQQHHHHHHHHHHHOQOU As indicated above, as the periods of overlap increase, the number of gates required to implement a clock generator also increases. For example, excluding the S gate, for an overlap of three hits, as shown in FIG. 2, eight gates were required. However, for an overlap of .five bits, as shown in the above table, 12 gates were required. For an overlap of seven bits, 16 gates would be required. Obviously, therefore, as the requirements for overlap between signals increase, the number of gates also increases to the point where a system is impractical to produce.

In all the cases described, and in other cases, the multiphase clock generator conforms to the following equations: 4n=number of gates required (excluding S gate); Sn=number of oscillator states; I 4n-1=number of states in ON period; 2n-l=number of states of overlap between adjacent signals;

L=number of states of isolation between [alttrnate] alternate signals;

2n-l=number of states in a minor phase (if decoded);

where n=any positive integer.

As indicated above, when n=2, eight gates are required with sixteen logic states (seven ON" and nine QUQODOODOQOMHHHHHHHHHHQQ said second three-input logic gate providing inputs to said first and third three-input logic gates and to said first two-input logic gate,

said third three-input logic gate providing inputs to said first and second two-input logic gates, and to said first three-input logic gate.

2. The closed loop gate multiple phase clock signal generator recited in claim 1 wherein said first three-input logic gate receives said inputs and provides an output for establishing initial operating conditions of said clock generator. I

[3. A closed loop logic gate multiple phase clock signal generator comprising:

five two-input logic gates, three three-input logic gates and one five-input logic gate,

said second three-point-logic gate providing inputs to said five-input logic gate, a first of said three-input logic gates, and a second of said two-input logic gates,

said second of said two-input logic gates providing inputs to a second of said three-input logic gates and to a third of said two-input logic gates,

said third of said two-input logic gates providing inputs to said five-input logic gate, to a fourth of said two-input logic gates and to a third three-input logic gate, said fourth of said two-input logic gates providing inputs to said third and fifth two-input logic gates,

said fifth two-input logic gate providing inputs to said first two-input logic gate, said third three-input logic gate, and to said five-input logic gate,

said first three-input logic gate providing inputs to said second three-input logic gate and to said fiveinput logic gate, said second three-input logic gate providing inputs to said second and fourth two-input logic gates and to said five-input logic gate,

said third three-input logic gate providing inputs to said fifth two-input logic gate and to said first threeinput logic gate,

said five-input logic gate providing inputs to said third three-input logic gate, said first two-input logic gate, said first three input logic gate, and said second threeinput logic gate.]

4. The closed loop logic gate multiple phase clock sigral generator recited in claim [3] where said five-input ogic gate receives said recited inputs and provides an out- It for establishing initial operating conditions of said :lock generator.

5. The closed loop logic gate multiple phase clock sig- 1al generator recited in claim 4 wherein said logic gates Lre NOR gates.

6. The closed loop logic gate multiple phase clock sigral generator recited in claim 4 wherein logic gates, ex- :luding the gate for establishing initial operating condiions, are added to increase the multiple phase clock sig- 1als generated by said clock generator, the inputs to said ive-input logic gate increasing as a function of the added ogic gates, said number of logic gates being 4n where n is any positive integer greater than one.

7. The closed loop logic gate multiple phase clock lignal generator recited in claim 6 wherein each gate, :xcluding the gate for establishing initial conditions, gen- :rates a multiple phase clock signal which is related to each other signal, with each adjacent signal having a ixed phase separation and with each alternate signal havng a fixed phase overlap equal to 2n1 phase intervals, where n is any positive integer greater than 1.

8. The closed loop logic gate multiple [phast] phase clock signal generator recited in claim 7 wherein each of said signals has a number of phase intervals equal to 8n where n is any positive integer greater than one, said phase intervals being divided between two logic levels with each signal remaining in a first logic level for a number of phase intervals equal to 4n-1, where n is any positive integer greater than one.

9. A closed loop logic gate multiple phase clock signal generator having a multiple input logic gate for establishing initial condition, said generator further including a plurality of multiple input logic gates 4n for generating multiple phase output signals each having 8n logic states, wherein each of said logic states comprises a first logic level and a second logic level with 4n1 logic states of each signal being at said first logic level,

certain of said plurality of said logic gates providing inputs to certain others of said plurality of logic gates until all logic gates are interconnected in a closed loop for providing a synchronized phase relationship between said multiple phase output signals, with output signals adjacent to each other in phase having a fixed phase separation and with the signals which are [alternatte] alternate to each other in phase having a phase overlap equal to 2n--1, and

third means comprising four two-input logic gates;

wherein said first means provides inputs to each of said second means, a first of said second means provides inputs to said first means and to a first and second of said third means, said first of said third means provides inputs to a second and third of said second means, said second of said third means provides inputs to said first and second of said second means, said second of said second means provides inputs to said first means to said first of said third means and to a third of said third means, said third of said second means provides inputs to said first means to said third of said third means and to a fourth of said second means, said third of said third means provides inputs to said first means to said third of said second means and to a fourth of said third means, said fourth of said second means provides inputs to said first m ans and to said second and fourth of said third means, and said fourth of said third means provides inputs to said first and fourth of said second means.

II. A closed loop logic gate multiple phase clock signal generator comprising:

a multiple input logic gate S for establishing initial conditions and 4n multiple input logic gates for generating multiple phase logic gating signals each having 8n combinational logic states, wherein 4n1 of said logic states comprise a first logic level and the remainder a second logic level, said 8n logic states of said logic gating signal comprised of a first series of said logic level states followed sequentially by a second series of said second logic level states, with each series of said first logic level states of a particular logic gating signal preceding the series of said first logic level states of a subsequent logic gating signal by two state times,

the output of a series of said first logic level states being generated in a subsequent logic gating signal one state time after said second logic level pervades a set comprising difierent ones of said logic gates, said set unique to said subsequent logic gate, with output signals adjacent to each other in phase having a fixed phase delay, said series of said first logic level states of each logic gate separated by one state time from the said series of said first logic level states of at least one other of said 4n logic gates, said series of said first logic level states of each logic gate overlapping by 2n.1 state times the said series of first logic level states of one other of said 4n logic gates,

said logic gates being connected such that excluding the S gate, for a kth gate of said 4n gates the inputs to said kth gate are from gates numbered 2n+k, 2n+k-1, and from S if k is between 2 and 2n+1 inclusive, with 4n being subtracted from said Zn-I-k or 2n+k-1 if said 2n+k or 2n-|k1 exceeds 4n, said S gate inputs being from gate numbers 1 to 2n+1 inclusive where n is any positive integer, and "k is any positive integer from 1 to 4n.

References Cited The following references, cited by the Examiner, are of record in the patented file of this patent or the original patent.

UNITED STATES PATENTS 3,110,821 11/1963 Webb 328-43 X 3,235,796 2/1966 Tarczy-Hornoch 33157 X 3,350,659 10/1967 Henn 331--57 3,428,913 2/1969 Pechoucek 307-223 X ROY LAKE, Primary Examiner S. H. GRIMM, Assistant Examiner US. Cl. X.R.

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