US9082811B2 - 3C-SiC transistor - Google Patents

3C-SiC transistor Download PDF

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US9082811B2
US9082811B2 US14/034,024 US201314034024A US9082811B2 US 9082811 B2 US9082811 B2 US 9082811B2 US 201314034024 A US201314034024 A US 201314034024A US 9082811 B2 US9082811 B2 US 9082811B2
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semiconductor
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drift region
transistor
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Peter Ward
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Anvil Semiconductors Ltd
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Definitions

  • This invention relates to a power semiconductor transistor, particularly but not exclusively, to a bipolar power semiconductor transistor.
  • FIG. 1 illustrates a recently published (N. Kaminski & O. Hilt, iPower2, Nov. 28, 2012, 18) graph illustrating trade-off between the specific on-resistance versus breakdown voltage for various Si and 4H-SiC devices.
  • the mature Si-MOSFET technology shows clearly the difference between practical products and the theoretical limit. For example at 1000V the theory suggests 200 m ⁇ -cm 2 while in practise 600 m ⁇ -cm 2 is achieved. This data also shows the dramatic advantage of Super Junction technology with ⁇ 75 m ⁇ -cm 2 at 1000V.
  • Si-IGBT and Si-IGCT data points relate to bipolar devices and demonstrate the advantages of this type of device in the breakdown voltage versus on-resistance compromise.
  • SiC another effect comes into play in that, unlike in Si, the resistance of the channel region under the MOSFET Gate becomes significant at “lower” voltages, as shown in FIG. 1 .
  • One way to mitigate the SiC unipolar drift region limit is to grow an n ⁇ 3C-SiC layer on a p+ Si wafer. This can produce a structure for an n-channel IGBT. It was also reported on the Dimitrijev review that the 3C conduction band is 0.9 eV lower than that of 4H and therefore the acceptor states above should not affect the 3C-SiC (like they can affect 4H-SiC). Therefore low channel resistance in 3C-SiC/Si MOSFETs and IGBTs can be expected.
  • a bipolar power semiconductor transistor comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region of the first conductivity type disposed on the semiconductor substrate; a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region; a body region of the first conductivity type located within the semiconductor drift region; a source region of the second conductivity type located within the body region; a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region; wherein the semiconductor substrate comprises a material comprising silicon (Si) and the first semiconductor region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
  • an n-channel IGBT can be produced in 3C-SiC/Si, which is also benefited from the better channel mobility in 3C-SiC compared to 4H-SiC.
  • the semiconductor substrate may comprise monocrystalline silicon material.
  • the substrate material may be heavily doped using Boron.
  • the first semiconductor region may also be heavily doped and having the same doping concentration level as the substrate region.
  • the semiconductor drift region, the body region and the source region each may comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
  • the interface between the first semiconductor region and the semiconductor substrate may be conductive due to the presence of a plurality of defects and dislocations in the first semiconductor region.
  • the interface may also be very heavily doped by an injection of Nitrogen in the first SiC growth phase and the up-diffusion of dopant (Boron) from the Si substrate.
  • the gate may be configured to form an n-channel between the source region and the semiconductor drift region through which electron can be injected to the semiconductor drift region.
  • the n-channel may comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
  • the transistor above may be an insulated gate bipolar transistor (IGBT).
  • the transistor above may be a non-punch through insulated gate bipolar transistor (NPT-IGBT).
  • the transistor may further comprise a buffer region of the first conductivity type between the first semiconductor region and the semiconductor drift region, the buffer region having lower doping concentration than the first semiconductor region.
  • the transistor may be a punch-through insulated gate bipolar transistor (PT-IGBT).
  • the buffer region may comprise a material having 3-step cubic silicon carbide (3C-SiC).
  • the first semiconductor region may be an injection region configured to inject charge into the semiconductor drift region.
  • the drift region may be configured to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor.
  • a lateral bipolar transistor comprising: a semiconductor substrate of a first conductivity type; a lateral drift region of a second, opposite conductivity type, disposed on the semiconductor substrate; a first semiconductor region of the second conductivity type disposed within the drift region; a contact region of the first conductivity type disposed within the first semiconductor region; a second semiconductor region of the first conductivity type within the drift region, wherein the lateral drift region is placed between the first semiconductor region and the second semiconductor region, the lateral drift region to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor; a source region of the second conductivity type located within the second semiconductor region; a gate placed above and in contact to the second semiconductor region, the gate to control charge in a channel region between the lateral drift region and the source region and to thereby control flow of charge within the lateral drift region; wherein the semiconductor substrate comprises a material comprising silicon and the
  • the first contact region, the first and second semiconductor regions and the lateral drift region each may comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
  • a lateral insulated gate bipolar transistor may incorporate the transistor as described hereinbefore.
  • a semiconductor transistor comprising: a semiconductor substrate having a first conductivity type; a first semiconductor region having the first conductivity type disposed on the semiconductor substrate; a drift region having a second, opposite conductivity type, disposed on the first semiconductor region, the drift region having lower doping concentration compared to the first semiconductor region; a second semiconductor region of the first conductivity type disposed on the drift region, the second semiconductor region having higher doping concentration than the drift region; and a contact region of the second conductivity type located within the second semiconductor region, the contact region having higher doping concentration than the second semiconductor region; wherein the semiconductor substrate comprises a material comprising silicon and wherein the first semiconductor region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
  • the substrate may comprise monocrystalline silicon material.
  • the drift region, the second semiconductor region and the contact region each may comprise a material comprising 3-step cubic silicon carbide.
  • a thyristor may incorporate the transistor as described hereinbefore.
  • a method of manufacturing a bipolar power semiconductor transistor comprising: forming a semiconductor substrate of a first conductivity type using silicon material forming a first semiconductor region of the first conductivity type using 3-step cubic silicon carbide (3C-SiC) material; forming a semiconductor drift region of a second conductivity type, opposite the first conductivity type; forming a body region of the first conductivity type located within the body region; forming a source region of the second conductivity type within the body region; forming a gate above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow to charge, within the semiconductor drift region.
  • 3C-SiC 3-step cubic silicon carbide
  • the semiconductor substrate may comprise a material comprising monocrystalline silicon and the semiconductor drift region, the body region and the source region each comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
  • FIG. 1 illustrates a graph showing trade-off between breakdown voltage and specific on-resistance for the state of the art semiconductor devices
  • FIG. 2 illustrates an energy band diagram showing the likely position of interface states for 4H-, 6H- and 15R-SiC;
  • FIG. 3 illustrates a schematic cross section of an IGBT
  • FIG. 4 illustrates an equivalent circuit diagram of the IGBT of FIG. 3 ;
  • FIG. 5 illustrates a schematic cross section of an alternative IGBT
  • FIG. 6 illustrates a schematic cross section of a lateral IGBT
  • FIG. 7 illustrates a schematic cross section of a thyristor.
  • the transistor 100 has first and second 3-step cubic silicon carbide (3C-SiC) epitaxial layers 120 , 130 grown using the process described in WO2013061047 from which the present application claims the continuation in part relationship.
  • the silicon carbide epitaxial layers 120 , 130 include a heavily-doped p-type layer 120 which is supported on a p ⁇ type silicon substrate 110 , and a lightly-doped n-type layer 130 which provides a drift region and which is supported on the p-type silicon carbide layer 120 .
  • the first epitaxial layer 120 provides a p-type collector.
  • P-type wells 140 at the surface 160 of the epitaxial layer 130 provide body regions 140 .
  • N-type wells 150 within the p-type wells 140 provide contact regions and provide emitters.
  • the body region 140 and the contact region 150 can be formed using 3C-SiC material.
  • a channel 170 is formed beneath a gate 180 which is separated using a gate dielectric layer 190 .
  • the IGBT shown in FIG. 3 is able to support much greater breakdown voltages due to the use of 3C-SiC in the epitaxial drift region 130 .
  • the on-resistance of the 3C-SiC IGBT can be significantly lower than the 4H-SiC IGBT. This is because a better channel mobility is observed in 3C-SiC (compared to 4H-SiC) and therefore the on-resistance of the channel region formed between the drift region 130 and the emitter region 150 can be significantly reduced.
  • a heterostructure is formed between the p+ silicon substrate 110 and p+ 3C-SiC layer 120 .
  • the 3C-SiC material in the first epitaxial layer 130 ( ⁇ 2 microns) just above the SiC/Si interface 200 is very heavily defective because of the lattice miss-match between the two materials and heavily doped with Al as-grown, consequently this defective region is very conductive.
  • the heterojunction structure and consequent potential barriers can be overcome by becoming a quasi-metallic interface due to the presence of the dislocations, Al doping during epitaxial growth and Boron up-diffusion from the Si substrate.
  • the on-state and off-state operations of the IGBT 100 are described below.
  • the IGBT as shown in FIG. 3 has within its structure two MOS-bipolar devices:
  • a reverse biased PIN diode (formed by region 120 , drift region 130 and body region 140 ) serves to support the high voltage applied between the emitter 150 and collector 120 .
  • the transistor 100 can be turned-on by applying a positive voltage to the gate 180 with respect to the emitter 150 to invert the p base surface under the insulated gate 180 .
  • the channel 170 is then formed at the surface of the body region 140 , between the n+ emitter 150 and the n ⁇ drift region 130 , which allows electrons to be injected into the n-drift region 130 .
  • This electron current serves as a base current for the bipolar PNP transistor formed between the p+ emitter 150 , the n ⁇ drift region (base) 130 and the p+ 3C-SiC collector 120 .
  • the transistor 100 can be turned-off by short-circuiting the gate voltage to the emitter 150 which cuts off the supply of electrons to the base (the drift region 130 ) of the PNP transistor within the IGBT 100 as described above.
  • the turn-off speed of the device 100 is determined by the open base current decay of the PNP transistor within the IGBT 100 which in turn is dependent on the excess carrier charge (plasma) stored in the n ⁇ drift region 130 .
  • the IGBT 100 of FIG. 3 is a non-punch through (NPT) IGBT in which the n-drift region 130 has a longer length such that, during the off-state, the depletion region in the drift region 130 does not reach the p+ SiC layer 120 .
  • NPT non-punch through
  • FIG. 5 illustrates a schematic cross-section of a punch-through (PT) IGBT 300 .
  • the IGBT structure 300 in FIG. 5 has an additional layer which is a buffer layer 310 between the p+ SiC layer 120 and the n-drift region 130 .
  • the buffer layer 310 is an n type layer having higher doping concentration than the n-drift region 130 .
  • the n buffer layer 310 and the n ⁇ drift layer 130 are made one after the other by epitaxial growth.
  • the n buffer 310 can have a double role: it stops the depletion region to reach the collector 120 and it adjust the injection efficiency of the collector junction. This helps to control the plasma growth during on-state and thus control the trade-off between the on-state losses and turn-off speed and losses.
  • FIG. 6 shows schematically a cross-sectional view of an LIGBT 400 .
  • an n-type drift region 405 is formed on a p-type substrate 410 .
  • the substrate 410 is a monocrystalline silicon substrate and the drift region 405 is a 3-step cubic silicon carbide (3C-SiC) epitaxial layer.
  • the 3C-SiC drift region 405 on the silicon substrate 410 is formed using the process described in WO2013061047 from which the present application claims the continuation in part relationship.
  • the drift region 410 is generally depleted of mobile carriers during the off-state blocking mode to support the breakdown voltage and conduct charge during the on-state conducting mode.
  • a p-type region 415 forms an ohmic contact with a drain electrode 470 .
  • An n-type region 420 surrounds the p-type region 415 and is more highly doped than the drift region 405 .
  • the n-type region 420 prevents the punch through breakdown and can also be used to alter LIGBT characteristics.
  • a p-well 425 forms a device channel region 440 .
  • a gate electrode 430 is placed on top of this region and is separated by a thin oxide 435 . The gate electrode 430 is used to control the charge in the channel region 440 by controlling the flow of charge within the drift region 405 .
  • a further n-type region 450 and p-type region 460 are formed within the p-well 425 which are connected together forming the ohmic contact to a device source electrode 490 .
  • the p-type region 415 , n-type region 420 , the p-well 425 , the further n-type region 450 and the further p-type region 460 are made of 3C-SiC material.
  • the current flows from the source electrode 490 to the drain electrode 470 in a lateral direction (unlike the IGBT structure of FIG. 3 in which the current flow in a vertical direction).
  • the on-resistance in the channel region is also significantly reduced due to the increased mobility of the 3C-SiC.
  • FIG. 7 illustrates a schematic view of a thyristor 500 according to one embodiment of the present invention.
  • the thyristor 500 is a four layer power bipolar semiconductor device having four alternating layers of p-type and n-type doping.
  • the thyristor 500 is a current-control device and in the on-state operates under very high level carrier injection.
  • the thyristor 500 has a p+ layer 505 to which an anode ohmic contact 510 is formed.
  • the p+ layer 505 therefore forms an anode region 505 .
  • the anode region 505 includes monocrystalline silicon as a material.
  • a p-type layer 515 is formed on the anode region 505 .
  • the p-type layer 515 has lower doping concentration than that of the anode region 505 .
  • the p-type layer 515 includes 3-step cubic silicon carbide (3C-SiC) as a material.
  • a n-drift region 520 is formed on the p-type layer 515 .
  • a second p-type region 525 is formed on the drift region 520 .
  • the second p-type region 525 has higher doping concentration than that of the drift region 520 .
  • a further p+ region 530 is disposed within the second p-type region 525 .
  • a gate 530 is directly disposed on the further p+ region 530 .
  • An p+ type region providing a cathode region 535 is formed within the second p-type region 525 .
  • the cathode region 535 is heavily doped and therefore a cathode ohmic contact is formed directly on the cathode region 535 .
  • the drift region 520 , the second p-type region 525 , the further p-type region 530 and the cathode region 535 each include a material comprising 3C-SiC.
  • the thyristor 500 can be turned on by the gate 530 by applying a positive current pulse. To turn-off the thyristor 500 , a reverse bias voltage is applied across the anode-cathode terminal. In the forward blocking state the anode region 505 is biased positive with respect to the cathode region 535 , while in the reverse blocking state the anode region 505 is biased negative with respect to the cathode region 535 .
  • FIG. 7 is directed to a normal thyristor structure in which 3C-SiC layers are formed on a silicon wafer 505 , it will be appreciated that the same principal can be applied to other thyristor structures, for example, a gate turn-off (GTO) thyristor and a gate-commutated thyristor (GCT).
  • GTO gate turn-off
  • GCT gate-commutated thyristor
  • 3C-SiC epitaxial layers on silicon wafer can be equally applied to other semiconductor devices such as a vertical bipolar junction transistor (BJT).
  • BJT vertical bipolar junction transistor
  • the structure of the vertical bipolar junction transistor is similar to the thyristor shown in FIG. 7 , except that p+ anode layer 505 and the p layer 515 on top of the p+ anode layer 505 are replaced by an p+ layer having silicon material.
  • the same concept can be equally applied to a lateral bipolar junction transistor, a substrate fed logic device and an integrated injection logic device.
  • first conductivity type can refer to a p-type doping polarity and the term “second conductivity” can refer to a n-type doping polarity.
  • second conductivity can refer to a n-type doping polarity.
  • all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present invention.
  • the emitter, collector and gate could be arranged to be out-of-plane or to be differently aligned so that the direction of the carriers is not exactly as described above, the resulting devices still being in accordance with the present invention.

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Abstract

A bipolar power semiconductor transistor is disclosed. The transistor includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type disposed on the semiconductor substrate; a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region, a body region of the first conductivity type located within the semiconductor drift region, a source region of the second conductivity type located within the body region, a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region. The semiconductor substrate includes a material having silicon (Si) and the first semiconductor region includes a material having 3-step cubic silicon carbide (3C-SiC).

Description

RELATIONSHIP TO EARLIER APPLICATIONS
This application is a continuation-in-part of PCT application number PCT/GB2012/052627 and published as WO2013/061047, which is hereby incorporated by reference in its entirety.
FIELD OF THE INVENTION
This invention relates to a power semiconductor transistor, particularly but not exclusively, to a bipolar power semiconductor transistor.
BACKGROUND TO THE INVENTION
It is known that semiconductor devices are employed as switches and they operate in “on” and “off” states. In the on-state the device can conduct high currents at modest voltages and the conduction losses are desired to be reduced. In the offstate the device can withstand the system maximum voltage with little or no current passing. There are generally two types of devices in the market, unipolar (MOSFET) where conduction is by majority carriers only, and bipolar where conduction is by majority and minority carriers. One fundamental problem is that to withstand a certain voltage a certain thickness of material is required (a drift region), set by a critical field for breakdown. Hence the higher the voltage the thicker and more resistive the drift region becomes. This sets the fundamental limit of a unipolar device in a given material because there is a compromise between voltage capability and device conductivity.
For these reasons wide band gap semiconductors with their much higher critical fields can be preferred to the standard silicon (Si). Of course, since Si is such an established engineering material, ways have been found to overcome this fundamental limit to some degree in the development of Superjunction MOSFETs. However the price paid as ever is much increased device complexity and higher manufacturing costs. The other way of overcoming this limit is to move from unipolar to bipolar devices. In this case the drift region resistivity is reduced in the on-state by the injection of minority carriers. The best known of these devices in the Si world is the Insulated Gate Bipolar Transistor (IGBT). In reality however this device is generally similar to a standard (non-SJ) MOSFET with the n+ Drain contact replaced by a p+ region which acts as an injector in the on-state. Of course there is a price to be paid for this enhanced performance in that the switching speed of an IGBT is much lower than that of a MOSFET because of the lengthy time required to remove the minority carriers from the drift region when switching the device off. This also increases switching losses.
Turning back to the trade-off between the breakdown voltage and specific on-resistance in unipolar device, consideration of basic materials properties and the structures of unipolar (MOSFET) devices are discussed below. FIG. 1 illustrates a recently published (N. Kaminski & O. Hilt, iPower2, Nov. 28, 2012, 18) graph illustrating trade-off between the specific on-resistance versus breakdown voltage for various Si and 4H-SiC devices.
Considering first the Si data, the mature Si-MOSFET technology shows clearly the difference between practical products and the theoretical limit. For example at 1000V the theory suggests 200 mΩ-cm2 while in practise 600 mΩ-cm2 is achieved. This data also shows the dramatic advantage of Super Junction technology with ˜75 mΩ-cm2 at 1000V.
The Si-IGBT and Si-IGCT data points relate to bipolar devices and demonstrate the advantages of this type of device in the breakdown voltage versus on-resistance compromise. Turning now to SiC another effect comes into play in that, unlike in Si, the resistance of the channel region under the MOSFET Gate becomes significant at “lower” voltages, as shown in FIG. 1.
It has been reported by Cree Inc. that the on-resistance in 4H-SiC devices is roughly half from the Channel region and half from the drift region. This would suggest that the current practical 4H-SiC unipolar limit for MOSFETs is five or six times higher than the theoretical value, probably reflecting the less than perfect material quality.
The SiC JFET data above suggests better performance than the MOSFET. However, this has to be regarded with a degree of caution since by their nature it is difficult to avoid a degree of bipolar action in a JFET. This of course may not be disadvantageous, except that this will bring into play other compromises.
The other bipolar SiC data points for Bipolar Transistors and IGBTs show some improvement over the unipolar limit, but nowhere near the several orders of magnitude difference between Si unipolars and Si bipolars.
Based on FIG. 1 and considering only device performance as governed by drift region consideration (and not costs) then it is clear that at 650V a simple structure MOSFET in SiC should outperform a Superjunction (SJ) Si MOSFET because the higher critical field of SiC permits a very thin drift region to be used. Further, since the SiC device cannot utilise SJ technology then the way is open to produce MOSFETs at higher voltages, as has been demonstrated by Cree Inc. All these unipolar devices conduct using electrons because of their high mobility and hence are termed “n-channel”.
However, at some point these unipolar devices will hit the drift region limit, although they are limited by other factors in 4H-SiC currently. Therefore it would be useful if the same “trick” could be employed in SiC to convert MOSFETs into IGBTs by adding a p+ injector. However, in fact this is (almost) impossible in 4H-SiC since all-pervasive nitrogen is an n-type dopant in SiC and the standard method of growing 4H-SiC crystals results in an n+ boule. Some work has been performed to produce p-channel IGBTs in 4H-SiC, forced by the presence of the n+ substrate.
Furthermore, the high channel resistance of 4H-SiC MOSFETs is a well-known problem, the best channel electron mobilities achieved are roughly 5% of the theoretical bulk value. A published review (Advances in SiC power MOSFET technology, Sima Dimitrijev, Philippe Jamet. Microelectronics Reliability 43 (2003) 225-233) summarises the idea that the high density of interface traps close to bottom of the conduction band causes the low mobility in 4H-SiC MOSFETs. The density of these interface traps is assumed to increase sharply toward the edge of the conduction band, where it reaches extremely high values as shown in FIG. 2.
It is an object of the present invention to address the problems discussed above.
SUMMARY
One way to mitigate the SiC unipolar drift region limit is to grow an n− 3C-SiC layer on a p+ Si wafer. This can produce a structure for an n-channel IGBT. It was also reported on the Dimitrijev review that the 3C conduction band is 0.9 eV lower than that of 4H and therefore the acceptor states above should not affect the 3C-SiC (like they can affect 4H-SiC). Therefore low channel resistance in 3C-SiC/Si MOSFETs and IGBTs can be expected.
According to one aspect of the present invention, there is provided a bipolar power semiconductor transistor comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region of the first conductivity type disposed on the semiconductor substrate; a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region; a body region of the first conductivity type located within the semiconductor drift region; a source region of the second conductivity type located within the body region; a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region; wherein the semiconductor substrate comprises a material comprising silicon (Si) and the first semiconductor region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
In this way an n-channel IGBT can be produced in 3C-SiC/Si, which is also benefited from the better channel mobility in 3C-SiC compared to 4H-SiC.
The semiconductor substrate may comprise monocrystalline silicon material. The substrate material may be heavily doped using Boron. The first semiconductor region may also be heavily doped and having the same doping concentration level as the substrate region. The semiconductor drift region, the body region and the source region each may comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
When the transistor is in use, the interface between the first semiconductor region and the semiconductor substrate may be conductive due to the presence of a plurality of defects and dislocations in the first semiconductor region. The interface may also be very heavily doped by an injection of Nitrogen in the first SiC growth phase and the up-diffusion of dopant (Boron) from the Si substrate. Hence the potential barriers which normally exist between different semiconductors, the heterojunction, are overcome because the interface between the first semiconductor region and the semiconductor substrate is effectively quasi-metallic.
The gate may be configured to form an n-channel between the source region and the semiconductor drift region through which electron can be injected to the semiconductor drift region. The n-channel may comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
The transistor above may be an insulated gate bipolar transistor (IGBT). The transistor above may be a non-punch through insulated gate bipolar transistor (NPT-IGBT).
The transistor may further comprise a buffer region of the first conductivity type between the first semiconductor region and the semiconductor drift region, the buffer region having lower doping concentration than the first semiconductor region.
The transistor may be a punch-through insulated gate bipolar transistor (PT-IGBT). The buffer region may comprise a material having 3-step cubic silicon carbide (3C-SiC).
The first semiconductor region may be an injection region configured to inject charge into the semiconductor drift region. The drift region may be configured to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor.
According to a further aspect of the present invention, there is provided a lateral bipolar transistor comprising: a semiconductor substrate of a first conductivity type; a lateral drift region of a second, opposite conductivity type, disposed on the semiconductor substrate; a first semiconductor region of the second conductivity type disposed within the drift region; a contact region of the first conductivity type disposed within the first semiconductor region; a second semiconductor region of the first conductivity type within the drift region, wherein the lateral drift region is placed between the first semiconductor region and the second semiconductor region, the lateral drift region to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor; a source region of the second conductivity type located within the second semiconductor region; a gate placed above and in contact to the second semiconductor region, the gate to control charge in a channel region between the lateral drift region and the source region and to thereby control flow of charge within the lateral drift region; wherein the semiconductor substrate comprises a material comprising silicon and the lateral drift region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
The first contact region, the first and second semiconductor regions and the lateral drift region each may comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
A lateral insulated gate bipolar transistor (LIGBT) may incorporate the transistor as described hereinbefore.
According to a further aspect of the present invention, there is provided a semiconductor transistor comprising: a semiconductor substrate having a first conductivity type; a first semiconductor region having the first conductivity type disposed on the semiconductor substrate; a drift region having a second, opposite conductivity type, disposed on the first semiconductor region, the drift region having lower doping concentration compared to the first semiconductor region; a second semiconductor region of the first conductivity type disposed on the drift region, the second semiconductor region having higher doping concentration than the drift region; and a contact region of the second conductivity type located within the second semiconductor region, the contact region having higher doping concentration than the second semiconductor region; wherein the semiconductor substrate comprises a material comprising silicon and wherein the first semiconductor region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
The substrate may comprise monocrystalline silicon material. The drift region, the second semiconductor region and the contact region each may comprise a material comprising 3-step cubic silicon carbide.
A thyristor may incorporate the transistor as described hereinbefore.
According to a further aspect of the present invention, there is provided a method of manufacturing a bipolar power semiconductor transistor, the method comprising: forming a semiconductor substrate of a first conductivity type using silicon material forming a first semiconductor region of the first conductivity type using 3-step cubic silicon carbide (3C-SiC) material; forming a semiconductor drift region of a second conductivity type, opposite the first conductivity type; forming a body region of the first conductivity type located within the body region; forming a source region of the second conductivity type within the body region; forming a gate above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow to charge, within the semiconductor drift region.
The semiconductor substrate may comprise a material comprising monocrystalline silicon and the semiconductor drift region, the body region and the source region each comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the invention to the specific embodiments shown, but are for explanation and understanding only.
FIG. 1 illustrates a graph showing trade-off between breakdown voltage and specific on-resistance for the state of the art semiconductor devices;
FIG. 2 illustrates an energy band diagram showing the likely position of interface states for 4H-, 6H- and 15R-SiC;
FIG. 3 illustrates a schematic cross section of an IGBT;
FIG. 4 illustrates an equivalent circuit diagram of the IGBT of FIG. 3;
FIG. 5 illustrates a schematic cross section of an alternative IGBT;
FIG. 6 illustrates a schematic cross section of a lateral IGBT, and
FIG. 7 illustrates a schematic cross section of a thyristor.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 3, an example of a vertical power semiconductor transistor 100 in the form of an insulated gate bipolar transistor (IGBT) is shown. The transistor 100 has first and second 3-step cubic silicon carbide (3C-SiC) epitaxial layers 120, 130 grown using the process described in WO2013061047 from which the present application claims the continuation in part relationship. The silicon carbide epitaxial layers 120, 130 include a heavily-doped p-type layer 120 which is supported on a p− type silicon substrate 110, and a lightly-doped n-type layer 130 which provides a drift region and which is supported on the p-type silicon carbide layer 120. The first epitaxial layer 120 provides a p-type collector. P-type wells 140 at the surface 160 of the epitaxial layer 130 provide body regions 140. N-type wells 150 within the p-type wells 140 provide contact regions and provide emitters. The body region 140 and the contact region 150 can be formed using 3C-SiC material. A channel 170 is formed beneath a gate 180 which is separated using a gate dielectric layer 190.
The IGBT shown in FIG. 3 is able to support much greater breakdown voltages due to the use of 3C-SiC in the epitaxial drift region 130. At the same time the on-resistance of the 3C-SiC IGBT can be significantly lower than the 4H-SiC IGBT. This is because a better channel mobility is observed in 3C-SiC (compared to 4H-SiC) and therefore the on-resistance of the channel region formed between the drift region 130 and the emitter region 150 can be significantly reduced.
It will be appreciated that a heterostructure is formed between the p+ silicon substrate 110 and p+ 3C-SiC layer 120. The 3C-SiC material in the first epitaxial layer 130 (˜2 microns) just above the SiC/Si interface 200 is very heavily defective because of the lattice miss-match between the two materials and heavily doped with Al as-grown, consequently this defective region is very conductive. In this way the heterojunction structure and consequent potential barriers can be overcome by becoming a quasi-metallic interface due to the presence of the dislocations, Al doping during epitaxial growth and Boron up-diffusion from the Si substrate.
The on-state and off-state operations of the IGBT 100 are described below.
The IGBT as shown in FIG. 3 has within its structure two MOS-bipolar devices:
(i) A cascade MOSFET-PIN diode;
(ii) A MOS base current controlled-wide base PNP transistor.
The equivalent circuits for these components of the IGBT structure 100 are shown in FIG. 4.
In the off-state a reverse biased PIN diode (formed by region 120, drift region 130 and body region 140) serves to support the high voltage applied between the emitter 150 and collector 120.
The transistor 100 can be turned-on by applying a positive voltage to the gate 180 with respect to the emitter 150 to invert the p base surface under the insulated gate 180. The channel 170 is then formed at the surface of the body region 140, between the n+ emitter 150 and the n− drift region 130, which allows electrons to be injected into the n-drift region 130. This electron current serves as a base current for the bipolar PNP transistor formed between the p+ emitter 150, the n− drift region (base) 130 and the p+ 3C-SiC collector 120. Once the PNP transistor (within the IGBT 100) is turned on, excess carrier charge (plasma) builds up in the lowly-doped n− drift region 130 and the conductivity of this layer increases significantly.
The transistor 100 can be turned-off by short-circuiting the gate voltage to the emitter 150 which cuts off the supply of electrons to the base (the drift region 130) of the PNP transistor within the IGBT 100 as described above. The turn-off speed of the device 100 is determined by the open base current decay of the PNP transistor within the IGBT 100 which in turn is dependent on the excess carrier charge (plasma) stored in the n− drift region 130.
The IGBT 100 of FIG. 3 is a non-punch through (NPT) IGBT in which the n-drift region 130 has a longer length such that, during the off-state, the depletion region in the drift region 130 does not reach the p+ SiC layer 120.
FIG. 5 illustrates a schematic cross-section of a punch-through (PT) IGBT 300. Many features of the IGBT in FIG. 5 are the same as those shown in FIG. 3 and therefore carry the same reference numerals. However, the IGBT structure 300 in FIG. 5 has an additional layer which is a buffer layer 310 between the p+ SiC layer 120 and the n-drift region 130. The buffer layer 310 is an n type layer having higher doping concentration than the n-drift region 130. The n buffer layer 310 and the n− drift layer 130 are made one after the other by epitaxial growth. The n buffer 310 can have a double role: it stops the depletion region to reach the collector 120 and it adjust the injection efficiency of the collector junction. This helps to control the plasma growth during on-state and thus control the trade-off between the on-state losses and turn-off speed and losses.
Referring to FIG. 6, an example of a lateral power semiconductor transistor 400 in the form of an lateral insulated gate bipolar transistor (LIGBT) is shown. FIG. 6 shows schematically a cross-sectional view of an LIGBT 400. In this figure, an n-type drift region 405 is formed on a p-type substrate 410. The substrate 410 is a monocrystalline silicon substrate and the drift region 405 is a 3-step cubic silicon carbide (3C-SiC) epitaxial layer. The 3C-SiC drift region 405 on the silicon substrate 410 is formed using the process described in WO2013061047 from which the present application claims the continuation in part relationship. The drift region 410 is generally depleted of mobile carriers during the off-state blocking mode to support the breakdown voltage and conduct charge during the on-state conducting mode. A p-type region 415 forms an ohmic contact with a drain electrode 470. An n-type region 420 surrounds the p-type region 415 and is more highly doped than the drift region 405. The n-type region 420 prevents the punch through breakdown and can also be used to alter LIGBT characteristics. A p-well 425 forms a device channel region 440. A gate electrode 430 is placed on top of this region and is separated by a thin oxide 435. The gate electrode 430 is used to control the charge in the channel region 440 by controlling the flow of charge within the drift region 405. A further n-type region 450 and p-type region 460 are formed within the p-well 425 which are connected together forming the ohmic contact to a device source electrode 490. The p-type region 415, n-type region 420, the p-well 425, the further n-type region 450 and the further p-type region 460 are made of 3C-SiC material. In this IGBT structure, the current flows from the source electrode 490 to the drain electrode 470 in a lateral direction (unlike the IGBT structure of FIG. 3 in which the current flow in a vertical direction). In this embodiment, the on-resistance in the channel region is also significantly reduced due to the increased mobility of the 3C-SiC.
FIG. 7 illustrates a schematic view of a thyristor 500 according to one embodiment of the present invention. The thyristor 500 is a four layer power bipolar semiconductor device having four alternating layers of p-type and n-type doping. The thyristor 500 is a current-control device and in the on-state operates under very high level carrier injection. The thyristor 500 has a p+ layer 505 to which an anode ohmic contact 510 is formed. The p+ layer 505 therefore forms an anode region 505. The anode region 505 includes monocrystalline silicon as a material. A p-type layer 515 is formed on the anode region 505. The p-type layer 515 has lower doping concentration than that of the anode region 505. The p-type layer 515 includes 3-step cubic silicon carbide (3C-SiC) as a material. A n-drift region 520 is formed on the p-type layer 515. A second p-type region 525 is formed on the drift region 520. The second p-type region 525 has higher doping concentration than that of the drift region 520. A further p+ region 530 is disposed within the second p-type region 525. A gate 530 is directly disposed on the further p+ region 530. An p+ type region providing a cathode region 535 is formed within the second p-type region 525. The cathode region 535 is heavily doped and therefore a cathode ohmic contact is formed directly on the cathode region 535. The drift region 520, the second p-type region 525, the further p-type region 530 and the cathode region 535 each include a material comprising 3C-SiC.
The thyristor 500 can be turned on by the gate 530 by applying a positive current pulse. To turn-off the thyristor 500, a reverse bias voltage is applied across the anode-cathode terminal. In the forward blocking state the anode region 505 is biased positive with respect to the cathode region 535, while in the reverse blocking state the anode region 505 is biased negative with respect to the cathode region 535.
Although the embodiment of FIG. 7 is directed to a normal thyristor structure in which 3C-SiC layers are formed on a silicon wafer 505, it will be appreciated that the same principal can be applied to other thyristor structures, for example, a gate turn-off (GTO) thyristor and a gate-commutated thyristor (GCT).
Similarly the principal of forming 3C-SiC epitaxial layers on silicon wafer can be equally applied to other semiconductor devices such as a vertical bipolar junction transistor (BJT). The structure of the vertical bipolar junction transistor is similar to the thyristor shown in FIG. 7, except that p+ anode layer 505 and the p layer 515 on top of the p+ anode layer 505 are replaced by an p+ layer having silicon material.
Furthermore, the same concept can be equally applied to a lateral bipolar junction transistor, a substrate fed logic device and an integrated injection logic device.
It will be appreciated that the doping concentrations of various layers of the transistors discussed with reference to FIGS. 3 to 7 are those used in the corresponding state of the art transistors.
The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘above’, ‘overlap’, ‘under’, ‘lateral’, ‘vertical’, etc. are made with reference to conceptual illustrations of a transistor, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a transistor when in an orientation as shown in the accompanying drawings.
It will be noted that the term “first conductivity type” can refer to a p-type doping polarity and the term “second conductivity” can refer to a n-type doping polarity. However, these terms are not restrictive. It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present invention. It will be appreciated that the emitter, collector and gate could be arranged to be out-of-plane or to be differently aligned so that the direction of the carriers is not exactly as described above, the resulting devices still being in accordance with the present invention.
Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims (22)

The invention claimed is:
1. A bipolar power semiconductor transistor comprising:
a semiconductor substrate of a first conductivity type;
a first semiconductor region of the first conductivity type disposed on the semiconductor substrate;
a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region;
a body region of the first conductivity type located within the semiconductor drift region;
a source region of the second conductivity type located within the body region;
a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region;
wherein the semiconductor substrate comprises a material comprising silicon (Si) and the first semiconductor region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
2. A transistor according to claim 1, wherein the semiconductor substrate comprises moncrystalline silicon material.
3. A transistor according to claim 1, wherein the semiconductor drift region, the body region and the source region each comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
4. A transistor according to claim 1, wherein, in use, the interface between the first semiconductor region and the semiconductor substrate is conductive due to the presence of a plurality of dopants, defects and dislocations in the first semiconductor region.
5. A transistor according to claim 4, wherein the interface between the first semiconductor region and the semiconductor substrate is a quasi-metallic interface which overcomes the potential barrier at the interface due to the presence of the dopants, defects and dislocations.
6. A transistor according to claim 1, wherein the gate is configured to form an n-channel between the source region and the semiconductor drift region through which electron can be injected to the semiconductor drift region.
7. A transistor according to claim 6, wherein the n-channel comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
8. A transistor according to claim 1 being an insulated gate bipolar transistor (IGBT).
9. A transistor according to claim 1 being a non-punch through insulated gate bipolar transistor (NPT-IGBT).
10. A transistor according to claim 1, further comprising a buffer region of the first conductivity type between the first semiconductor region and the semiconductor drift region, the buffer region having lower doping concentration than the first semiconductor region.
11. A transistor according to claim 10 being a punch-through insulated gate bipolar transistor (PT-IGBT).
12. A transistor according to claim 10, wherein the buffer region comprises a material having 3-step cubic silicon carbide (3C-SiC).
13. A transistor according to claim 1, wherein the first semiconductor region is an injection region configured to inject charge into the semiconductor drift region.
14. A transistor according to claim 1, wherein the drift region is configured to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor.
15. A lateral bipolar transistor comprising:
a semiconductor substrate of a first conductivity type;
a lateral drift region of a second, opposite conductivity type, disposed on the semiconductor substrate;
a first semiconductor region of the second conductivity type disposed within the drift region;
a contact region of the first conductivity type disposed within the first semiconductor region;
a second semiconductor region of the first conductivity type within the drift region, wherein the lateral drift region is placed between the first semiconductor region and the second semiconductor region, the lateral drift region to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor;
a source region of the second conductivity type located within the second semiconductor region;
a gate placed above and in contact to the second semiconductor region, the gate to control charge in a channel region between the lateral drift region and the source region and to thereby control flow of charge within the lateral drift region;
wherein the semiconductor substrate comprises a material comprising silicon and the lateral drift region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
16. A transistor according to claim 15, wherein the first contact region, the first and second semiconductor regions and the lateral drift region each comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
17. A lateral insulated gate bipolar transistor (LIGBT) incorporating the transistor of claim 15.
18. A semiconductor transistor comprising:
a semiconductor substrate having a first conductivity type;
a first semiconductor region having the first conductivity type disposed on the semiconductor substrate;
a drift region having a second, opposite conductivity type, disposed on the first semiconductor region, the drift region having lower doping concentration compared to the first semiconductor region;
a second semiconductor region of the first conductivity type disposed on the drift region, the second semiconductor region having higher doping concentration than the drift region; and
a contact region of the second conductivity type located within the second semiconductor region, the contact region having higher doping concentration than the second semiconductor region;
wherein the semiconductor substrate comprises a material comprising silicon and wherein the first semiconductor region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
19. A transistor according to claim 18, wherein the substrate comprises moncrystalline silicon material and wherein the drift region, the second semiconductor region and the contact region each comprise a material comprising 3-step cubic silicon carbide.
20. A thysistor incorporating the transistor of claim 18.
21. A method of manufacturing a bipolar power semiconductor transistor, the method comprising:
forming a semiconductor substrate of a first conductivity type using silicon material;
forming a first semiconductor region of the first conductivity type using 3-step cubic silicon carbide (3C-SiC) material, the first semiconductor region being disposed on the semiconductor substrate;
forming a semiconductor drift region of a second conductivity type, opposite the first conductivity type, the semiconductor drift region being disposed on the first semiconductor region;
forming a body region of the first conductivity type located within the semiconductor drift region;
forming a source region of the second conductivity type within the body region;
forming a gate above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow to charge, within the semiconductor drift region.
22. A method according to claim 21, wherein the semiconductor substrate comprises a material comprising monocrystalline silicon and the semiconductor drift region, the body region and the source region each comprise a material comprising 3-step cubic silicon carbide (3C-SiC).
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170242949A1 (en) * 2016-02-18 2017-08-24 Infineon Technologies Austria Ag Transistor model, a method for a computer based determination of characteristic of a transistor, a device and a computer readable storage medium for performing the method
TWI730732B (en) * 2020-04-22 2021-06-11 力晶積成電子製造股份有限公司 Insulating gate field effect bipolar transistor and manufacturing method thereof
US11038023B2 (en) 2018-07-19 2021-06-15 Macom Technology Solutions Holdings, Inc. III-nitride material semiconductor structures on conductive silicon substrates
US11264465B2 (en) * 2015-09-08 2022-03-01 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation using silicon carbide diffusion barrier regions

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9013027B2 (en) 2013-07-25 2015-04-21 Infineon Technologies Ag Semiconductor device, a semiconductor wafer structure, and a method for forming a semiconductor wafer structure
US20150059640A1 (en) * 2013-08-27 2015-03-05 Raytheon Company Method for reducing growth of non-uniformities and autodoping during column iii-v growth into dielectric windows
WO2015040369A1 (en) * 2013-09-23 2015-03-26 Anvil Semiconductors Limited 3C-SiC TRANSISTOR
JP6248532B2 (en) * 2013-10-17 2017-12-20 セイコーエプソン株式会社 3C-SiC epitaxial layer manufacturing method, 3C-SiC epitaxial substrate, and semiconductor device
GB2534357B (en) * 2015-01-14 2020-02-19 Anvil Semiconductors Ltd Wafer bow reduction
JP6450282B2 (en) * 2015-08-19 2019-01-09 エア・ウォーター株式会社 Compound semiconductor substrate and method of manufacturing compound semiconductor substrate
KR102534857B1 (en) * 2016-02-12 2023-05-19 주식회사 엘엑스세미콘 Silicon carbide epi wafer and semiconductor device comprising the same
ITUA20162943A1 (en) 2016-04-27 2017-10-27 Pilegrowth Tech S R L Method for the industrial manufacture of a semiconductor structure with reduced bowing.
US9793430B1 (en) * 2016-05-09 2017-10-17 Qatar University Heterojunction schottky gate bipolar transistor
WO2018060679A1 (en) * 2016-09-30 2018-04-05 Anvil Semiconductors Limited 3c-sic igbt
GB2555451A (en) * 2016-10-28 2018-05-02 Univ Warwick Coated wafer
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US10615075B2 (en) * 2018-06-13 2020-04-07 Texas Instruments Incorporated Dicing a wafer
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CN111293113B (en) * 2020-02-21 2023-01-10 电子科技大学 SGTO device adopting single-layer metal process and layout structure and manufacturing method thereof
CN111863595A (en) * 2020-07-06 2020-10-30 璨隆科技发展有限公司 Preparation method of high-quality seed crystal for PVT crystal growth of silicon carbide
CN116387359A (en) * 2023-06-02 2023-07-04 清华大学 Reverse-resistance gate pole commutation thyristor and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6342404B1 (en) 1999-03-31 2002-01-29 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device and method for producing
WO2006060339A2 (en) 2004-12-01 2006-06-08 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
US20080105949A1 (en) * 2006-08-17 2008-05-08 Cree, Inc. High power insulated gate bipolar transistors
US20100065857A1 (en) * 2006-11-10 2010-03-18 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method of manufacturing the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5598823A (en) * 1979-01-20 1980-07-28 Tdk Corp Manufacture of single crystal element
JPS56150880A (en) * 1980-04-23 1981-11-21 Matsushita Electric Ind Co Ltd Gallium nitride light emitting element chip and manufacture thereof
JPS60113435A (en) * 1983-11-25 1985-06-19 Hitachi Ltd Semiconductor device and its manufacture
JPS63260014A (en) * 1986-12-09 1988-10-27 Sharp Corp Method of forming silicon carbide single crystal thin film
US5272105A (en) * 1988-02-11 1993-12-21 Gte Laboratories Incorporated Method of manufacturing an heteroepitaxial semiconductor structure
US5030583A (en) * 1988-12-02 1991-07-09 Advanced Technolgy Materials, Inc. Method of making single crystal semiconductor substrate articles and semiconductor device
JPH0574669A (en) * 1991-09-18 1993-03-26 Rohm Co Ltd Manufacture of semiconductor device
JP3058954B2 (en) * 1991-09-24 2000-07-04 ローム株式会社 Method of manufacturing semiconductor device having growth layer on insulating layer
JP2793460B2 (en) * 1993-01-08 1998-09-03 ローム株式会社 Manufacturing method of SOI structure
JP3795145B2 (en) 1996-09-04 2006-07-12 松下電器産業株式会社 Growth method of silicon carbide
JPH10135140A (en) 1996-10-28 1998-05-22 Nippon Telegr & Teleph Corp <Ntt> Hetero-epitaxial growing method, hetero-epitaxial layer and semiconductor light-emitting device
US6246076B1 (en) * 1998-08-28 2001-06-12 Cree, Inc. Layered dielectric on silicon carbide semiconductor structures
US6566158B2 (en) * 2001-08-17 2003-05-20 Rosemount Aerospace Inc. Method of preparing a semiconductor using ion implantation in a SiC layer
FR2836159B1 (en) 2002-02-15 2004-05-07 Centre Nat Rech Scient METHOD FOR FORMING A LAYER OF SILICON CARBIDE OR ELEMENT III NITRIDE ON A SUITABLE SUBSTRATE
JP5011681B2 (en) * 2004-12-02 2012-08-29 日産自動車株式会社 Semiconductor device
JP2009081352A (en) * 2007-09-27 2009-04-16 Seiko Epson Corp Manufacturing method for semiconductor substrate, and semiconductor substrate
JP2009123914A (en) * 2007-11-15 2009-06-04 Fuji Electric Device Technology Co Ltd Semiconductor device for switching having reverse breakdown strength
JP2009130266A (en) * 2007-11-27 2009-06-11 Toshiba Corp Semiconductor substrate and semiconductor device, and method of manufacturing the same
JP2009218272A (en) * 2008-03-07 2009-09-24 Covalent Materials Corp Compound semiconductor substrate, and manufacturing method thereof
US8048225B2 (en) * 2009-01-29 2011-11-01 Soraa, Inc. Large-area bulk gallium nitride wafer and method of manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6342404B1 (en) 1999-03-31 2002-01-29 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device and method for producing
WO2006060339A2 (en) 2004-12-01 2006-06-08 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
US20080105949A1 (en) * 2006-08-17 2008-05-08 Cree, Inc. High power insulated gate bipolar transistors
US20100065857A1 (en) * 2006-11-10 2010-03-18 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method of manufacturing the same

Non-Patent Citations (12)

* Cited by examiner, † Cited by third party
Title
Dimitrijev et al., "Advances in SiC power MOSFET technology", Microelectronics Reliability 43 (2003) 225-233 (cited on p. 3, line 25 of the specification).
Edgar et al., "Selective epitaxial growth of silicon carbide on Si02 masked Si(100): The effects of temperature", Journal of Applied Physics, American Institute of Physics, New York, US, vol. 84, No. 1, Jul. 1, 1998, pp. 201-204, XP012045156.
Gupta et al., "Selective epitaxy and lateral overgrowth of 3C-SiC on Si-A review", Progress in Crystal Growth and Characterization of Materials, Elsevier Publishing, Barking, GB, vol. 51, No. 1-3, Jan. 1, 2005, pp. 43-69, XP027827904.
Gwo et al., "Selective-area chemical-vapor deposition of Si using a bilayer dielectric mask patterned by proximal probe oxidation", Journal of Vacuum Science and Technology: Part A, AVS/AIP, Melville, NY, US, vol. 19, No. 4, Jul. 1, 2001, pp. 1806-1811, XP012005718.
International Search Report for corresponding International Application No. PCT/GB2012/052627 mailed Apr. 23, 2013.
Kaminski et al., "SiC and GaN Devices-Wide Band-Gap is not all the Same", iPOWER2, Warwick/Coventry, Nov. 28, 2012 (cited on p. 2, line 11 of the specification).
Nishino et al., "Lateral over-growth of 3C-SiC on patterned Si(111) substrates", Journal of Crystal Growth, Elsevier, Amsterdam, NL, vol. 237-239, Apr. 1, 2002, pp. 1250-1253, XP004355976 (previously listed on IDS submitted with application on Sep. 23, 2013).
Nishino et al., "Lateral over-growth of 3C-SiC on patterned Si(111) substrates", Journal of Crystal Growth, Elsevier, Amsterdam, NL, vol. 237-239, Apr. 1, 2002, pp. 1250-1253, XP004355976.
Teker, K. "Selective epitaxial growth of 3C-SiC on patterned Si using hexamethyldisilane by APCVD", Journal of Crystal Growth, Elsevier, Amsterdam, NL, vol. 257, No. 3-4, Oct. 1, 2003, pp. 245-254, XP004452937 (previously listed on IDS submitted with application on Sep. 23, 2013).
Teker, K. "Selective epitaxial growth of 3C-SiC on patterned Si using hexamethyldisilane by APCVD", Journal of Crystal Growth, Elsevier, Amsterdam, NL, vol. 257, No. 3-4, Oct. 1, 2003, pp. 245-254, XP004452937.
Wu et al., "A comparison of Si02 and Si3N4 masks for selective epitaxial growth of 3C-SiC films on Si", Materials Science Forum, Trans Tech Publications Ltd.-Switzerland, vol. 353-356, Jan. 1, 2001, pp. 171-174, XP009166208 (previously listed on IDS submitted with application on Sep. 23, 2013).
Wu et al., "A comparison of Si02 and Si3N4 masks for selective epitaxial growth of 3C-SiC films on Si", Materials Science Forum, Trans Tech Publications Ltd.-Switzerland, vol. 353-356, Jan. 1, 2001, pp. 171-174, XP009166208.

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11264465B2 (en) * 2015-09-08 2022-03-01 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation using silicon carbide diffusion barrier regions
US11810955B2 (en) 2015-09-08 2023-11-07 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation using silicon carbide diffusion barrier regions
US20170242949A1 (en) * 2016-02-18 2017-08-24 Infineon Technologies Austria Ag Transistor model, a method for a computer based determination of characteristic of a transistor, a device and a computer readable storage medium for performing the method
US11038023B2 (en) 2018-07-19 2021-06-15 Macom Technology Solutions Holdings, Inc. III-nitride material semiconductor structures on conductive silicon substrates
US11942518B2 (en) 2018-07-19 2024-03-26 Macom Technology Solutions Holdings, Inc. Reduced interfacial area III-nitride material semiconductor structures
TWI730732B (en) * 2020-04-22 2021-06-11 力晶積成電子製造股份有限公司 Insulating gate field effect bipolar transistor and manufacturing method thereof
US11063141B1 (en) 2020-04-22 2021-07-13 Powerchip Semiconductor Manufacturing Corporation Insulated gate field effect bipolar transistor and manufacturing method thereof

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