GB2555451A - Coated wafer - Google Patents

Coated wafer Download PDF

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Publication number
GB2555451A
GB2555451A GB1618253.7A GB201618253A GB2555451A GB 2555451 A GB2555451 A GB 2555451A GB 201618253 A GB201618253 A GB 201618253A GB 2555451 A GB2555451 A GB 2555451A
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coated wafer
layer
wafer according
principal surface
silicon
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Myronov Maksym
Colston Gerard
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University of Warwick
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University of Warwick
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Priority to PCT/GB2017/053246 priority patent/WO2018078385A1/en
Publication of GB2555451A publication Critical patent/GB2555451A/en
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32—Carbides
    • C23C16/325—Silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

A coated wafer 1 comprising a wafer or substrate 2 having a principal surface 3 and a reverse surface 4 comprising a material or respective materials, such as a silicon, silicon-on-insulator, gallium nitride or sapphire, having a cubic crystal structure, such as a diamond or zinc blend crystal structure, and a melting temperature equal to or greater than 1250 °C. The coated wafer further comprises a layer 5 of 3C-SiC having a thickness of at least 1 nm disposed on the reverse surface 4 or on a dielectric layer supported by the reverse surface 4. The 3-cubic silicon carbide polymorph layer 5 may be mono-crystalline, have a thickness no more than 300 nm and a layer 6 may also be grown using chemical vapour deposition (CVD) on the principal surface 3. The principle surface 3 may be subjected to deposition, etching or implantation. The coated wafer 1 may have a diameter of at least 100 mm.

Description

(71) Applicant(s):
University of Warwick (Incorporated in the United Kingdom)
University House, COVENTRY, CV4 8UW,
United Kingdom (72) Inventor(s):
Maksym Myronov Gerard Colston (74) Agent and/or Address for Service:
Venner Shipley LLP
Byron House, Cambridge Business Park,
Cowley Road, Cambridge, CB4 0WZ, United Kingdom (56) Documents Cited:
GB 2540608 A GB 2495949 A
GB 2484506 A US 5378901 A
US 5247192 A
Journal of Applied Physics 111, no. 5 2012 Zielinski, M., J. F. Michaud, S. Jiao, T. Chassagne, A. E. Bazin, A. Michon, M. Portail, and D.AIquier Experimental observation and analytical model of the stress gradient inversion in 3C-SiC layers on silicon. 053507 (58) Field of Search:
INT CL C23C, H01L
Other: WPI, EPODOC, TXTA, XPESP, XPIOP, XPAIP, XPI3E, XPIEE, XPMISC, OAC, SPRINGER, IP.COM (54) Title of the Invention: Coated wafer
Abstract Title: Coated wafer with 3C-SiC layer (57) A coated wafer 1 comprising a wafer or substrate 2 having a principal surface 3 and a reverse surface 4 comprising a material or respective materials, such as a silicon, silicon-on-insulator, gallium nitride or sapphire, having a cubic crystal structure, such as a diamond or zinc blend crystal structure, and a melting temperature equal to or greater than 1250 °C. The coated wafer further comprises a layer 5 of 3C-SiC having a thickness of at least 1 nm disposed on the reverse surface 4 or on a dielectric layer supported by the reverse surface 4. The 3-cubic silicon carbide polymorph layer 5 may be mono-crystalline, have a thickness no more than 300 nm and a layer 6 may also be grown using chemical vapour deposition (CVD) on the principal surface 3. The principle surface 3 may be subjected to deposition, etching or implantation. The coated wafer 1 may have a diameter of at least 100 mm.
Figure GB2555451A_D0001
x.y
Fig. 1
1Ί
1/1
Figure GB2555451A_D0002
Fig. 1
8-: 2Ί 7Α
J χ-y
Fig. 2
Figure GB2555451A_D0003
Fig. 3
Application No. GB1618253.7
RTM
Date :27 February 2017
Intellectual
Property
Office
The following terms are registered trade marks and should be read as such wherever they occur in this document:
Epsilon (Page 10)
Intellectual Property Office is an operating name of the Patent Office www.gov.uk/ipo
- 1 Coated wafer
Field of the Invention
The present invention relates to a coated wafer, particularly, but not exclusively, a 5 coated silicon wafer or a coated silicon-on-insulator wafer.
Background
Silicon carbide is wide-bandgap compound semiconductor material which is well suited to being used in high-power and high-frequency electronic devices on account of having high values of thermal conductivity, breakdown field and saturation velocity.
Silicon carbide exists in several different crystal forms (or “polytypes”) depending on the sequence in which bi-layers of silicon and carbon stack. Of these polytypes, 3Csilicon carbide (3C-S1C), 4H-silicon carbide (4H-S1C) and 6H-silicon carbide (6H-S1C) are most commonly used in electronic devices.
4H- and 6H-SiC substrates are commercially available and high-quality homoepitaxial layers of 4H- and 6H-SiC can be grown on these types of substrates. However, 4H- and 6H-SiC substrates are much more expensive to produce than silicon substrates and are much smaller.
Although 3C-S1C substrates are not available, heteroepitaxial 3C-S1C can be grown on silicon. This allows larger, cheaper silicon wafers to be used. Currently, however, hotwall chemical vapour deposition (CVD) reactors are used to grow 3C-S1C epitaxial layers on silicon. High-temperature cold-wall CVD reactors have purportedly been used to grow 3C-SiC epitaxial layers on silicon, although it is unclear how temperatures exceeding i,3OO°C can be achieved in such reactors without damaging the reactor or component lying inside the reactor.
Moreover, most, if not all, of the research into 3C-SiC/Si heteroepitaxy tends to be conducted on small substrates, such as 50 mm-diameter wafers or 10 mm dies. This can give a misleading impression of whether or not a given heteroepitaxial process has been successful and suitable for production since it is easier to achieve a uniform temperature across a small substrate. Thus, small heterostructures may not reveal problems regarding lack of uniformity across the wafer, voiding, and wafer bow.
For example, R. Anzalone et al.: “Heteroepitaxy of 3C-S1C on different on-axis oriented silicon substrates”, Journal of Applied Physics, volume 105, page 084910 (2009) describes growing epitaxial films on 2-inch silicon wafers in a hot-wall, low-pressure chemical vapour (LPCVD) reactor using trichlorosilane (SiHCl3) as a silicon supply, ethylene (C2H4) as a carbon supply and hydrogen (H2) as a carrier gas at a growth temperature of 1350 °C. A hot-wall CVD reactor tends to have a low throughput and requires regular, costly maintenance.
Wei-Yu Chen et al. :“Crystal Quality of 3C-S1C Influenced by the Diffusion Step in the 10 Modified Four-Step Method”, Journal of The Electrochemical Society, volume 157, pages H377-H380 (2010) describes growing epitaxial films on 1 cm x cm substrate in a horizontal, cold-wall-type LPCVD system using silane (SiH4) as a silicon supply, propane (C3Hs) as a carbon supply and hydrogen (H2) as a carrier gas at a growth temperature of 1420 °C. Although a cold-wall reactor is used, a complex 3- or 4-step deposition process is used, employing temperatures which are close to melting point of silicon. However, it is unclear if the process is repeatable, can be achieved without damaging the chamber and components inside the chamber, and can be used to produce high volumes of large-diameter wafers.
Y. Gao et al: “Low-temperature chemical-vapor deposition of 3C-SiC films on Si(ioo) using SiH4-C2H4-HCl-H2”, Journal of Crystal Growth, volume 191, pages 439 to 445 (1998) describes deposition of 3C-SiC films on silicon using HCI to suppress pure silicon nucleation. The paper, however, omits several details, such as wafer offcut and size, and does not mention whether the substrate suffers from warp or bow after deposition. Furthermore, the SiC films appear to be very rough. From micrographs shown in the paper, RMS surface roughness values of SiC films appear to be several hundreds of nanometres. Moreover, although using a higher concentration of HCI appears to improve crystal quality, it reduces growth rate and if HCI is omitted, then the SiC films are polycrystalline.
-3Summary
According to a first aspect of the present invention there is provided a coated wafer comprising a wafer having a principal surface (that is, the surface which will be processed to form semiconductor devices) and a reverse surface comprising a material or respective materials having a cubic crystal structure and a melting temperature equal to or greater than 1,250 °C and a layer of 3C-SiC having a thickness of at least 1 nm disposed on the reverse surface or on a dielectric layer supported by (for example, disposed on) the reverse surface.
Thus, the 3C-S1C layer need not be necessarily used to form part of a device, but can be used solely or at least in part as a protective layer which can be processed using CMOS and other semiconductor fab processing techniques, i.e. industrial-scale processes.
During or after processing of the wafer, the protective 3C-S1C layer maybe removed, although it need not necessarily be removed since it can serve as a heat management layer due to the fact that 3C-SiC has a greater thermal conductivity than, for example, silicon or silicon dioxide.
The cubic crystal structure maybe a diamond crystal structure. For example, silicon and silicon-germanium have a diamond cubic crystal structure. The cubic crystal structure may be a zinc blende crystal structure. For example, gallium arsenide and other III-V semiconductors have a zinc blende crystal structure.
The 3C-SiC layer maybe monocrystalline, for example, if the 3C-SiC layer is grown on silicon or other suitable material.
The principal and reverse surfaces may comprise the same material.
The wafer may comprise a multilayer wafer, such as, for example, silicon-on-insulator, silicon-on-sapphire, gallium nitride on silicon, silicon-germanium-on-silicon and the like.
Preferably, all of the materials in the wafer have a melting temperature equal to or greater than 1,250 °C.
-4The wafer may be a silicon or silicon-on-insulator wafer. Thus, the principal surface may be a principle silicon surface and the reverse surface may be a reverse silicon surface.
The wafer may be a gallium nitride wafer or a gallium nitride on silicon wafer.
The wafer maybe a sapphire wafer or silicon on sapphire wafer.
The dielectric layer may be a layer of silicon dioxide (Si02), silicon nitride (Si3N4) or 10 other dielectric material having melting temperature equal to or greater than 1,250 °C.
If the 3C-SiC layer is disposed on a dielectric layer, then the 3C-SiC layer is not monocrystalline (that is, it maybe polycrystalline and/or amorphous).
The layer of 3C-SiC on the reverse surface preferably has a thickness no more than 300 15 nm. The layer of 3C-S1C on the reverse surface coats preferably at least 60%, more preferably at least 80% and still more preferably all of the reverse surface.
The coated wafer may further comprise a layer of 3C-S1C on the principal surface having a thickness of at least 1 nm. The layer of 3C-S1C on the principal surface preferably has a thickness no more than 300 nm. The layer of 3C-SiC on the principal surface is preferably monocrystalline.
The layer of 3C-SiC on the principal surface may coat at least 60%, more preferably at least 80% and still more preferably all of the principal surface.
The coated wafer may further comprise at least one window in the layer of 3C-SiC on the principal which exposes at least a portion of the principal surface.
The principal surface maybe substantially flat, i.e. without features resulting from 30 processing. The principal surface may be substantially unprocessed. Thus, the wafer may be provided in a blank form ready for CMOS or other semiconductor processing.
The coated wafer may further comprise at least one layer of silicon or dielectric material on the principal surface and/or one etched step in the principal surface. Thus, the wafer may be provided in part-processed form. The principal surface may have been subjected to at least one deposition, etching or implantation processing step.
-5The coated wafer may have a diameter of at least 100 mm, at least 200 mm or at least 450 mm.
According to a second aspect of the present invention there is provided a coated wafer comprising a wafer having a principal surface and a reverse surface comprising a material or respective materials having a cubic crystal structure and a melting temperature equal to or greater than 1,250 °C and a layer of 3C-SiC having a thickness of at least 1 nm on the reverse surface or on a dielectric layer supported by the reverse surface.
According to a third aspect of the present invention there is provide a set of coated wafers according to the first or second aspect of the invention.
According to a fourth aspect of the present invention there is provided package comprising a wafer carrier, such as a cassette, and one or more coated wafers according to the first or second aspect of the invention removably housed in the wafer carrier.
According to a fifth aspect of the present invention there is provided a method of fabricating a coated wafer. The method comprises providing a wafer having a principal surface and a reverse surface comprising a material having a cubic crystal structure, such as a diamond or zinc blend crystal structure, and a melting temperature equal to or greater than 1,250 °C and providing a layer of 3C-SiC having a thickness of at least 1 nm on the reverse surface or on a dielectric layer supported by (for example, disposed on) the reverse surface. The layer preferably has a thickness no more than 300 nm.
Providing the 3C-SiC layer comprises forming the 3C-SiC layer by growing epitaxial 3CSiC on the reverse surface. The method comprises providing the wafer, such as a silicon or silicon-on-insulator wafer, in a cold-wall chemical vapour deposition reactor. The method comprises heating the wafer to a temperature equal to or greater than 700 °C and equal to or less than 1200 °C and introducing a gas mixture into the reactor, while the substrate is at the temperature, so as to deposit an epitaxial layer of 3C-SiC on the reverse silicon surface of the wafer. The gas mixture comprises a silicon source precursor, a carbon source precursor and a carrier gas.
-6The method may further comprise providing a layer of monocrystalline 3C-S1C layer having a thickness of at least 1 nm on the principal surface of the wafer. The layer preferably has a thickness no more than 300 nm.
The 3C-S1C growth rate may be at least 1 pm/h. The growth rate may be at least 10 pm/h. The growth rate may be up to 20 pm/h or more. However, lower growth rates can be used, for example, to grow thin layers (e.g. < 100 nm) of 3C-S1C.
The carbon source precursor maybe an organosilicon compound. The carbon source 10 precursor may be a methyl-containing silane. Preferably, the carbon source precursor is trimethylsilane (C3Hi0Si).
The silicon source precursor and carbon source precursor are preferably different, i.e. a single precursor serving as both silicon and carbon sources is not used.
The carbon source precursor may have a flow rate of at least 1 seem or at least 10 seem.
The silicon source precursor may be a silane, or a chlorine-containing silane.
Preferably, the silicon source precursor is dichlorosilane (SiH2Cl2). The silicon source precursor may be trichlorosilane. The silicon source precursor may comprise first and second precursor components. For example, the silicon source precursor may comprise a mixture of gases, such as silane or disilane and hydrogen chloride (HC1).
The silicon source precursor may have a flow rate of at least 1 seem or at least 10 seem.
The carrier gas is preferably hydrogen (H2).
The carrier gas may have a flow rate of at least 1 seem or at least 10 seem.
The ratio of the flow rate of the carbon source precursor and the silicon source precursor may be less than 3 and greater than 0.33. The ratio of the flow rate of the carbon source precursor and the silicon source precursor may be less than 2 and greater than 0.5. The flow rates of the carbon source precursor and the silicon source precursor may be the same or substantially the same (e.g. ratio of the flow rate of the carbon source precursor and the silicon source precursor is less than 1.2 and greater than 0.8).
-ΊThe gas mixture preferably consists of a silicon source precursor, a carbon source precursor and a carrier gas or a silicon source precursor, a carbon source precursor, a carrier gas and a dopant source precursor.
The gas mixture preferably excludes (i.e. does not include or consist of) hydrogen chloride (HC1) gas.
The temperature may be equal to or greater than 900 °C, equal to or greater than 900 °C, or equal to or greater than 1000 °C. The temperature is preferably equal to or greater than 1100 °C.
Pressure in the reactor during deposition maybe equal to or greater than 66.7 Pa (0.5 Torr) and equal to or less than 26.7 kPa (200 Torr) or equal to or less than 80 kPa (600
Torr), i.e. sub-atmospheric chemical vapour deposition. Pressure in the reactor during deposition is equal to or greater than 13.3 kPa (too Torr) and equal to or less than 13.3 kPa (760 Torr).
The principal surface and/or reverse surface may have an (001) surface orientation.
The principal surface and/or reverse surface may have a (110) orientation. The principal surface and/or reverse surface may have a (111) orientation. An epilayer of 3C-SiC having (111) orientation (i.e. grown on (111) Si) can used as a substrate for gallium nitride (GaN) overgrowth.
Preferably, the principal surface and/or reverse surface is/are flat, i.e. unpatterned.
The principal surface and/or reverse surface maybe on-axis. The principal surface and/or reverse surface maybe off-axis.
For a wafer having a diameter of at least 100 mm, there is substantially no wafer bow.
The principal surface and/or reverse surface may have an RMS surface roughness, measured by AFM, equal to or less than 20 nm and preferably equal to or less than 10 nm.
The wafer may have a diameter which is at least too mm, at least 200 mm or at least
450 mm or more. The wafer is preferably a single-crystal wafer. The silicon-oninsulator (SOI) wafer may be a silicon-on-sapphire (SoS) wafer or other, similar type of
-8substrates.
-9Brief Description of the Drawings
Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
Figure l shows a coated silicon wafer;
Figure 2 shows a coated silicon-on-insulator wafer; and Figure 3 shows a wafer carrier housing coated wafers.
Detailed Description of Certain Embodiments
Referring to Figure 1, a first coated wafer 1 is shown.
The coated wafer 1 comprises a monocrystalline silicon substrate 2 having first and second faces 3,4 (herein referred to as “upper” and “lower” faces or surfaces respectively or “principal” and “reverse” faces or surfaces respectively).
A first layer 5 of monocrystalline 3C-SiC (hereinafter simply referred to as the first 3CSiC layer) having a thickness of at least 1 nm is disposed on the reverse silicon surface
4. The first 3C-SiC layer 5 can have a thickness of at least 5 nm or at least 10 nm. The first 3C-SiC layer 5 can have a thickness of no more than 300 nm or no more than too nm.
Optionally, a second layer 6 of monocrystalline 3C-SiC (hereinafter simply referred to as the second 3C-SiC layer) having a thickness of at least 1 nm may be disposed on the principal silicon surface 3. The second 3C-SiC layer 6 can have a thickness of at least 5 nm or at least 10 nm. The second 3C-SiC layer 6 can have a thickness of no more than
300 nm or no more than too nm.
Referring to Figure 2, a second coated wafer 1’ is shown.
The second coated wafer 1’ is the same as the first coated wafer 1 (Figure 1) except that a silicon-on-insulator wafer 2’ is used instead of a silicon wafer 2. The silicon-oninsulator wafer 2’ includes a silicon handle 7, a buried oxide layer 8 and a silicon cap 9. The silicon-on-insulator wafer 2’ has silicon principal and reverse surfaces 10,11.
As will be now be explained in more detail, the 3C-SiC layer(s) 5, 6 is/are grown by a low-temperature (i.e. below 1200 °C) deposition process in a cold-wall chemical vapour deposition (CVD) reactor of a type normally used in silicon processing.
- 10 Growing qC-SiC on Si
For the coated wafers l, Τ, herein described, crystalline 3C-S1C can be grown on silicon at a temperature below 1200 °C using a cold-wall, reduced-pressure, sub-atmospheric5 pressure or atmospheric press CVD reactor of a type normally used in silicon processing. An example of a suitable reactor system is the ASM Epsilon 2000 RP-CVD system.
Deposition is carried out using a gas mixture consisting of a silicon source precursor, a 10 carbon source precursor, an optional dopant precursor and a carrier gas. A single silicon/carbon precursor is not used. Hydrogen chloride is not included in the gas mixture.
The silicon source precursor takes the form of dichlorosilane (which may be referred to as “DCS”) having a chemical formula SiH2Cl2 and the silicon source precursor takes the form of trimethylsilane (which may be referred to as “TMS”) having a chemical formula C3Hi0Si. An n-type dopant precursor may take the form of arsine (AsH3) or phosphine (PH3) and a p-type dopant precursor may take the form diborane (ΞΕΗβ). Hydrogen gas is used as a carrier gas.
Using these or other similar precursors, crystalline 3C-SiC epilayers can be grown on blank (i.e. unpatterned) silicon substrates, such as on-axis (ooi)-orientated silicon wafers, at a deposition temperature, Tepi, at or below 1,200 °C and growth rates above 10 pm/h can be achieved. If required, lower growth rates can be used.
Examples of other silicon source precursors include other silanes, such as silane (SiH4) or chlorine-containing silanes, such as trichlorosilane (SiHCl3). Examples of other carbon source precursors include methyl-containing silanes, such as methylsilane (CHeSi) or penta-methylene methyl silane (C6Hi4Si).
The on-axis (ooi)-orientated silicon wafer is cleaned and its native surface oxide (not shown) is removed using a hydrofluoric (HF) acid dip. The wafer is loaded into the reactor (not shown) at a standby temperature, TSb, via the load lock at atmospheric pressure. The standby temperature, TSb, is 900 °C. However, the standby temperature,
Tsb, can take a value between room temperature and 1,200 °C.
- 11 Carrier gas, in this case hydrogen, is introduced into the reactor at a flow rate of 10 slm at a pressure 13.3 kPa (100 Torr). The heaters are switched on and are controlled so that the temperature of the wafe2 reaches and is maintained at a set-point temperature, which in this case is 1,190 °C.
A mixture of dichlorosilane, trimethylsilane and hydrogen is introduced into the reactor (not shown) having flow rates of 10 seem, 10 seem and 10,000 seem respectively, while temperature is maintained at 1,190 °C and pressure is maintained at 13.3 kPa (100 Torr). Thus, the partial pressures of the dichlorosilane and trimethylsilane are 13.3 Pa,
13.3 Pa respectively. The growth rate for this gas mixture and gas flow rates, and at this temperature and pressure is about 20 pm/h.
The gas mixture continues to flow until the desired thickness of 3C-SiC is grown. Once the desired thickness has been reached, the flow of dichlorosilane and trimethylsilane is stopped, but the carrier gas continues to flow. The heaters are switched off and the 3CSiC/Si wafer is allowed to cool. This can take about 5 to 10 minutes. Once the wafer has cooled, carrier gas flow is stopped and the reactor purged. The 3C-SiC/Si wafer is then removed from the reactor.
The process can be modified by forming in-situ a thin seed layer (not shown) prior to epitaxy. The seed layer (not shown) comprises a layer of silicon-carbon (Sii-xCx where x is about 0.01) having a thickness of up to 10 nm.
After loading the wafer into the reactor at a standby temperature, Tsb, via the load lock at atmospheric pressure, the wafer is cooled to about 600 °C. A short deposition cycle (e.g. lasting a few minutes) using the same precursors, same flow rates and same pressure is carried out. Due to the lower temperature, however, the process does not result in epitaxy.
Without wishing to be bound by theory, the seed layer (not shown) is thought to help prevent the formation of voids at the surface of the silicon during epitaxy.
No wafer bow can be observed in a 3C-SiC/Si heterostructure 1 comprising a 3C-SiC epilayer grown on a 100 mm-diameter (100) orientation, on-axis single-crystal silicon wafer at 1,190 °C using dichlorosilane and trimethylsilane using the process
- 12 hereinbefore described. Furthermore, the 3C-SiC/Si heterostructure has an RMS surface roughness of (to ± 1) nm as measured using an atomic force microscope.
Referring also to Figure 3, the coated wafers 1,1’ can be transported to or from a fab 5 (not shown) or within the fab (not shown) using a wafer carrier 10 having a cassette 11 for holding a set of one or more coated wafers 1,1’.
Modifications
It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known in wafer processing and in heteroepitaxy which may be used instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.
For example, the wafer need not be a silicon or silicon-on-insulator wafer, but may be another suitable type of wafer comprising cubic crystal structure material(s), for example, wafers such as a GaN wafer or a GaN on silicon wafer, or sapphire wafer.
Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features disclosed herein either explicitly or implicitly or any generalization thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.
The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims (20)

  1. Claims
    l. A coated wafer comprising:
    a wafer having a principal surface and a reverse surface comprising a material or 5 respective materials having a cubic crystal structure and a melting temperature equal to or greater than 1,250 °C; and a layer of 3C-SiC having a thickness of at least 1 nm disposed on the reverse surface or on a dielectric layer supported by the reverse surface.
    10
  2. 2. A coated wafer according to claim 1, wherein the cubic crystal structure is a diamond crystal structure or a zinc blend crystal structure.
  3. 3. A coated wafer according to claim 1 or 2, wherein the wafer is a silicon or siliconon-insulator wafer.
  4. 4. A coated wafer according to claim 1 or 2, wherein the wafer is a gallium nitride wafer.
  5. 5. A coated wafer according to claim 1 or 2, wherein the wafer is a sapphire wafer.
  6. 6. A coated wafer according to any preceding claim, wherein the layer of monocrystalline 3C-SiC on the reverse surface has a thickness no more than 300 nm.
  7. 7. A coated wafer according to any preceding claim, wherein the layer of
    25 monocrystalline 3C-S1C on the reverse surface coats at least 60% of the reverse surface.
  8. 8. A coated wafer according to claim 7, wherein the layer of monocrystalline 3C-SiC on the reverse surface coats at least 80% of the reverse surface.
    30
  9. 9. A coated wafer according to claim 8, wherein the layer of monocrystalline 3C-SiC on the reverse surface coats all of the reverse surface.
  10. 10. A coated wafer according to any preceding claim, further comprising:
    a layer of monocrystalline 3C-SiC on the principal surface having a thickness of at
    35 least 1 nm.
    -1411. A coated wafer according to claim to, wherein the layer of monocrystalline 3CSiC on the principal surface has a thickness no more than 300 nm.
  11. 12. A coated wafer according to claim 10 or 11, wherein the layer of monocrystalline 5 3C-S1C on the principal surface coats at least 60% of the principal surface.
  12. 13. A coated wafer according to claim 12, wherein the layer of monocrystalline 3C-SiC on the principal surface coats at least 80% of the principal surface.
    10
  13. 14. A coated wafer according to claim 13, wherein the layer of monocrystalline 3C-SiC on the principal surface coats all of the principal surface.
  14. 15. A coated wafer according to any one of claims 10 to 14, further comprising at least one window in the layer of monocrystalline 3C-SiC on the principal surface which
    15 exposes at least a portion of the principal surface.
  15. 16. A coated wafer according to any one of claims 1 to 15, wherein the principal surface is substantially flat.
    20
  16. 17. A coated wafer according to any one of claims 1 to 16, wherein the principal surface is substantially unprocessed.
  17. 18. A coated wafer according to any one of claims 1 to 15, further comprising at least one layer of semiconductor material or dielectric material on the principal surface
    25 and/or one etched step in the principal surface.
  18. 19. A coated wafer according to any one of claims 1 to 15 or 18, wherein the principal surface has been subjected to at least one deposition, etching or implantation processing step.
  19. 20. A coated wafer according to any preceding claim, wherein the coated wafer has a diameter of at least too mm.
  20. 21. A coated wafer according to any preceding claim, wherein the coated wafer has a 35 diameter of at least 200 mm.
    -1522. A coated wafer according to any preceding claim, wherein the coated wafer has a diameter of at least 450 mm.
    23· A set of coated wafers according to any preceding claim. 5 24. A method of semiconductor processing comprising: receiving a coated wafer according to any one of claims 1 to 22; and performing a plurality of processing steps on the coated wafer so as to form
    semiconductor devices.
    Intellectual
    Property
    Office
    Application No: GB1618253.7 Examiner: Dr Thomas Martin
GB1618253.7A 2016-10-28 2016-10-28 Coated wafer Withdrawn GB2555451A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247192A (en) * 1991-09-30 1993-09-21 Rohm Co., Ltd. Heterojunction bipolar transistor
US5378901A (en) * 1991-12-24 1995-01-03 Rohm, Co., Ltd. Heterojunction bipolar transistor and method for producing the same
GB2484506A (en) * 2010-10-13 2012-04-18 Univ Warwick Heterogrowth
GB2495949A (en) * 2011-10-26 2013-05-01 Anvil Semiconductors Ltd Epitaxially deposited silicon carbide
GB2540608A (en) * 2015-07-23 2017-01-25 Univ Warwick Growing epitaxial 3C-SiC on single-crystal silicon

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Publication number Priority date Publication date Assignee Title
US9515222B2 (en) * 2011-10-26 2016-12-06 Anvil Semiconductors Limited Gallium nitride on 3C—SiC composite wafer

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Publication number Priority date Publication date Assignee Title
US5247192A (en) * 1991-09-30 1993-09-21 Rohm Co., Ltd. Heterojunction bipolar transistor
US5378901A (en) * 1991-12-24 1995-01-03 Rohm, Co., Ltd. Heterojunction bipolar transistor and method for producing the same
GB2484506A (en) * 2010-10-13 2012-04-18 Univ Warwick Heterogrowth
GB2495949A (en) * 2011-10-26 2013-05-01 Anvil Semiconductors Ltd Epitaxially deposited silicon carbide
GB2540608A (en) * 2015-07-23 2017-01-25 Univ Warwick Growing epitaxial 3C-SiC on single-crystal silicon

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* Cited by examiner, † Cited by third party
Title
Journal of Applied Physics 111, no. 5 2012 Zielinski, M., J. F. Michaud, S. Jiao, T. Chassagne, A. E. Bazin, A. Michon, M. Portail, and D.Alquier "Experimental observation and analytical model of the stress gradient inversion in 3C-SiC layers on silicon." 053507 *

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