US8773345B2 - Field-effect transistor shift register - Google Patents

Field-effect transistor shift register Download PDF

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US8773345B2
US8773345B2 US13/057,538 US200913057538A US8773345B2 US 8773345 B2 US8773345 B2 US 8773345B2 US 200913057538 A US200913057538 A US 200913057538A US 8773345 B2 US8773345 B2 US 8773345B2
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transistor
stage
node
output
source
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US20110134107A1 (en
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Hugues Lebrun
Thierry Kretz
Chantal Hordequin
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InterDigital CE Patent Holdings SAS
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Thales SA
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET

Definitions

  • the present invention relates to an optimized field-effect transistor shift register, particularly suitable for controlling the selection lines of an active matrix of a flat screen such as a liquid crystal or OLED (organic light-emitting diode) screen.
  • a flat screen such as a liquid crystal or OLED (organic light-emitting diode) screen.
  • each image dot is addressed by means of a switching transistor.
  • Each selection line of the matrix is thus connected to the gates of the switching transistors of a row of image dots. These lines are therefore strongly capacitive.
  • On each video frame they are each selected in sequence, one by one, in a direction of scanning of the lines of the screen, during a line selection time corresponding to a fraction of the duration of the frame, enabling the video voltages to be applied to the image dots of the row.
  • the selection of a line thus corresponds to the application, during the corresponding line selection time, of a predetermined voltage level which controls the passing state of the switching transistors of the corresponding row of image dots. Outside the line selection time, said line is held at a voltage level capable of holding the switching transistors of the active matrix in the blocked state.
  • Vgon and Vgoff are usually used to denote the voltage levels to be applied to the line to make these transistors passing (Vgon) and blocked (Vgoff). These levels are determined according to characteristic video voltages.
  • the selection lines are usually controlled by circuits that include one or more shift registers in series, each having a plurality of cascaded stages, each stage being capable of switching the levels Vgon and Vgoff at the output to a corresponding line of the matrix, according to the sequencing of the selection of the lines.
  • TFT thin-film field-effect transistors
  • Patent Application EP 0815 562 discloses a shift register structure with a small number of field-effect transistors, of the same polarity and with a small footprint. This structure leads to a low duty cycle for the transistors, and is also designed to limit the voltage levels that are applied to them. In particular, when a stage is not active, its transistors have their gate-source voltage below or equal to zero. These transistor control conditions make it possible to improve their lifespan.
  • this structure is based on the use, in each stage of an output transistor able to conduct a sufficient current to charge the output capacitive line, associated with a “bootstrap” capacitor, connected between its gate and its source.
  • the drain of the output transistor receives a clock signal; its source forms the output node on a line of the active matrix; its gate is controlled by the bias of a precharging transistor, which brings the gate to a precharging potential making it possible to control the passing state of the output transistor at the input in the line selection phase.
  • the gate of the output transistor then follows the potential of its source via the bootstrap capacitor, which holds the transistor in the passing state throughout the line selection phase.
  • the gate precharging potential is determined so that the output transistor conducts an output current of sufficient level to transfer a pulse of the clock signal applied to its drain, to its source which forms the output node.
  • the gate of the output transistor is also controlled by a discharge transistor activated after the line selection phase, to bring the gate of the output transistor to a voltage level enabling it to be blocked.
  • this structure is advantageous in that it requires only a small number of transistors, controlled with a low duty cycle and low voltage levels, optimized with respect to the levels Vgon and Vgoff to be applied to the output, it does, however, exhibit a sensitivity to the drift in the threshold voltage of the output transistor, which limits its lifespan.
  • the gate potential increases with the source potential, by bootstrap effect from the capacitor connected between the gate and the source. If V 1 is used to denote the precharging potential of the gate at the input in the selection phase, the gate potential then increases by a quantity Va proportional to the voltage at the output node Vgon.
  • the gate-source voltage Vgs seen by the output transistors during each line selection phase is thus greater than the threshold voltage of the transistor. Over time, it induces a drift in the threshold voltage, which can reach ten or so volts.
  • the precharging voltage level V 1 applied by the precharging transistor is equal to the level Vgon supplied by the output node of the preceding stage, during the associated line selection time, minus the threshold voltage of the precharging transistor.
  • the level Vgon that has to be overevaluated, according to the lifespan sought, to take account of the drift over time of the threshold voltage of the output transistors.
  • a transistor whose threshold voltage at the start of life is of the order of 1 or 2 volts, can have its threshold voltage drift by approximately 13 volts.
  • a voltage Vgon of the order of 20 volts can be chosen, whereas at the start of life, a voltage Vgon of the order of 7 volts would have been sufficient.
  • the output transistor is then extremely conductive. The excessive output current tends to accelerate the speed with which the threshold voltage of the output transistor will drift. Its lifespan is hence diminished.
  • the object of the invention is to improve the lifespan of the shift registers.
  • One idea on which the invention is based is to improve the control of their output transistors, by adapting the precharging voltage level of their gate, to their level of conduction, that is to say, to their threshold voltage, so that it is less high at the start of life than at the end of life. Consequently, in the line selection phase, the gate-source voltage of the output transistor will be lower at the start of life than at the end of life, and adapted to the correct conduction level of the output transistor.
  • the technical solution provided by the invention lies in the use, for each output transistor, of a transistor of the same technology, produced at the same time as it, and whose threshold voltage will drift over time at least as quickly as its own, to adapt the level of the precharging voltage to its threshold voltage.
  • the invention provides a shift register produced using field-effect transistors of the same polarity, the shift register including a plurality of cascaded identical stages, the stages of even rank receiving a clock signal and the stages of odd rank receiving a complementary clock signal and the stages being sequenced to transmit, one after the other, a clock pulse to an output node, during a corresponding line selection phase, each stage including:
  • Each stage includes an additional transistor of the same technology and of the same polarity as the output transistor, the drain of which is connected to the internal node, and the source of which is biased to an output transistor blocking voltage at least during the precharging phase, and the function of which is to adjust the voltage to the internal node according to the conduction performance characteristics of the output transistor during the precharging and/or phase of selection of the stage.
  • the optimization of the precharging voltage to the level of conduction of the output transistor obtained applies throughout the period of use, from start to end of life: as the circuit is used, the additional transistor becomes increasingly less active to limit the precharging voltage. It will be shown that this optimization also applies for the usage temperature.
  • the invention applies to an active matrix flat screen.
  • it allows for the integration, on one and the same substrate, and with the same transistor technology, of the matrix and of the control circuit of the selection lines.
  • FIG. 1 is a general diagram of a line control shift register of an active matrix
  • FIG. 2 a details a structure of a stage of a shift register according to the state of the art, to which the invention can be applied;
  • FIG. 2 b is a timing diagram of the signals illustrating the operation of such a register
  • FIG. 3 illustrates a first embodiment of a stage of such a shift register according to the invention
  • FIG. 4 shows the different curves of the voltage at the gate node of the output transistor of a stage at the start of life and at the end of life, according to the state of the art and according to the invention
  • FIG. 5 illustrates a second embodiment of the invention
  • FIG. 6 illustrates a variant of this embodiment
  • FIG. 7 illustrates a third embodiment of the invention
  • FIG. 8 illustrates a control variant applicable to the various embodiments of the invention illustrated in FIGS. 3 , 5 and 6 ;
  • FIG. 9 diagrammatically illustrates an active matrix substrate with integrated control circuits.
  • the invention applies generally to the shift registers produced using field-effect transistors of the same polarity. It is described more particularly, without being limited thereto, in the context of registers that use thin-film transistors TFT, for example based on amorphous silicon, particularly advantageous for controlling the active matrix selection lines of a flat screen.
  • a shift register comprises N cascaded identical stages E 1 to E N .
  • the stages of even rank E 1 , E n ⁇ 1 , E n+1 , . . . E N receive a clock signal Ck 1 .
  • the stages of odd rank E 2 , E n receive a complementary clock signal Ck 2 .
  • the high and low levels of these clock signals are the levels Vgon and Vgoff. They are illustrated in FIG. 2 b.
  • the first stage E 1 receives a line scanning signal IN (vertical scan) transmitting a clock pulse for each new video frame F to be displayed.
  • This pulse of the signal IN will be “propagated” to the output S 1 of the first stage E 1 , then from line to line, on the outputs of the stages E 1 , E 2 , . . . E n , . . . E N , so that the lines R( 1 ) to R(N) are selected one after the other, during a corresponding line selection phase, ⁇ t 1 , ⁇ t 2 , . . . ⁇ t n , . . . ⁇ t N , once per frame F.
  • a basic structure of a stage E n of such a shift register comprises ( FIG. 2 a ):
  • the transistors T 1 and T 2 are advantageously controlled (by their gate), the first, T 1 , by the signal supplied by the output node S n ⁇ 1 of the preceding stage E n ⁇ 1 or by the line scanning signal IN in the case of the transistor T 1 of the first stage E 1 ( FIG. 1 ), the second, T 2 , by the signal supplied by the output node S n+1 of the next stage E n+1 or by an end-of-line scanning signal R_last in the case of the transistor T 1 of the last stage E N ( FIG. 1 ).
  • the gate g 1 and the drain d 1 of the transistor T 1 are connected in common to the output node Sn ⁇ 1.
  • the transistor T 2 has its gate connected to the output node S n+1 , its drain d 2 to the internal node P n , and its source to a blocking voltage denoted V B .
  • another transistor T 4 is also generally provided, connected to the output node S n and with its source connected to the blocking voltage of the switching transistors of the matrix, that is to say, Vgoff. Its gate is connected to the output node S n+1 of the next stage R(n+1). Its function is to facilitate the discharging of the output node S n , at the end of the line selection phase, by pulling it to Vgoff.
  • the blocking voltages V B and Vgoff are not necessarily equal and can be brought by separate power supply buses, in particular for isolation purposes.
  • a capacitor C 1 is used for this function, connected to the internal node P n and controlled by the complementary clock signal of the clock signal applied to the drain d 3 of the output transistor, therefore Ck 1 in the example.
  • the roles of the clock signals Ck 1 and Ck 2 are exchanged: for example, in the stages E n ⁇ 1 and E n+1 , the transistor T 3 receives the signal Ck 1 and the capacitor C 1 receives the clock signal Ck 2 (not illustrated).
  • FIG. 2 b is a timing diagram showing the different signals involved.
  • the clock signals Ck 1 and Ck 2 are complementary, i.e. in phase opposition.
  • the selection phase ⁇ t n ⁇ 1 of the line R(n ⁇ 1) begins at the time t n ⁇ 1 and ends at the time t n .
  • the selection phase ⁇ t n of the line R(n) begins at the time t n and ends at the time t n+1 , and so on.
  • the clock signals Ck 1 and Ck 2 are respectively in the high state Vgon and in the low stage Vgoff.
  • the output node S n+1 of the next line rises, making the transistors T 2 and T 4 of the stage E n passing: the internal node P n and the output node S n are each pulled to a blocking voltage, respectively V B and Vgoff.
  • the capacitor C 2 is discharged.
  • the line R(n) is deselected.
  • the scanning sequence of the lines of the matrix begins with the activation of the scanning control signal IN, which precharges the internal node P 1 of the first stage.
  • the signal R_last is used to discharge the internal node P N and the output node S N of the last stage, marking the end of the selection phase of the associated line R(N) and the end of the video frame.
  • the line scan recommences on the first line, for the next video frame.
  • a transistor T 5 is used in each stage that is of the same technology and of the same polarity, manufactured during the same manufacturing steps as the output transistor T 3 , so that it has substantially the same threshold voltage at the start of life (technological deviations apart) as this output transistor, to adapt the gate voltage of this output transistor to its conduction performance characteristics, during the precharging and/or selection phase of the stage concerned.
  • each stage E n of the shift register comprises an additional transistor, that will be denoted T 5 , of the same technology, of the same polarity as the output transistor T 3 .
  • the drain d 5 of this additional transistor is connected to the internal node P n , and its source s 5 is connected to a blocking voltage for the output transistor T 3 at least in the precharging phase.
  • the function of this additional transistor is to adjust the voltage to the internal node P n , which is connected to the gate of the output transistor T 3 , according to the conduction performance characteristics of said output transistor T 3 , during the precharging and/or selection phase of the stage concerned.
  • connections of the transistor T 5 provide polarization conditions such that its threshold voltage drifts at least as quickly as that of the output transistor, which is used to adapt the precharging voltage to the conduction conditions of the output transistor.
  • FIG. 3 illustrates a first embodiment.
  • the drain d 5 of the additional transistor T 5 is connected to the internal node P n
  • the source s 5 is linked to the source s 3 of the output transistor T 3 .
  • the gate g 5 of the transistor T 5 is linked to the gate g 3 of the transistor T 3 (at the node P n ).
  • the transistor T 5 is polarized with the same gate-source voltage as the output transistor T 3 , throughout the duration of the frame: its threshold voltage drifts like that of the output transistor T 3 .
  • adapting the precharging voltage level according to the threshold voltage of the transistor T 5 is equivalent to adapting the level of the precharging voltage according to the threshold voltage of the transistor T 3 : the transistor T 5 is used as a measure of the variation of the threshold voltage of the output transistor T 3 , to adapt the level of the precharging voltage.
  • the less the transistor T 3 is able to conduct the less the transistor T 5 conducts and the less it discharges the gate, so as to enable the conduction of the transistor T 3 to be maintained.
  • the threshold voltage of the transistors T 3 and T 5 is at its nominal value, specific to the technology. It is, for example, 1 or 2 volts.
  • Vgon is applied to the drain d 1 of the transistor T 1 (node S n ⁇ 1 ) and Vgoff is applied to the source of the transistor T 5 (node S n ).
  • the transistor T 1 starts to conduct, and causes the voltage to rise at the node P n .
  • the transistor T 5 At the start of life, the transistor T 5 will start to conduct rapidly, as soon as the voltage at the node P n exceeds its threshold voltage. It becomes more and more conductive as the node P n rises. The current drawn by the transistor T 5 therefore tends to slow down the rising of the node P n .
  • T 1 and T 5 which conduct in series, thus form a divider bridge at the node P n between Vgon and Vgoff.
  • the two precharging curves V A (P n ) (t) of the node P n with or without transistor T 5 at the start of life are illustrated in FIG. 4 .
  • the node P n rises to V 1 .
  • the rise of the node P n is limited to V 1 ′ ⁇ V 1 .
  • This potential V 1 ′ is sufficient to make the transistor T 3 passing and sufficiently, but not excessively, conductive to transmit the level Vgon of the clock signal applied to its drain, to its source, during the next selection phase ⁇ t n of the line R(n), between t n and t n+1 .
  • the voltage at the node P n rises with the source s 3 of the transistor T 3 (the effect of the capacitor C 2 ), by a quantity Va, which is substantially the same in both cases (with or without T 5 ).
  • the transistor T 5 mounted as a diode continues to conduct, thus continuing to discharge the node Pn and therefore limit the stress.
  • the dimensions of the transistor T 5 are determined so as to no longer influence the charging of the internal node P n at the end of life.
  • the transistor T 5 according to the invention makes it possible to obtain a circuit that has a longer lifespan with constant Vgon, compared to the same circuit without the transistor T 5 .
  • the transistor T 5 also makes it possible to optimize the control of the output transistor T 3 to the temperature conditions.
  • the mobility of the transistors is greater, and the threshold voltage lower than at low temperature.
  • the discharging of the internal node P n will thus be more effective, the mobility of the transistor T 5 being greater and the voltage at the node P n at the end of the precharging will thus be lower, perfectly suited to the threshold voltage of the output transistor.
  • the transistor T 5 At low temperature, the mobility is reduced and the threshold voltage increases.
  • the transistor T 5 With reduced mobility, will be largely ineffective in discharging the internal node P n (high series impedance) which consequently will reach a precharging level at the time t n that is higher, allowing for a better conduction of the output transistor T 3 .
  • the transistors T 3 and T 5 have their gates linked together and their sources linked together: they thus see the same gate-source voltage, regardless of the phase concerned.
  • the drifts of these threshold voltages are substantially identical (technological dispersions apart).
  • the transistor T 5 has its source s 5 not connected to the source s 3 of the output transistor, but to a constant voltage, for blocking the output transistor.
  • the source s 5 is thus connected to the source s 2 of the transistor T 2 .
  • the source s 5 can be polarized to a blocking voltage corresponding to the low voltage level Vgoff of the clock signals, typically by connecting the source s 5 to the source s 4 of the transistor T 4 .
  • the transistors T 3 and T 5 always have their gates g 3 and g 5 connected together, at the same potential; but the source of the transistor T 5 is permanently polarized to a blocking voltage V B , less than or equal to Vgoff, which is the low level of the clock signal, whereas the source of the transistor T 3 is polarized to Vgon during the line selection time ⁇ t n and Vgoff the rest of the time.
  • V B blocking voltage
  • Vgoff the source of the transistor T 3
  • Vgon the line selection time ⁇ t n and Vgoff the rest of the time.
  • the gate-source voltage seen by the transistor T 5 is thus overall higher over the frame time. Its threshold voltage will therefore drift more quickly than that of the transistor T 3 . This makes it possible to adapt the conduction of the transistor T 5 according to the drift in the threshold voltage of T 3 .
  • This variant embodiment makes it possible to make the dimensioning of the transistor T 5 more simple compared to the other transistors of the circuit, because it does not cause any modification of the polarity of the line in the precharging phase (no precharging of the line via the conduction path T 1 -T 5 ) and also because its threshold voltage will drift more quickly.
  • the transistor T 5 has its source s 5 connected to the drain d 3 of the output transistor, that is to say, to the clock signal Ck 2 which drives this drain.
  • its source s 5 In the precharging phase, between t n ⁇ 1 and t n , its source s 5 is thus held at the low level Vgoff of the clock signal Ck 2
  • its selection phase between t n and t n+1 , its source s 5 is thus held at the high level Vgon of the clock signal Ck 2 .
  • the gate-source voltage of the transistor T 5 is substantially equal to that of the transistor T 3 .
  • the source of this transistor T 5 follows the clock signal. The drift in their threshold voltage (i.e. T 3 and T 5 ) will be substantially the same.
  • FIG. 7 Another embodiment is illustrated in FIG. 7 .
  • the gate g 5 of the transistor T 5 is linked to the gate g 1 of the transistor T 1 .
  • the source s 5 of the transistor T 5 is linked to the source s 2 of the transistor T 2 , to the blocking voltage V B of the output transistor T 3 .
  • the source s 5 of the transistor T 5 could also be polarized to the blocking voltage Vgoff of the switching transistors (low level of the clock signals). In the example illustrated, this would typically be obtained by connecting its source s 5 to the source s 4 of the transistor T 4 .
  • the transistor T 5 is activated and blocked at the same time as the transistor T 1 . It is therefore active only in the precharging phase (which is also the selection phase for the preceding line), between the times t n ⁇ 1 and t n .
  • This embodiment makes it simpler to determine the respective sizes of the transistors T 1 and T 5 , to determine the voltage V 1 ′.
  • These respective sizes of the transistors T 1 and T 5 are chosen according to the voltage V 1 ′ that is desired at the node P n at the end of the precharging phase, at the start of life of the circuit.
  • the transistor T 5 is less and less active as the circuit ages.
  • the transistor T 5 is polarized to a gate-source voltage equal to Vgon (voltage on its gate) minus V B , during the time ⁇ t n ⁇ 1 , and to a voltage equal to Vgoff minus V B for the rest of the frame.
  • Vgon voltage on its gate
  • Vgoff voltage on the gate
  • the transistor T 3 is polarized with a gate-source voltage equal to V 1 ′+Va (its gate voltage) minus Vgon (its source voltage). This voltage is less than or equal to that of the transistor T 5 in the active state. For these reasons, the threshold voltage of the transistor T 5 will drift in the same way or more quickly than that of the transistor T 3 .
  • FIG. 8 illustrates a refinement of the invention, applicable to the various embodiments already described. It is explained by referring once again to the embodiment illustrated in FIG. 3 .
  • the drain d 1 of the transistor T 1 is no longer connected to the gate of g 1 . It is linked to the voltage Vgon.
  • This electrical scheme makes it possible to avoid a voltage drop on the output node S n ⁇ 1 of the preceding stage E n ⁇ 1 , when the transistors T 1 and T 5 of the stage E n conduct, in the precharging phase, that is to say when the node S n ⁇ 1 is at Vgon.
  • a power supply bus is then provided in practice to bring the voltage Vgon to each of the stages of the control circuit.
  • the invention makes it possible to increase the lifespan of the screen, by providing better management of the drift in the threshold voltage of the field-effect transistors of the control circuit, regardless of the technology concerned (thin films, MOS, etc.).

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FR0804537 2008-08-08
FR0804537A FR2934919B1 (fr) 2008-08-08 2008-08-08 Registre a decalage a transistors a effet de champ.
PCT/EP2009/060083 WO2010015621A1 (fr) 2008-08-08 2009-08-04 Registre a decalage a transistors a effet de champ

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US9412291B2 (en) 2011-05-13 2016-08-09 Semiconductor Energy Laboratory Co., Ltd. Display device
US20190213970A1 (en) * 2018-01-10 2019-07-11 Boe Technology Group Co., Ltd. Shift register circuit and method of controlling the same, gate driving circuit, and display device
US12027535B2 (en) 2014-07-24 2024-07-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with a capacitor and a plurality of overlapping openings in the conductive layers

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TWI406503B (zh) 2010-12-30 2013-08-21 Au Optronics Corp 移位暫存器電路
KR101102614B1 (ko) 2011-04-12 2012-01-10 한양대학교 산학협력단 플립 플롭 및 그를 포함하는 시프트 레지스터
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TWI508446B (zh) 2015-11-11
KR20110052608A (ko) 2011-05-18
EP2311042B1 (fr) 2018-11-21
WO2010015621A1 (fr) 2010-02-11
JP2011530774A (ja) 2011-12-22
US20110134107A1 (en) 2011-06-09
FR2934919B1 (fr) 2012-08-17
JP5433906B2 (ja) 2014-03-05
TW201021416A (en) 2010-06-01
EP2311042A1 (fr) 2011-04-20
FR2934919A1 (fr) 2010-02-12

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