US8713230B2 - Method for adjusting link speed and computer system using the same - Google Patents

Method for adjusting link speed and computer system using the same Download PDF

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US8713230B2
US8713230B2 US13/212,194 US201113212194A US8713230B2 US 8713230 B2 US8713230 B2 US 8713230B2 US 201113212194 A US201113212194 A US 201113212194A US 8713230 B2 US8713230 B2 US 8713230B2
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target bridge
peripheral device
link speed
bridge
bus
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US20120047308A1 (en
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Kang-Ning FENG
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Pegatron Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • This disclosure relates to a method of adjusting a link speed of a bridge and, more particularly, to a method for automatically adjusting a link speed of a bridge before executing a bus enumeration procedure and a computer system using the same.
  • PCI Express peripheral component interconnect express
  • a bridge is searched by reading its register.
  • the PCIe bridge it provides three registers to indicate buses connected thereto.
  • the three registers are used for storing a primary bus number, a secondary bus number, and a subordinate bus number, respectively.
  • the buses connected with the PCIe bridge can be found via the three numbers.
  • the primary bus number indicates the number of the upstream bus immediately connected with the PCIe bridge.
  • the secondary bus number indicates the number of the downstream bus immediately connected with the PCIe bridge.
  • the subordinate bus number indicates the maximum number among all the downstream bus numbers of the PCIe bridge.
  • FIG. 1A is a schematic diagram showing a PCIe structure.
  • FIG. 1B is a schematic diagram showing bus numbers. Please refer to FIG. 1A and FIG. 1B .
  • a primary bridge 100 is connected with a PCIe bridge 111 via a bus 0
  • the PCIe bridge 111 is connected with a PCIe bridge 121 and a PCIe bridge 131 via a bus 1 .
  • the PCIe bridge 121 and the PCIe bridge 131 are connected with a PCIe device 140 and a PCIe device 150 via a bus 2 and a bus 3 , respectively.
  • the primary bus number of the PCIe bridge 111 is 0 . Since the secondary bus number is the number of the downstream bus immediately connected thereto, here the secondary bus number is 1 . The subordinate bus number is 3 . Similarly, for the PCIe bridge 121 , the primary bus number is 1 . The secondary bus number is the number of the downstream bus immediately connected thereto and therefore it is 2 . The subordinate bus number is 2 . For the PCIe bridge 131 , the primary bus number is 1 . The secondary bus number is the number of the downstream bus immediately connected thereto and therefore it is 3 . The subordinate bus number is 3 . Accordingly, the bus information of the corresponding PCIe bridge can be obtained via reading the aforementioned bus numbers. Further, whether the bridge is connected with a certain peripheral device can be determined via the bus information.
  • PCI Express interface includes different versions such as PCI Express 1.0, PCI Express 2.0, PCI Express 3.0 and so on. These versions define different speed and related communication protocols, respectively, and therefore incompatibility of the link speed may occur due to different versions when a connection is established between the PCI Express bridge and the controller on the add on card. If a valid connection between the add on card and the PCI Express bridge of the chipset fails to be established, the system may fail to recognize and use the add on card and a peripheral controller on the motherboard, and more seriously, the system may be unstable.
  • a basic input/output system for initialization provides two connecting modes. One is directly using hardware in the chipset for connection. However, if the connection fails, only a message indicating a connection error occurs is provided. The add on card work normally fails to be determined until an operating system is loaded. If the add on card fails to work normally, the system has to be rebooted and the link speed has to be forcedly adjusted down via options of the BIOS. The other is forcedly adjusting the link speed to the slowest speed. However, it is also inconvenient.
  • This disclosure provides a method for adjusting a link speed, being capable of automatically selecting a best link speed between a bridge and a peripheral device.
  • the disclosure provides a computer system ensuring that a peripheral device connected with a bridge can be found when a bus enumeration procedure is executed.
  • the embodiment of the invention provides a method for adjusting a link speed used after executing a boot block code and before executing a bus enumeration procedure.
  • the embodiment of the method includes the following steps. At first, a bus information list is read to select a target bridge. If the target bridge is connected with a peripheral device, a maximum link speed supported by both the target bridge and the peripheral device is taken as the link speed between the target bridge and the peripheral device. Then whether the target bridge is capable of accessing the peripheral device is tested. If the target bridge fails to access the peripheral device, the link speed is adjusted down and a connection between the target bridge and the peripheral device is re-established. Afterwards the steps of testing whether the target bridge is capable of accessing the peripheral device and adjusting the link speed down if the target bridge fails to access the peripheral device are re-executed until the target bridge is capable of accessing the peripheral device.
  • the method may further include the following steps.
  • a temporary bus number may be allocated to the target bridge. Whether a bus of the target bridge is connected with the peripheral device may be determined according to the temporary bus number.
  • the step of allocating the temporary bus number to the target bridge may include the step of writing a subordinate bus number and a secondary bus number into respective registers. Further, after the step of testing whether the target bridge is capable of accessing the peripheral device, if the target bridge is capable of accessing the peripheral device, the registers for storing the subordinate bus number and the secondary bus number may be restored.
  • the method may further include the following steps. Whether the target bridge is the last one whose link speed is to be adjusted in the bus information list may be determined. If the target bridge is not the last one whose link speed is to be adjusted in the bus information list, the bus information list may be read to select another target bridge.
  • the embodiment of the invention provides a computer system including a central processing unit (CPU), a control chip, and a basic input/output system (BIOS) unit.
  • the CPU executes a boot block code.
  • the control chip is coupled to the CPU, and the BIOS unit is coupled to the control chip.
  • the BIOS unit executes the following steps.
  • the BIOS unit reads a bus information list to select a target bridge. If the target bridge is connected with a peripheral device, the BIOS unit takes a maximum link speed supported by both the target bridge and the peripheral device as the link speed between the target bridge and the peripheral device. Afterwards the BIOS unit tests whether the target bridge is capable of accessing the peripheral device.
  • the BIOS unit adjusts the link speed down, and after a connection between the target bridge and the peripheral device is re-established, the BIOS unit re-executes the steps of testing whether the target bridge is capable of accessing the peripheral device and adjusting the link speed down if the target bridge fails to access the peripheral device until the target bridge is capable of accessing the peripheral device.
  • the invention automatically adjusts the link speed via the BIOS unit before the bus enumeration procedure is executed, ensuring that the peripheral device connected with the bridge can be found when the bus enumeration procedure is executed. Further, the late allocation of system resource when the computer is booted may not be affected and effect on the booting procedure may be reduced.
  • FIG. 1A is a schematic diagram showing a PCIe structure
  • FIG. 1B is a schematic diagram showing bus numbers
  • FIG. 2 is a block diagram showing a computer system according to one embodiment of the invention.
  • FIG. 3 is a flow chart showing a method for adjusting a link speed of a bridge according to one embodiment of the invention.
  • FIG. 4 is a flow chart showing a method for adjusting a link speed of a bridge according to another embodiment of the invention.
  • the invention provides a method for adjusting a link speed and a computer system using the same.
  • the link speed of the bridge is adjusted when the computer system is booted, thus ensuring compatibility between the computer system and a peripheral device such as an add on card.
  • FIG. 2 is a block diagram showing a computer system according to one embodiment of the invention. Please refer to FIG. 2 .
  • the computer system at least includes a CPU 210 , a control chip 220 , and a BIOS unit 230 .
  • the control chip 220 may be a south bridge chip, a north bridge chip, or a chipset integrating the south bridge chip and the north bridge chip.
  • the BIOS unit 230 may be a read only memory (ROM) or a flash memory for storing basic codes for loading the system, i.e. a BIOS.
  • an algorithm is added into codes of the BIOS unit 230 , thus adjusting a link speed of a bridge via the BIOS unit 230 .
  • the steps of adjusting the link speed of the bridge are executed after the CPU 210 executes a boot block code and before the BIOS unit 230 executes a bus enumeration procedure.
  • the BIOS unit 230 at least executes the following steps.
  • the BIOS unit 230 reads a bus information list to select a target bridge. If the target bridge is connected with a peripheral device, the BIOS unit 230 takes a maximum link speed supported by both the target bridge and the peripheral device as the link speed between the target bridge and the peripheral device. Further, after the target bridge is connected with the peripheral device, the BIOS unit 230 tests whether the target bridge is capable of accessing the peripheral device.
  • the link speed is adjusted to a lower grade, and after a connection between the target bridge and the peripheral device is re-established, the BIOS unit 230 re-executes the steps of testing whether the target bridge is capable of accessing the peripheral device and adjusting the link speed down if the target bridge fails to access the peripheral device until the target bridge is capable of accessing the peripheral device.
  • peripheral devices connected with each bridge can be found when the bus enumeration procedure is executed, and further the peripheral devices can be accessed.
  • FIG. 3 is a flow chart showing a method for adjusting a link speed of a bridge according to one embodiment of the invention. Please refer to FIG. 3 .
  • step S 305 is executed to read a bus information list to select a target bridge.
  • the bus information list can be created according to circuits on a motherboard.
  • the related information about all the bridges on the motherboard can be created in the bus information list.
  • the bus information list records one or a combination of a device ID, a vendor ID, a bus number, a device number, and a function number of each bridge whose link speed is to be adjusted.
  • step S 310 if the target bridge is connected with a peripheral device, a maximum link speed supported by both the target bridge and the peripheral device is taken as the link speed between the target bridge and the peripheral device. After the link speed is determined, a connection between the target bridge and the peripheral device can be established.
  • step S 315 whether the target bridge is capable of accessing the peripheral device is tested. For example, data exchange therebetween may be tested.
  • step S 320 if the target bridge fails to access the peripheral device, the link speed is adjusted to a lower grade, and after a connection between the target bridge and the peripheral device is re-established, step S 315 is re-executed to test whether the target bridge is capable of accessing the peripheral device until the target bridge is capable of accessing the peripheral device.
  • PCI Express peripheral component interconnect express
  • PCIe peripheral component interconnect express
  • the PCIe 1.0 provides a link speed of 2.5 GT/second (gigatransfer per second);
  • the PCIe 2.0 provides a link speed of 5.0 GT/second;
  • the PCIe 3.0 provides a link speed of 8.0 GT/second.
  • the link speed can be defined as a maximum link speed supported by both sides, i.e. 5.0 GT/second.
  • the BIOS executes other initialization procedures including the bus enumeration procedure.
  • FIG. 4 is a flow chart showing a method for adjusting a link speed of a bridge according to another embodiment of the invention. Please refer to FIG. 4 .
  • an algorithm is added into the BIOS to execute the following steps.
  • step S 405 after the CPU executes the boot block code of the BIOS, a bus information list is read to select a PCIe bridge.
  • the bus information list (recording a device ID, a vendor ID, a bus number, a device number, and a function number of each PCIe bridge whose link speed is to be adjusted) can be created in advance according to circuits on a motherboard.
  • a temporary bus number is allocated to the PCIe bridge whose link speed is to be adjusted, and it is written into a bus number register. That is, any bus number except 0 ( 0 is the number of the downstream bus immediately connected with a primary bridge) or other number having special uses can be used as the temporary bus number thus to be written into the register defined in the PCl/PCIe bridge specification.
  • the peripheral device connected with the PCIe bridge i.e. the PCIe device
  • a temporary group of a subordinate bus number and a secondary bus number (such as Offset 1 Ah and Offset 1 Bh) can be written into respective registers.
  • step S 415 the link speed of the PCIe bridge is adjusted to the slowest one.
  • the link speed of the allocated temporary secondary bus of the PCIe bridge is first forcedly adjusted to the slowest one conforming to the PCIe 1.0, and then a PCI Express connection is re-established.
  • Step S 415 is to prevent the peripheral device connected with the bridge from failing to be accessed due to connection mechanism.
  • step S 420 whether a peripheral device is connected with the bus of the PCIe bridge is determined. For example, whether any PCIe device is connected with the bus with the allocated bus number can be determined using a memory mapped I/O (MMIO) or a conventional PCI configuration method. If the peripheral device is absent, step S 425 is executed to restore the bus number register of the PCIe bridge.
  • MMIO memory mapped I/O
  • step S 430 is executed.
  • a maximum link speed supported by both the PCIe bridge and the peripheral device is taken as the link speed between the target bridge and the peripheral device.
  • a maximum link speed supported by the peripheral device can be obtained from a PCI configuration register via software, and then the maximum link speed supported by both the PCIe bridge and the peripheral device is taken for the first test. After the maximum link speed is written into the corresponding register of the PCIe bridge, a connection is re-established.
  • step S 435 is executed to test whether the PCIe bridge is capable of accessing the peripheral device. If the PCIe bridge fails to access the peripheral device, step S 440 is executed to adjust the link speed to a lower grade. Then step S 435 is re-executed until the PCIe bridge is capable of accessing the peripheral device.
  • step S 425 is executed to restore the bus number register of the PCIe bridge.
  • step S 445 whether the PCIe bridge is the last one whose link speed is to be adjusted in the bus information list is determined. If yes, all the adjustment of the PCIe bridges in the computer system has been completed. Then control of the computer system is returned to the BIOS to continue other procedures during POST such as the bus enumeration procedure.
  • step S 405 If not all of the PCIe bridges whose link speeds are to be adjusted have been adjusted yet, the method returns to step S 405 to designate the next PCIe bridge whose link speed is to be adjusted, thus re-adjusting the link speed of another PCIe bridge.
  • the methods in the aforementioned embodiments can be used in a software layer or a firmware of the PCIe structure.
  • an algorithm can be added in the firmware (such as the BIOS) or the software for initializing the computer system, thus adjusting the link speed of the bridge and improving compatibility between the peripheral device (such as an add on card) and the system (such as a server, a notebook computer, a desktop computer, a motherboard, or a barebone system).
  • the peripheral device such as an add on card
  • the system such as a server, a notebook computer, a desktop computer, a motherboard, or a barebone system.
  • This method can benefit all the systems having extensible PCIe slots.
  • the link speed of the bridge can be adjusted. Accordingly, the late allocation of system resource when the computer is booted may not be affected and effect on the booting procedure may be reduced. Further, the connection between the bridge and the peripheral device can be established properly.

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US10678721B1 (en) * 2017-02-02 2020-06-09 Amazon Technologies, Inc. Communication link testing
US11815976B2 (en) * 2019-05-22 2023-11-14 Qualcomm Incorporated Bandwidth based power management for peripheral component interconnect express devices
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