US7973314B2 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- US7973314B2 US7973314B2 US12/117,630 US11763008A US7973314B2 US 7973314 B2 US7973314 B2 US 7973314B2 US 11763008 A US11763008 A US 11763008A US 7973314 B2 US7973314 B2 US 7973314B2
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- 238000004519 manufacturing process Methods 0.000 title description 16
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000009413 insulation Methods 0.000 claims description 84
- 239000010410 layer Substances 0.000 description 169
- 239000004020 conductor Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
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- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device and to a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device having a multi-layered structure of a high voltage circuit and a low voltage circuit and to a method of manufacturing the same.
- SoC system-on-chip
- a memory circuit and an input/output (I/O) operating at high voltage, and a logic circuit operating at low voltage are formed in a single layer.
- the manufacturing of a memory device having such a single-layered structure is complex because a gate oxide layer of the high voltage circuit and a gate oxide layer of the low voltage circuit have different thicknesses.
- a relatively thick gate oxide layer of the high voltage circuit and a relatively thin gate oxide layer of the low voltage circuit are formed by forming an oxide layer on a substrate, removing a portion of the oxide layer, and then forming an oxide layer again on a region from which the portion of the oxide layer was removed.
- An object of the present invention is to provide a small scale semiconductor device by which various different types and/or sizes of memory circuits can be provided along with a universal logic circuit.
- Another object of the present invention is to provide a method by which such a semiconductor device can be manufactured.
- Still another object of the present invention is to provide a semiconductor device having transistors whose gate insulation layers have different thicknesses, and which device is easy to manufacture by virtue of its design.
- another object of the present invention is to provide a method of readily manufacturing a semiconductor device having transistors whose gate insulation layers have different thicknesses.
- a multi-layered system on chip structure having a first layer including a first patterned gate oxide layer, a second layer stacked on the first layer and including a second patterned gate oxide layer, and wherein the thickness of the first patterned gate oxide layer is different from the thickness of the second patterned gate oxide layer.
- a semiconductor device including a logic circuit and a memory circuit stacked one atop the other in respective layers, and a via by which the logic and memory circuits are electrically connected.
- a semiconductor device including a first semiconductor layer made up of a first substrate and a first circuit including a first transistor disposed on the first substrate, a second semiconductor layer made up of a second substrate disposed on the first semiconductor layer and a second circuit including a second transistor disposed on the second substrate, a via by which the first and second circuits are electrically connected, and wherein the thickness of the gate insulation layer of the first transistor is different from the thickness of the gate insulation layers of the second transistor.
- one of the first and second circuits may be a logic circuit, and the other of the first and second circuits may be a memory circuit.
- the logic circuit preferably is a low voltage circuit operating at relatively low voltage
- the memory circuit is preferably a high voltage circuit operating at voltage that is higher than that at which the logic circuit operates.
- the gate insulation layer of the transistor of the logic circuit is thinner than the gate insulation layer of the transistor of the memory circuit.
- the first circuit is the logic circuit and the second circuit is the memory circuit.
- the logic circuit includes insulation covering the first transistor.
- the memory circuit includes a bit line electrically connected to the second transistor, and insulation covering the second transistor and the bit line.
- the via extends through the insulation of the first layer and the second semiconductor substrate.
- the memory circuit may also include a plug extending through the insulation of the second layer and electrically connecting the bit line and the via.
- the memory circuit may include a double well structure, i.e., a first well and a second well disposed in the first well.
- a method of manufacturing a semiconductor device which includes providing a first semiconductor layer having a first circuit, forming a first via hole in the first semiconductor layer to such an extent as to expose an inner region of the first semiconductor layer, providing a second semiconductor layer having a second circuit, forming a second via hole in the second semiconductor layer, stacking the first and second semiconductor layers such that the first via hole is aligned with the second via hole, and filling the first and second via holes to form a via.
- the first semiconductor layer may be provided by fabricating a first transistor on a first semiconductor substrate, and forming a first insulation layer on the first semiconductor substrate so as to cover the first transistor.
- the first via hole is formed to expose a junction region of the first transistor.
- the second semiconductor layer may be provided by fabricating a second transistor on a second semiconductor substrate. Also, the second via hole is formed so as to extend through the second semiconductor substrate. In addition, a second insulation layer is formed on the second semiconductor substrate so as to cover the second transistor. Preferably, the thickness of the gate insulation layer of the second transistor is different from the thickness of the gate insulation layer of the first substrate.
- the first and second via holes may be filled with conductive material to form the via before the second insulation layer is formed.
- a portion of the second insulation layer may be removed to form a via hole exposing the top of the via.
- the via hole in the second insulation layer is filled with conductive material to form a via plug connected to the via.
- the second via hole may be formed after the second insulation layer is formed.
- the second via hole is formed in the second insulation layer and the second substrate.
- a contact hole may be formed in the second insulation layer to expose a junction region of the second transistor.
- the contact hole and the second via hole may be formed sequentially instead of simultaneously. In either case, the contact hole and the second via hole are filled at the same time with conductive material to form a contact plug connected to the junction region of the second transistor, and the via, respectively.
- a bit line, connected to the contact plug and to the via or via plug, may also be formed on the second insulation layer. Then, a third insulation layer may be formed to cover the bit line.
- a method of manufacturing a semiconductor device which includes providing a first semiconductor layer having a first circuit disposed on a first semiconductor substrate, providing a second semiconductor layer having a second circuit disposed on a second semiconductor substrate, forming a via hole which extends in the second semiconductor layer and exposes the first semiconductor substrate, and electrically connecting the first and second circuits including by filling the via hole with conductive material to form a via.
- FIG. 1A is a sectional view of an embodiment of a semiconductor device according to the present invention.
- FIG. 1B is a sectional view of another embodiment of a semiconductor device according to the present invention.
- FIGS. 2A through 2E are sectional views illustrating an embodiment of a method of manufacturing a semiconductor device according to the present invention.
- FIGS. 3A through 3D are sectional views illustrating another embodiment of a method of manufacturing a semiconductor device according to the present invention.
- FIGS. 4A through 4D are sectional views illustrating yet another embodiment of a method of manufacturing a semiconductor device according to the present invention.
- a layer (or film) when referred to in the written description as being ‘on’ another layer or substrate, it means that such a layer (or film) can be directly on the other layer or substrate, or that one or more other layers may be present therebetween. Also, when a layer (or film) is referred to as being ‘under’ another layer, it means that the layer (or film) can be directly under the other layer, or that one or more other layers may be present therebetween. In addition, when a layer (or film) is referred to as being ‘between’ two layers, it means that the layer (or film) may be the only layer (or film) between the two layers, or that one or more other layers may also be present between the two layers.
- a semiconductor device 100 includes a first semiconductor layer 101 , a second semiconductor layer 102 , and a via 170 .
- the first semiconductor layer 101 may include a logic circuit.
- the second semiconductor layer 102 may be stacked on the first semiconductor layer 101 and may include a memory circuit.
- the logic circuit of the first semiconductor layer 101 and the memory circuit of the second semiconductor layer 102 are electrically connected to each other through the via 170 .
- the logic circuit may operate at a low voltage while the memory circuit operates at a high voltage.
- the logic circuit may operate at a high voltage while the memory circuit operates at a low voltage.
- the present invention will be described further, though, with respect to an embodiment in which the logic circuit operates at a low voltage and the memory circuit operates at a high voltage.
- the first semiconductor layer 101 also includes a first substrate 110 made of a semiconductor such as silicon (Si).
- the logic circuit of the first semiconductor layer 101 may be made up of a plurality of transistors 116 surrounded by an insulation layer 126 .
- device isolation layers 112 define an active region 111 in the first substrate 110 .
- a low voltage well 114 may be disposed in the active region 111 .
- Each of the transistors 116 may include a gate 117 , a gate insulation layer 118 , a spacer 121 , and a junction region 120 .
- each transistor 116 is electrically connected to a metal interconnection 124 through a contact plug 122 that is electrically connected to a junction region 120 .
- the gate insulation layer 118 of each of the transistors of the logic circuit comprises a silicon oxide layer having a relatively small thickness t 1 of about 15 ⁇ to about 40 ⁇ , i.e., may be relatively thin compared to the gate insulation layer of the transistors of the memory circuit (described below).
- the widths of the gate oxide layers 118 of the various transistors 116 may vary throughout the first semiconductor layer 101 .
- the second semiconductor layer 102 also includes a substrate 150 made of a semiconductor such as silicon (Si).
- the memory circuit of the second semiconductor layer 102 may be a NOR flash memory circuit; however, the present invention is not limited thereto.
- the memory circuit may be a NAND flash memory circuit or an electrically erasable programmable read only memory (EEPROM) circuit.
- the first semiconductor layer 101 may include a memory circuit, e.g., a NOR flash memory circuit, a NAND flash memory circuit or an EEPROM circuit, in which case the second semiconductor layer 102 includes a logic circuit.
- the NOR flash memory circuit of the second semiconductor layer 102 includes a plurality of memory transistors 156 surrounded by insulation layers 167 and 168 .
- an active region 151 is defined in the second substrate 150 by a device isolation layer 152 .
- the active region 151 has a double-well structure including a high voltage deep well 154 and a high voltage pocket well 155 disposed in the high voltage deep well 154 , for example.
- the double-well structure is preferably used for electrically isolating memory arrays in units of a PAGE or a MAT from each other.
- the high voltage deep well 154 and the high voltage pocket well 155 may have different conductivity types. For example, when the second substrate 150 has a p-type conductivity, the high voltage deep well 154 has an n-type conductivity and the high voltage pocket well 155 has a p-type conductivity.
- Each of the transistors 156 of the second semiconductor layer 102 may include a gate pattern 166 , a gate insulation layer 160 , a spacer 165 , and junction regions 161 and 162 .
- the gate pattern 166 may include a floating gate 159 , a blocking insulation layer 158 and a control gate 157 which are stacked one atop the other in the foregoing sequence.
- the floating gate 159 is electrically isolated to store a charge.
- the junction regions 161 may be source regions and thereby together serve as a common source line.
- the junction regions 162 may serve as drains for the transistors. In this case, each drain is electrically connected to a bit line 164 through a contact plug 163 .
- the gate insulation layer 160 of the memory circuit is a so-called tunnel insulation layer and may comprise a silicon oxide having a thickness t 2 of about 50 to about 70 ⁇ , i.e., may be relatively thick compared to the gate insulation layer 118 of the logic circuit.
- the relatively thin gate insulation layer 118 of the low voltage circuit is disposed on the first substrate 110 and the relatively thick gate insulation layer 160 of the high voltage circuit is disposed on the second substrate 150 . Accordingly, this structure is much easier to manufacture than a conventional SoC device in which gate insulation layers of different thicknesses are formed on a single substrate.
- the via 170 extends from a junction region 120 of the first semiconductor layer 101 through the substrate 150 of the second semiconductor layer 102 and the insulation layer 126 of the first semiconductor layer 101 .
- the via 170 may be disposed in a lateralmost portion of the first and second semiconductor layers 101 and 102 .
- the second semiconductor layer 102 includes a via plug 172 electrically connecting the via 170 to the bit line 164 .
- the bit line 164 is electrically connected to a junction region 120 of the first semiconductor layer 101 .
- FIG. 1B is a sectional view of another embodiment of a semiconductor device according to the present invention.
- the via 170 extends through the insulation layer 167 and substrate 150 of the second semiconductor layer 102 and the insulation layer 126 of the first semiconductor layer 101 to directly connect the bit line 164 to a junction region 120 of the first semiconductor layer 101 .
- the other elements and their structural relationships are similar to those described above with reference to FIG. 1A .
- FIGS. 2A through 2E illustrate a method of manufacturing a semiconductor device according to the present invention.
- a first semiconductor layer 101 including a logic circuit surrounded by an insulation layer 126 is prepared.
- the logic circuit may operate at a relatively low voltage compared to a memory circuit of the device (described later).
- the logic circuit is fabricated by forming a plurality of transistors 116 on an active region 111 of the first substrate 110 , by forming an insulation layer 126 on the transistors 116 , by forming contact plugs 122 in the insulation layer 126 , and by forming a metal interconnection 124 electrically connected to the transistors 116 through the contact plugs 122 , all using well known processes.
- a device isolation layer 112 is formed in a first substrate 110 , made of a semiconductor, to define the active region 111 .
- Ions are implanted into the active region 111 to form a low voltage well 114 .
- a plurality of transistors 116 each including a gate insulation layer 118 , a gate 117 , a spacer 121 and a junction region 120 are formed on the active region 111 .
- the gate insulation layer 118 may be formed by depositing silicon oxide to a thickness t 1 of about 15 ⁇ to about 40 ⁇ on the substrate 111 and then patterning the silicon oxide along with the layer constituting the gate 117 . Then, the insulation layer 126 is formed over the transistors 116 .
- the contact plugs 122 are formed in the insulation layer 126 such that the plugs 122 are each connected to a junction region 120 , and a metal interconnection 124 is formed such that it is connected to the contact plugs 122 .
- a portion of the insulation layer 126 is removed to form a first via hole 140 exposing a portion of one of the junction regions 120 .
- the first via hole 140 is preferably formed in a lateralmost portion of the first semiconductor layer 101 .
- a second substrate 150 made of a semiconductor is prepared, and a plurality of memory transistors 156 are formed on an active region 151 of the substrate, using well-known processes per se.
- a device isolation layer 152 is formed in the second substrate 150 to define the active region 151 .
- Ions are implanted into the active region 151 to form a double well structure.
- the double well structure has a high voltage pocket well 155 of a second conductivity type disposed in a high voltage deep well 154 of a first conductivity type.
- the second substrate 150 has a p-type conductivity
- the high voltage deep well 154 has an n-type conductivity
- the high voltage pocket well 155 has a p-type conductivity.
- a plurality of transistors 156 each including a gate pattern 166 , a gate insulation layer 160 , a spacer 165 and junction regions 161 and 162 are formed on the active region 151 using well known processes.
- the gate insulation layer 160 is a so-called tunnel insulation layer, and may be formed by depositing silicon oxide to a relatively great thickness t 2 of about 50 ⁇ to about 70 ⁇ on the second substrate 150 .
- the gate pattern 166 may be made up of a floating gate 159 , a blocking dielectric layer 158 , and a control gate 157 .
- the floating gate 159 is electrically isolated to store charge.
- junction regions 161 may be source regions which together serve as a common source line, and the junction regions 162 may serve as drain regions electrically connected to a bit line ( 164 in FIG. 2E ) which will described later.
- a portion of the second substrate 150 is removed to form a second via hole 142 extending through the second substrate 150 in a vertical direction.
- the via hole 142 is preferably formed in a lateralmost portion of the second substrate 150 .
- the second substrate 150 is stacked on the first semiconductor layer 101 .
- the first via hole 140 is vertically aligned with the second via hole 142 .
- the first and second via holes 140 and 142 are filled with conductive material to form a via 170 .
- the via 170 extends through the second substrate 150 and the insulation layer 126 of the first semiconductor 101 such that the via 170 is connected to a (lateralmost) junction region 120 of the first semiconductor layer 101 .
- insulating material is deposited on the second substrate 150 to form an insulation layer 167 surrounding the transistors 156 . Subsequently, a portion of the insulation layer 167 is removed to form contact holes 146 exposing the drains 162 and a third via hole 144 exposing the via 170 .
- the contact holes 146 and the third via hole 144 may be formed simultaneously.
- the contact holes 146 and the third via hole 144 are filled with conductive material to form contact plugs 163 and a via plug 172 , respectively.
- the contact plugs 163 (collectively) and the via plug 172 may be formed simultaneously or sequentially.
- conductive material is deposited on the insulation layer 167 and is patterned to form a bit line 164 .
- the bit line 164 is electrically connected to the via plug 172 and thus to the via 170 .
- the bit line 164 is also electrically connected to the contact plugs 163 and thus to the drains 162 .
- an insulation layer 168 may be formed over the bit line 164 .
- the logic circuit and the NOR flash memory circuit of the semiconductor device 100 are formed on the first substrate 110 and the second substrate 150 , respectively, and the logic circuit and the NOR flash memory circuit are electrically connected to each other through the via 170 .
- the logic circuit may be formed on the second semiconductor layer 102 and the NOR flash memory circuit may be formed on the first semiconductor layer 101 according to the present invention. In this case, steps similar to those described above may be carried out to form such a device. The sequence and specifics of such steps can be readily discerned from the description above and therefore, will not be described in detail for the sake of brevity.
- FIGS. 3A through 3D illustrate another embodiment of a method of manufacturing a semiconductor device according to the present invention.
- a first semiconductor layer 101 including a first substrate 110 on which a logic circuit is formed is prepared.
- the logic circuit includes a plurality of transistors 116 .
- an insulation layer 126 is formed over the transistors 116 .
- the first semiconductor layer 101 may be prepared using the same method described above with reference to FIG. 2A .
- a portion of the insulation layer 126 is removed to form a first via hole 140 exposing a (lateralmost) junction region 120 .
- a second semiconductor substrate 150 on which a memory circuit is formed is prepared.
- the memory circuit includes a plurality of memory transistors 156 .
- the transistors 156 may be fabricated using the same method described above with reference to FIG. 2B .
- insulating material is deposited on the second substrate 150 to form an insulation layer 167 over the transistors 167 .
- a portion of the insulation layer 167 is removed to form contact holes 146 exposing drains 162 , respectively, and a portion of the insulation layer 167 and a portion of the second substrate 150 are removed to form a second via hole 143 extending vertically through the insulation layer 167 and the second substrate 150 .
- the contact holes 146 (collectively) and the second via hole 143 may be formed simultaneously or sequentially.
- the second substrate 150 is stacked on the first semiconductor layer 101 .
- the first via hole 140 is aligned with the second via hole 143 .
- the first and second via holes 140 and 143 are filled with conductive material to form a via 170
- the contact holes 146 are filled with conductive material to form contact plugs 163 .
- the contact plugs 163 (collectively) and the via 170 may be formed simultaneously or sequentially.
- the via 170 extends through the insulation layer 126 , the second substrate 150 and the insulation layer 167 such that the via 170 is connected to a (lattermost) junction region 120 of the first semiconductor layer 101 .
- bit line 164 is electrically connected to the via 170 directly.
- the bit line 164 is also electrically connected to the contact plugs 163 , and thus to the drains 162 .
- an insulation layer 168 may be formed on the bit line 164 so as to cover the bit line 164 .
- the logic circuit and the NOR flash memory circuit are formed on the first substrate 110 and the second substrate 150 , respectively, and the logic circuit and the NOR flash memory circuit are electrically connected to each other through the via 170 .
- FIGS. 4A through 4D illustrate another embodiment of a method of manufacturing a semiconductor device according to the present invention.
- a first semiconductor layer 101 including a logic circuit is prepared.
- the first semiconductor layer 101 may be prepared using the same method described above with reference to FIG. 3A .
- a second semiconductor substrate 150 having a plurality of memory transistors 156 covered with an insulation layer 167 is prepared.
- the method of preparing the second semiconductor substrate 150 may be the same as that described above with reference to FIG. 3B .
- the second semiconductor substrate 150 is stacked on the first semiconductor layer 101 .
- a via hole 140 is formed through insulation layer 167 , the second semiconductor substrate 150 and the insulation layer 126 of the first semiconductor layer 101 to expose a lateralmost one of the junction regions 120 of the first semiconductor layer 120 .
- contact holes 146 are formed in the insulation layer 167 to expose respective ones of the drains 162 .
- the via hole 140 and the contact holes 146 may be formed simultaneously.
- the via hole 140 is filled with conductive material to form a via 170
- the contact holes 146 are filled with conductive material to form contact plugs 163 .
- the via 170 and the contact plugs 163 may be formed simultaneously or sequentially.
- a bit line 164 is formed on the insulation layer 167 such that the bit line 164 is connected to the via 170 and to the contact plugs 163 . Furthermore, an insulation layer 168 may be formed over the bit line 164 so as to cover the bit line 164 .
- a logic circuit and a NOR flash memory circuit are formed on a first substrate 110 and the second substrate 150 , respectively, and the logic circuit and the NOR flash memory circuit are electrically connected to each other through the via 170 .
- the logic circuit and the memory circuit having the respective gate insulation layers are formed on different substrates, the substrates are stacked, and then the logic circuit and the memory circuit are electrically connected to each other through a via. Therefore, it is relatively easy to form the gate insulation layers of the logic circuit and memory circuits even though the layers have different thicknesses. Also, it is possible to readily manufacture semiconductor devices having identical logic circuits but different memory circuits (i.e., different kinds of memory circuits or memory circuits of various sizes) to meet consumer demand or market conditions.
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Abstract
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