US6756241B2 - Method of manufacturing semiconductor device and system for manufacturing the same - Google Patents
Method of manufacturing semiconductor device and system for manufacturing the same Download PDFInfo
- Publication number
- US6756241B2 US6756241B2 US10/026,551 US2655101A US6756241B2 US 6756241 B2 US6756241 B2 US 6756241B2 US 2655101 A US2655101 A US 2655101A US 6756241 B2 US6756241 B2 US 6756241B2
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- processing
- semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
Definitions
- the present invention relates to a method of and a system for manufacturing a semiconductor device, and more particularly, to a method of and a system for manufacturing a semiconductor device in which inspection is followed by re-processing.
- FIG. 10 is a manufacturing step diagram for a conventional semiconductor device. These manufacturing steps are used to form side walls 45 as those shown in FIG. 4, for example. Now, steps of forming the side walls 45 will be described with reference to FIG. 4 .
- pre-processing for depositing an insulation film 43 is executed so as to cover a semiconductor substrate 41 and a gate electrode 42 formed on the semiconductor substrate 41 .
- a film thickness of the insulation film 43 is measured.
- a condition for a step 104 is set up based on a result of the measurement at the step 102 .
- step 104 post-processing is executed, in which the insulation film 43 is etched back in accordance with an etching condition determined at the step 103 and the side walls 45 are consequently formed on the both sides of the gate electrode 42 .
- widths of the side walls 45 are measured and whether the widths comply with a predetermined standard is inspected.
- a step 106 whether a result of the inspection at the step 105 complies with a predetermined standard is judged. If compliance with the standard is found, the sequence proceeds to a step 107 for commercialization. On the other hand, if there is not compliance with the standard, the sequence proceeds to a step 108 for discarding.
- the present invention aims at providing a method of and a system for manufacturing a semiconductor device which re-process a semiconductor substrate failing to comply with a predetermined standard to comply with the standard, and thereby improve a production yield.
- the present invention is directed to a manufacturing method of a semiconductor device in which a semiconductor substrate is subjected to processing includes pre-processing and post-processing, comprising: a pre-processing step to process a semiconductor substrate; a measurement step to measure a characteristic of the semiconductor substrate processed at the pre-processing step; a setup step to set a processing condition for post-processing based on a result of the measurement at the measurement step; a post-processing step to process the semiconductor substrate using the processing condition; and an inspection step to inspect a characteristic of the semiconductor substrate processed at the post-processing step and to judge whether compliance with a predetermined standard is found or not, and characterized in further comprising re-processing step to re-process the semiconductor substrate judged not complying with the standard at the inspection step such that the semiconductor substrate complies with the standard.
- a processing condition for the re-processing step is determined based on a result of the inspection at the inspection step.
- the re-processing step may be one step selected from a group including the pre-processing step and the post-processing step.
- the re-processing step may include the pre-processing step, the measurement step, the setup step and the post-processing step.
- the pre-processing step is a step at which an insulation film is deposited on the semiconductor substrate
- the post-processing step is a step at which the insulation film is etched using an etching condition determined from a measurement result regarding a film thickness of the insulation film.
- the pre-processing step is a step at which a field oxide film is formed on the semiconductor substrate
- the post-processing step is a step at which the field oxide film is etched using an etching condition determined based on a measurement result regarding at least one dimension selected between a film thickness of the field oxide film and a width of an active layer region sandwiched by the field oxide film, from a table showing a relationship between the width of the active layer region and an etching quantity of the field oxide film such that the width of the active layer region has a predetermined dimension.
- the measurement step is preferably a step to measure one dimension selected between a film thickness and a width of a predetermined portion of the semiconductor substrate.
- the present invention is also directed to a manufacturing system for semiconductor device including a pre-processing apparatus and a post-processing apparatus, comprising: a pre-processing apparatus to perform pre-processing on a semiconductor substrate; a measurement apparatus to measure a characteristic of the semiconductor substrate processed by the pre-processing; a setup apparatus to set a processing condition for post-processing based on a result of the measurement performed by the measurement apparatus; a post-processing apparatus to perform post-processing on the semiconductor substrate using the processing condition; an inspection apparatus to inspect a characteristic of the semiconductor substrate processed by the post-processing; and an evaluation apparatus to judge whether a result of the inspection by the inspection apparatus complies with a predetermined standard or not, and further characterized in that said pre-processing apparatus and/or the post-processing apparatus re-process(es) the semiconductor substrate judged not complying with the standard by the evaluation apparatus such that the semiconductor substrate complies with the standard.
- the present invention may also include a re-processing condition setup apparatus which sets a re-processing condition for said pre-processing apparatus and/or the post-processing apparatus based on the result of the inspection by the inspection apparatus.
- said pre-processing apparatus is a deposition apparatus and the post-processing apparatus is an etching apparatus.
- the measurement apparatus is an apparatus which measures one dimension selected between a film thickness and a width of a predetermined portion of the semiconductor substrate.
- the manufacturing method according to the present invention requires to re-process a semiconductor substrate judged not complying with a predetermined standard during inspection after processing, and therefore, makes it possible to ensure compliance with the standard.
- FIG. 1 is a manufacturing step diagram according to the present invention
- FIG. 2 is a re-processing step diagram according to the present invention.
- FIG. 3 is a manufacturing step diagram according to the example 1 of the present invention.
- FIGS. 4A and 4B are a cross sectional view showing manufacturing steps according to the example 1 of the present invention.
- FIG. 5 is a manufacturing step diagram according to the example 2 of the present invention.
- FIGS. 6A and 6B are a cross sectional view showing manufacturing steps according to the example 2 of the present invention.
- FIGS. 7A and 7B are a cross sectional view showing manufacturing steps according to the example 3 of the present invention.
- FIG. 8 is a manufacturing step diagram according to the example 4 of the present invention.
- FIGS. 9A-9E are a cross sectional view showing manufacturing steps according to the example 4 of the present invention.
- FIG. 10 is a manufacturing step diagram of conventional manufacturing.
- FIG. 1 is a manufacturing step diagram for a semiconductor device according to a preferred embodiment of the present invention. From a pre-processing step generally denoted at 1 to a commercialization step generally denoted at 7 are similar to the conventional manufacturing steps 101 to 107 shown in FIG. 10 .
- the steps according to the preferred embodiment are different from the conventional manufacturing steps in that when it is judged at a step 6 that an inspection result obtained at a step 5 does not comply with a standard, re-processing is executed at a step 8 .
- FIG. 2 shows detailed contents of the re-processing step generally denoted at 8 .
- re-processing at a step 81 is selected.
- the re-processing is selected either as a pre-processing step 82 , a post-processing step 85 , or the pre-processing step 82 and the post-processing step 85 .
- the pre-processing step 82 is a step with a change to a processing condition for the pre-processing denoted at 1 .
- the step 85 is a step with a change to a processing condition for the post-processing denoted at 4 .
- step 8 the inspection step of step 5 is performed once again to thereby judge at the step 6 whether compliance with the standard is found.
- step 6 When compliance with the standard is found at the step 6 by the re-processing step 8 , the sequence proceeds to the step 7 of commercialization.
- the re-processing step 8 may be performed once again or discarding may be performed.
- the pre-processing step 82 and/or the post-processing step 85 are/is executed once again at the re-processing step 8 when a semiconductor substrate already subjected to the pre-processing step 1 and the post-processing step 4 fails to comply with a predetermined standard, and therefore, it is possible to ensure compliance with the predetermined standard. As a result of this, it is possible to improve a production yield of semiconductor devices and reduce production costs, etc.
- FIG. 3 is a manufacturing step diagram for a side wall, using the present invention. Among these manufacturing steps, first, an insulation film is deposited on a semiconductor substrate, as pre-processing at a step 11 . Used at the step 11 is a deposition apparatus such as a CVD machine, for instance.
- FIG. 4A is a cross sectional view of a semiconductor substrate 41 as it is at the step 11 .
- a gate electrode 42 is formed on the semiconductor substrate 41 .
- An insulation film 43 is deposited so as to cover a surface of the semiconductor substrate 41 and the gate electrode 42 .
- As the insulation film 43 a silicon oxide film, a silicon nitride film, etc., may be used.
- a film thickness of the insulation film 43 is measured.
- an etching condition to etch back the insulation film 43 is set up.
- materials, a film thickness and the like of the insulation film and corresponding appropriate etching conditions are stored in a database in advance, and an etching condition proper to the film thickness measured at the step 12 is selected from the database.
- the insulation film 43 is etched back.
- an etching apparatus such as a sputtering machine is used, for example.
- FIG. 4B is a cross sectional view of the semiconductor substrate 41 as it is at the etch back step.
- the etch back is realized using an ion beam 44 .
- the etch back step leaves the insulation film on the both sides of the gate electrode 42 , which will become side walls 45 .
- a step 16 whether a result of the measurement on the widths of the side walls 45 complies with a predetermined standard is judged.
- the manufacturing is furthered, for example, at a step 17 for the purpose of commercialization into a semiconductor device.
- a step 18 of re-processing is executed. For instance, when the widths of the side walls 45 are smaller than the standard, the step 11 (pre-processing), the steps 12 , 13 and 14 (post-processing) are executed, whereby the side walls 45 are further formed.
- the step 14 post-processing is carried out, whereby the side walls 45 are etched.
- the measurement result at the step 15 as well is used to determine processing conditions for the steps 11 and 14 during the re-processing.
- the steps 15 and 16 are executed to thereby judge once again whether the widths of the side walls 45 comply with the standard or not.
- further manufacturing is performed at the step 17 for the purpose of commercialization into a semiconductor device.
- the re-processing of the step 18 may be carried out once again. Alternatively, discarding may be performed without the step 18 .
- FIG. 5 is a manufacturing step diagram for an inter-layer insulation film, using the present invention. Among these manufacturing steps, first, an insulation film is deposited on a semiconductor substrate, as pre-processing at a step 21 .
- FIG. 6A is a cross sectional view of a semiconductor substrate 61 as it is after the step 21 .
- a transistor (not shown), for instance, is formed on the semiconductor substrate 61 .
- Denoted at 62 is a gate electrode of the transistor.
- An insulation film 63 is deposited so as to cover a surface of the semiconductor substrate 61 and the gate electrode 62 .
- a silicon oxide film for example, is used as the insulation film 63 .
- a film thickness of the insulation film 63 is measured.
- an etching condition to etch back the insulation film 63 is set up.
- an etching condition proper to the film thickness measured at the step 22 is selected from a database prepared in advance.
- FIG. 6B is a cross sectional view of the semiconductor substrate 61 as it is at the etch back step.
- the etch back is realized using an ion beam 64 .
- the etch back step reduces the film thickness of the insulation film 63 so that the insulation film 63 becomes an inter-layer insulation film 65 with a predetermined film thickness.
- a film thickness of the inter-layer insulation film 65 is measured.
- a step 26 whether a result of the measurement on the film thickness of the inter-layer insulation film 65 complies with a predetermined standard is judged.
- further manufacturing is performed at a step 27 for the purpose of commercialization into a semiconductor device.
- a hole for example, is formed in the inter-layer insulation film 65 to thereby form a contact hole (not shown) connected to the transistor formed on the semiconductor substrate 61 .
- step 28 when there is not compliance with the standard, re-processing is executed at a step 28 .
- the step 21 pre-processing is carried out to further deposit the insulation film 63 .
- the step 24 is carried out to etch the inter-layer insulation film 65 .
- the steps 25 and 26 are executed to thereby judge once again whether the film thickness of the inter-layer insulation film 65 complies with the standard or not.
- further manufacturing is performed at the step 27 for the purpose of commercialization into a semiconductor device.
- the re-processing of the step 28 may be carried out once again. Alternatively, discarding may be performed without the step 28 .
- the example 3 uses the manufacturing steps of the example 2 described above in order to form an inter-layer insulation film across a multilayer interconnection. Manufacturing steps of this example, as shown in FIG. 7A, are same as the manufacturing steps of the example 2, except for that a wiring layer 72 of aluminum or the like is formed on a semiconductor substrate 71 .
- an insulation film 73 on the semiconductor substrate 71 is etched back using an ion beam 74 and accordingly becomes an inter-layer insulation film 75 with a predetermined film thickness.
- a hole for example, is formed in the inter-layer insulation film 75 to thereby form a through hole (not shown).
- the through hole connects the wiring layer 72 with a wiring layer (not shown) formed on the inter-layer insulation film 75 , whereby a multilayer interconnection is obtained.
- FIG. 8 is a manufacturing step diagram for a transistor, using the present invention. Among these manufacturing steps, first, an oxide film and a nitride film are deposited on a semiconductor substrate, as pre-processing at a step 31 .
- FIG. 9A is a cross sectional view of a semiconductor substrate 91 of silicon or the like as it is after the step 31 .
- An oxide film 92 of SiO 2 and a nitride film 93 of SiN, for instance, are deposited sequentially on the semiconductor substrate 91 .
- the nitride film 93 and the oxide film 92 are etched using a resist mask (not shown) formed on the nitride film 93 , thereby exposing a surface of the semiconductor substrate 91 in a LOCOS formation area.
- an opening width namely, a width of the exposed surface area of the semiconductor substrate 91 (denoted at x in FIG. 9B) is measured.
- the exposed surface of the semiconductor substrate 91 is oxidized to thereby form a field oxide film.
- the nitride film 93 used as a mask and the oxide film 92 are removed by etching, so that LOCOS isolation areas 94 as those shown in FIG. 9C are formed.
- a surface area of the semiconductor substrate 91 sandwiched by the LOCOS isolation areas 94 becomes a transistor formation area (field region) whose width is y1.
- a step is executed of forming an oxide film in a surface of the transistor formation area and removing the oxide film after through-implantation of ions via the oxide film
- a step is executed of forming a gate oxide film in the transistor formation area and thereafter removing the gate oxide film in an unwanted area, etc. (not shown).
- the oxide films are removed using hydracid fluoride (hydrofluoric acid), and therefore, the field oxide film in the LOCOS isolation areas 94 , too, is etched. In consequence, the width of the transistor formation area expands from y1 (FIG. 9C) to y2 (FIG. 9 D).
- a condition for hydrofluoric acid processing such as a concentration of hydrofluoric acid and a processing time, is determined based on a value x calculated at a step 32 , using a database which stores in advance a relationship between processing conditions and a quantity of increase in the width y1 of the surface area of the semiconductor substrate 1 sandwiched by the LOCOS isolation areas 94 .
- the width (field dimension) y2 of the transistor formation area (FIG. 9D) is measured.
- a step 38 whether a result of the measurement on y2 complies with a predetermined standard is judged.
- further manufacturing for instance, is performed at a step 39 for the purpose of commercialization into a semiconductor device.
- hydrofluoric acid processing (post-processing) is executed at a step 40 . More precisely, when the measured width y2 is narrower than a predetermined width, the field oxide film of the LOCOS isolation areas 94 is etched through further hydrofluoric acid processing, whereby the width of the transistor formation area increases from y2 to y3 (FIG. 9 E).
- a condition for the hydrofluoric acid processing at the step 40 is determined from a database which stores in advance a relationship between processing conditions, such as a concentration of hydrofluoric acid, and a quantity of increase in the width y2 of the surface area of the semiconductor substrate 1 sandwiched by the LOCOS isolation areas 94 .
- the database used at the step 35 may be used as this database.
- the width y3 of the transistor formation area (FIG. 9E) is measured once again at the step 37 , in order to judge whether the width y3 complies with the standard or not.
- further manufacturing is performed at the step 39 for the purpose of commercialization into a semiconductor device.
- the hydrofluoric acid processing of the step 40 may be executed once again. Alternatively, discarding may be performed without the step 40 .
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-397501 | 2000-12-27 | ||
JP2000397501A JP2002198410A (en) | 2000-12-27 | 2000-12-27 | Method of manufacturing semiconductor device and manufacturing system |
Publications (2)
Publication Number | Publication Date |
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US20020081754A1 US20020081754A1 (en) | 2002-06-27 |
US6756241B2 true US6756241B2 (en) | 2004-06-29 |
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US10/026,551 Expired - Fee Related US6756241B2 (en) | 2000-12-27 | 2001-12-27 | Method of manufacturing semiconductor device and system for manufacturing the same |
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US (1) | US6756241B2 (en) |
JP (1) | JP2002198410A (en) |
KR (1) | KR100443683B1 (en) |
TW (1) | TW518653B (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6479309B1 (en) * | 2001-05-25 | 2002-11-12 | Advanced Micro Devices, Inc. | Method and apparatus for determining process layer conformality |
JP2005347420A (en) * | 2004-06-01 | 2005-12-15 | Nec Electronics Corp | Semiconductor manufacturing apparatus, and method for manufacturing semiconductor apparatus |
JP5221979B2 (en) * | 2008-02-25 | 2013-06-26 | シャープ株式会社 | Manufacturing method of semiconductor device |
JP5378732B2 (en) * | 2008-09-04 | 2013-12-25 | Sumco Techxiv株式会社 | Semiconductor wafer evaluation method, semiconductor wafer manufacturing method, and semiconductor wafer manufacturing process evaluation method |
JP6267881B2 (en) * | 2013-07-03 | 2018-01-24 | 東京エレクトロン株式会社 | Substrate processing method and control apparatus |
CN103985655B (en) * | 2014-05-27 | 2016-08-17 | 中国科学技术大学 | The preparation method of the automatically controlled quantum dot of GaAs/AlGaAs semiconductor heterostructure grid and measuring method thereof |
JP6133347B2 (en) * | 2015-03-30 | 2017-05-24 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing system, and program |
JP6072845B2 (en) * | 2015-03-31 | 2017-02-01 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing system, substrate processing apparatus, and program |
CN112449495B (en) * | 2019-08-27 | 2021-11-30 | 南通深南电路有限公司 | Drilling detection method and drilling detection equipment |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5210041A (en) * | 1990-07-24 | 1993-05-11 | Hitachi, Ltd. | Process for manufacturing semiconductor integrated circuit device |
JPH05259015A (en) | 1991-04-19 | 1993-10-08 | Matsushita Electron Corp | Manufacture of semiconductor device |
JPH10163080A (en) | 1996-11-27 | 1998-06-19 | Matsushita Electron Corp | Semiconductor manufacturing system |
JPH1116805A (en) | 1997-06-20 | 1999-01-22 | Sony Corp | Feedback method for manufacturing process for semiconductor device |
JPH11219874A (en) | 1998-02-04 | 1999-08-10 | Hitachi Ltd | Semiconductor manufacturing method and device |
JP2000133568A (en) | 1998-10-23 | 2000-05-12 | Sony Corp | Method and device for testing measured value |
US6424417B1 (en) * | 1998-06-14 | 2002-07-23 | Nova Measuring Instruments Ltd. | Method and system for controlling the photolithography process |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100211648B1 (en) * | 1996-02-27 | 1999-08-02 | 윤종용 | Method for generating semiconductor wafer |
DE59705526D1 (en) * | 1996-10-11 | 2002-01-10 | Goldschmidt Ag Th | Silicon poly (meth) acrylates, their production and their use in coatings |
KR19980068739A (en) * | 1997-02-24 | 1998-10-26 | 김광호 | Exposure Time Control Method in Semiconductor Manufacturing Process |
-
2000
- 2000-12-27 JP JP2000397501A patent/JP2002198410A/en active Pending
-
2001
- 2001-12-05 TW TW090130081A patent/TW518653B/en not_active IP Right Cessation
- 2001-12-26 KR KR10-2001-0084797A patent/KR100443683B1/en not_active IP Right Cessation
- 2001-12-27 US US10/026,551 patent/US6756241B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5210041A (en) * | 1990-07-24 | 1993-05-11 | Hitachi, Ltd. | Process for manufacturing semiconductor integrated circuit device |
JPH05259015A (en) | 1991-04-19 | 1993-10-08 | Matsushita Electron Corp | Manufacture of semiconductor device |
JPH10163080A (en) | 1996-11-27 | 1998-06-19 | Matsushita Electron Corp | Semiconductor manufacturing system |
JPH1116805A (en) | 1997-06-20 | 1999-01-22 | Sony Corp | Feedback method for manufacturing process for semiconductor device |
JPH11219874A (en) | 1998-02-04 | 1999-08-10 | Hitachi Ltd | Semiconductor manufacturing method and device |
US6424417B1 (en) * | 1998-06-14 | 2002-07-23 | Nova Measuring Instruments Ltd. | Method and system for controlling the photolithography process |
JP2000133568A (en) | 1998-10-23 | 2000-05-12 | Sony Corp | Method and device for testing measured value |
Also Published As
Publication number | Publication date |
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KR100443683B1 (en) | 2004-08-09 |
KR20020053735A (en) | 2002-07-05 |
JP2002198410A (en) | 2002-07-12 |
TW518653B (en) | 2003-01-21 |
US20020081754A1 (en) | 2002-06-27 |
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