US6385598B1 - Fuzzy processor with architecture for non-fuzzy processing - Google Patents

Fuzzy processor with architecture for non-fuzzy processing Download PDF

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US6385598B1
US6385598B1 US08/623,617 US62361796A US6385598B1 US 6385598 B1 US6385598 B1 US 6385598B1 US 62361796 A US62361796 A US 62361796A US 6385598 B1 US6385598 B1 US 6385598B1
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fuzzy
processor
memory
rules
instruction
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Biagio Giacalone
Francesco Pappalardo
Enrico Pelos
Vincenzo Catania
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CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
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CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N7/00—Computing arrangements based on specific mathematical models
    • G06N7/02—Computing arrangements based on specific mathematical models using fuzzy logic
    • G06N7/04—Physical realisation

Definitions

  • the present invention relates to fuzzy processors, and more particularly to a fuzzy processor which can also perform non-fuzzy processes.
  • fuzzy processors there are various kinds of fuzzy processors.
  • An example of a classic fuzzy processor is the MB94110 processor by Fujitsu, comprising a block that performs fuzzy instructions.
  • Another example is the SAE81 C99 processor by Siemens, which can also load various knowledge bases from an external memory, although this is not possible conditionally or concurrently with normal fuzzy processing.
  • known fuzzy processors only process fuzzy instructions and cannot integrate fuzzy control with the processing of classic instructions such as shift, rotate, compare, or arithmetic/logic instructions, and also have no signals such as interrupt, stack, etcetera. Accordingly, it is not possible to perform any kind of arithmetic/logic processing on the inputs and on the outputs of the fuzzy controller.
  • All known fuzzy control units furthermore perform control by processing the fuzzy instructions sequentially, with no possibility of jumping from one instruction to another.
  • fuzzy processors process a fixed number of inputs and a fixed number of fuzzy rules.
  • a certain number of membership functions are associated with each fuzzy input, and the set of these functions is termed a knowledge base. Both the set of fuzzy rules and the knowledge base remain unchanged throughout processing.
  • an aim of the present invention is to provide a fuzzy processor with an improved architecture that is more versatile than known fuzzy processors.
  • an object of the present invention is to provide a fuzzy processor with an improved architecture that is capable of handling inputs and outputs.
  • Another object of the present invention is to provide a fuzzy processor with improved architecture that is capable of loading various knowledge bases or sets of fuzzy rules from outside during normal operation.
  • Another object of the present invention is to provide a fuzzy processor with an improved architecture capable of changing the knowledge base or the set of fuzzy rules to be processed during normal processing, conditionally or unconditionally, the conditions occurring on the inputs or on the outputs.
  • Another object of the present invention is to provide a fuzzy processor with an improved architecture capable of performing arithmetic/logic processing on the inputs and on the outputs of the fuzzy controller, processing non-fuzzy instructions, and handling interrupt signals.
  • Another object of the present invention is to provide a fuzzy processor with an improved architecture capable of performing conditional or unconditional jumps within fuzzy instructions.
  • Another object of the present invention is to provide a processor that is highly reliable and relatively easy to manufacture at a competitive cost.
  • a fuzzy processor with an improved architecture comprising: a fuzzy rule processor, an internal fuzzy instruction memory, and an internal knowledge base memory, and characterized in that it also includes an arithmetic-logic unit, a control unit capable of performing non-fuzzy instructions typical of conventional microprocessors, and an internal memory comprising non-fuzzy instructions.
  • FIG. 1 is a block diagram of a fuzzy processor with an improved architecture according to the present invention.
  • fuzzy processors only process fuzzy instructions and cannot integrate fuzzy control with the processing of classic instructions such as shift, rotate, compare, and arithmetic-logic instructions, and also have no signals such as interrupt, stack, etcetera.
  • the fuzzy processor according to the present invention is provided with an arithmetic/logic unit (ALU), a direct memory access control unit (DMA), a timer, an interrupt handler, interfaces for the buses, and other components.
  • ALU arithmetic/logic unit
  • DMA direct memory access control unit
  • timer such as arithmetic/logic instructions, shift, rotate, etcetera
  • interrupt handler such as arithmetic/logic instructions, shift, rotate, etcetera
  • the fuzzy control unit according to the present invention can use internal registers of the chip as inputs of the fuzzy section and can also use them as buffer registers for the output of the fuzzy section, and preprocessings on the inputs and postprocessings on the outputs can be performed in these registers.
  • adders, subtracters, multipliers, and dividers are already present in the classic architecture of a fuzzy control unit and are used for fuzzification and defuzzification, the present invention proposes the concept of arithmetic/logic processing of the inputs and of the outputs, the execution of non-fuzzy instructions, and the handling of interrupt signals. These functions can be performed by using appropriately modified existing blocks or specifically designed circuitry. In particular, input and output processing can be performed almost entirely by existing blocks.
  • fuzzy control units perform control by processing the fuzzy instructions sequentially, without being able to jump from one fuzzy instruction to another.
  • the fuzzy processor according to an illustrative embodiment of the present invention proposes the insertion, among fuzzy rules, of conditional or unconditional jump instructions, in which the optional condition will have to occur on the inputs or on the outputs. This allows one to instantly adapt the fuzzy control to particular changes in the system to be controlled, and therefore to jump within the rules to be processed according to the inputs or outputs obtained.
  • fuzzy control units process a fixed number of inputs and fuzzy rules. A certain number of membership functions are associated with each input.
  • the set of membership functions is termed a knowledge base. Both the set of rules and the knowledge base are invariant throughout processing.
  • the processor according to the present invention is able to change the knowledge base and/or the set of fuzzy rules during normal processing. This is performed by means of a buffer memory, where the next knowledge base and/or set of fuzzy rules to be processed is loaded during normal operation, so that the base or set can be swapped by virtue of an instruction for conditional or unconditional swapping of the rule set and/or the knowledge base.
  • the conditions can be imposed on the inputs or on the outputs. This allows adaptive control and furthermore, by associating different inputs with the various knowledge bases, it is possible to process a larger number of inputs and thus to perform more simply the time-sharing control of a plurality of systems. Indeed, this allows one to process an infinite number of fuzzy rules.
  • characteristics that are innovative with respect to known fuzzy processors are the possibility of loading from outside the fuzzy rule memory and the knowledge base memory (the membership functions) concurrently (and transparently) with respect to instruction processing; the possibility of processing both fuzzy rules and non-fuzzy instructions (shift, rotate, arithmetic/logic operations, etcetera); the possibility of conditional or unconditional jumps within the set of fuzzy rules that is being processed; and finally, the possibility of conditionally or unconditionally swapping the knowledge base or the set of rules to be processed.
  • FIG. 1 A block diagram of the innovative architecture of the fuzzy processor according to an illustrative embodiment of the present invention is shown in FIG. 1 .
  • the reference numeral 1 designates the classic fuzzy rule processor, which executes fuzzy rules.
  • An arithmetic/logic unit (ALU) 2 has been included in the processor according to the present invention to perform the arithmetic/logic processing of the inputs and of the outputs.
  • a control unit 3 is furthermore connected to the ALU 2 and is adapted to perform non-fuzzy instructions.
  • An interrupt handler 4 is located inside the control unit 3 .
  • the control unit 3 is furthermore connected directly to the fuzzy rule processor 1 .
  • the control unit 3 and the ALU 2 are connected to internal registers 17 , which in turn are connected to a data memory 18 that acts as a buffer for the internal registers 17 .
  • the control unit 3 is also connected to the data memory 18 .
  • the internal registers 17 , the data memory 18 , the ALU 2 , and the fuzzy rule processor 1 are connected to a data bus 19 .
  • the data bus 19 is connected to the ALU 2 by means of two lines, a direct line, and a line that passes through a multiplexer 20 which performs a selection so that the second input of the ALU 2 arrives from the data bus or from the control unit 3 .
  • An external control line IF/MC 21 is connected to the control unit 3 and sends a signal externally if the processor is executing fuzzy or non-fuzzy instructions.
  • a conventional timer 22 is furthermore connected to the control unit 3 and has its own output line 23 . Interrupt signals are sent to the control unit 3 and to the interrupt handler 4 located therein by means of an interrupt line 24 . Reset signals are sent to the control unit by means of a reset line 25 .
  • a clock signal is sent to the control unit 3 by means of a clock line 26 .
  • a data input control unit 27 is furthermore connected to the data bus 19 and to the control unit 3 .
  • the control unit 27 is connected to the outside by means of a handshake line 28 , an input data line 29 , and an input number selection line 30 for selecting an input among the multiple available inputs.
  • a data output control unit 31 is likewise connected to the data bus 19 and to the control unit 3 .
  • Said data output control unit is connected to the outside by means of a handshake line 32 , an output data line 33 , and an output number selection line 34 for externally indicating which among the plurality of available outputs is on the output data line 33 .
  • the processor according to the present invention is furthermore provided with an internal RAM memory 5 directly connected to the fuzzy rule processor 1 and to the control unit 3 .
  • the RAM memory 5 furthermore internally comprises, in addition to other components, a microcode memory (MCM) 6 .
  • MCM microcode memory
  • Said microcode memory 6 stores all the non-fuzzy instructions and is directly connected to the control unit 3 , so that said instructions are executed by said control unit.
  • the internal RAM memory 5 furthermore includes a fuzzy instruction memory 7 (IFM) that is conveniently divided into two parts, IFM 1 and IFM 2 .
  • Said fuzzy instruction memory 7 comprises all the fuzzy instructions that must be executed by the fuzzy rule processor 1 to which the memory 7 is directly connected.
  • the internal RAM memory 5 furthermore comprises a knowledge base memory 8 that is conveniently divided into two parts ADM 1 and AMD 2 (Antecedent Data Memory) and is directly connected to the fuzzy rule processor 1 .
  • An external memory 9 is furthermore associated with the processor according to the present invention and can advantageously be an internal one; it comprises an external knowledge base memory 10 , an external fuzzy rule memory 11 , and an external microcode memory 12 .
  • the external knowledge base memory 10 is divided into multiple banks, each of which contains a knowledge base, from bank 1 to bank i, and the external fuzzy rule memory 11 is also divided into multiple banks, each bank containing a different set of rules, from bank 1 to bank n.
  • the external memory 9 with its respective internal memories 10 , 11 , and 12 , is connected to the internal RAM memory 5 by means of a direct memory access control unit (DMA) 13 and a demultiplexer 14 .
  • the memories 10 , 11 , and 12 are connected to the DMA 13 by means of a data line 15
  • the DMA 13 is connected to the external memory by means of a memory address line 16 .
  • the DMA allows one to load knowledge bases and sets of fuzzy instructions in the corresponding buffer memories concurrently with normal processing.
  • the arithmetic/logic unit 2 performs the arithmetic/logic processing, whereas the non-fuzzy instructions are performed by the control unit 3 .
  • the non-fuzzy instructions reside in the microcode memory 6 and are performed directly by the control unit 3 , whereas the fuzzy rules are stored in the fuzzy instruction memory 7 , and the task of processing the fuzzy rules is assigned to the fuzzy rule processor 1 .
  • the control unit 3 can order the execution of a certain number n of fuzzy instructions processed by the fuzzy processor 1 and then resume control.
  • Interrupts are requested by means of the interrupt line 24 and performed by the interrupt handler 4 located inside the control unit 3 .
  • the non-fuzzy instructions also include the instruction ordering processing of the fuzzy instructions in a continuous cycle (as in classic fuzzy control units) and can be interrupted only by an intervening interrupt.
  • the fuzzy rules can process the inputs taken directly from the outside by means of the data input control unit 27 or the inputs residing in the internal registers 17 , which in this case may have been preprocessed by the control unit 3 .
  • the outputs of the fuzzy rule processor 1 can furthermore be sent immediately outside by means of the data output control unit 31 or placed in the internal registers 17 , so that they can be postprocessed by the control unit 3 before being sent outside the processor.
  • a jump instruction has been inserted among the fuzzy instructions contained in the fuzzy instruction memory 7 ; alternatively, this can be done by means of the control unit.
  • the possibility of changing the knowledge base or the set of fuzzy rules to be processed during normal processing is provided by means of the DMA 13 , which transparently loads from the external memory 9 the new knowledge base and/or the set of rules to be processed.
  • the internal knowledge base memory 8 and the internal fuzzy instruction memory 7 inside the internal RAM memory 5 are duplicated in memories ADM 1 -ADM 2 and IFM 1 -IFM 2 respectively, since while the fuzzy rule processor 1 processes rules residing in one of the fuzzy instruction memories IFM by using the knowledge base that resides in a knowledge base memory ADM, the DMA 13 can load the other memories (by taking the data from the external memory 9 ), and therefore the instruction for swapping the knowledge base or the set of fuzzy rules to be processed simply swaps the internal memories to be processed.
  • This last instruction can be conditional or unconditional, and the conditions to be verified may occur on the inputs and on the outputs of the fuzzy rule processor 1 or also on the non-fuzzy processing value.

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EP95830117 1995-03-30
EP95830117A EP0735459B1 (de) 1995-03-30 1995-03-30 Fuzzy-Prozessor-Architektur

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010039538A1 (en) * 1999-11-30 2001-11-08 Francesco Pappalardo Logical fuzzy union and intersection operation calculation circuit
US20020172368A1 (en) * 2000-10-26 2002-11-21 General Instrument, Inc. Intial free preview for multimedia multicast content
US7185192B1 (en) * 2000-07-07 2007-02-27 Emc Corporation Methods and apparatus for controlling access to a resource
US20150206058A1 (en) * 2014-01-23 2015-07-23 Melanie Anne McMeekan Fuzzy inference deduction using rules and hierarchy-based item assignments

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US5305424A (en) * 1990-07-26 1994-04-19 Apt Instruments (N.A.) Inc. Data forming method for a multi-stage fuzzy processing system
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010039538A1 (en) * 1999-11-30 2001-11-08 Francesco Pappalardo Logical fuzzy union and intersection operation calculation circuit
US6862584B2 (en) * 1999-11-30 2005-03-01 Stmicroelectronics S.R.L. Logical fuzzy union and intersection operation calculation circuit
US7185192B1 (en) * 2000-07-07 2007-02-27 Emc Corporation Methods and apparatus for controlling access to a resource
US20020172368A1 (en) * 2000-10-26 2002-11-21 General Instrument, Inc. Intial free preview for multimedia multicast content
US20150206058A1 (en) * 2014-01-23 2015-07-23 Melanie Anne McMeekan Fuzzy inference deduction using rules and hierarchy-based item assignments
US9256833B2 (en) * 2014-01-23 2016-02-09 Healthtrust Purchasing Group, Lp Fuzzy inference deduction using rules and hierarchy-based item assignments
US9542651B2 (en) 2014-01-23 2017-01-10 Healthtrust Purchasing Group, Lp Fuzzy inference deduction using rules and hierarchy-based item assignments

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EP0735459A1 (de) 1996-10-02
JPH08286921A (ja) 1996-11-01
DE69531772D1 (de) 2003-10-23
EP0735459B1 (de) 2003-09-17

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