US5192943A - Cursor display control method and apparatus in a graphic display system - Google Patents

Cursor display control method and apparatus in a graphic display system Download PDF

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Publication number
US5192943A
US5192943A US07/583,584 US58358490A US5192943A US 5192943 A US5192943 A US 5192943A US 58358490 A US58358490 A US 58358490A US 5192943 A US5192943 A US 5192943A
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United States
Prior art keywords
cursor
display
data
cursor pattern
storage means
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Expired - Fee Related
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US07/583,584
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English (en)
Inventor
Shigeru Matsuo
Tadashi Fukushima
Tooru Komagawa
Masahisa Narita
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Hitachi Engineering Co Ltd
Hitachi Ltd
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Hitachi Engineering Co Ltd
Hitachi Ltd
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Assigned to HITACHI ENGINEERING CO., LTD., HITACHI, LTD. reassignment HITACHI ENGINEERING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: FUKUSHIMA, TADASHI, KOMAGAWA, TOORU, MATSUO, SHIGERU, NARITA, MASAHISA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/08—Cursor circuits

Definitions

  • the present invention relates to a cursor display control method in a graphic display system, and particularly to a display control apparatus which has a special storage region for exclusive use for a cursor pattern so that a desired shape is defined in the storage region and has a preferred cursor display function for displaying the defined shape as a cursor.
  • a conventional graphic cursor display system there has been known, for example, a system in which a cursor pattern is drawn on a frame buffer together with graphic information so that they are displayed on a screen.
  • a desired cursor pattern can be displayed and hardware can be simplified, but the cursor pattern must be drawn on the frame buffer by means of a CPU or the like whenever a cursor is moved. It is further necessary to perform a processing for stacking or resuming the graphic information of an overlapped portion, when there has been a problem in the operating speed.
  • FIG. 3 is a block diagram illustrating this system.
  • This system is constituted by a CRT controller (ACRTC) 1000 for performing display control, a cursor pattern memory 1030, a counter 1010 for generating an address of the memory 1030, shift registers 1040 and 1050 for converting the data of the memory 1030 into a video signal, an output position adjusting circuit 1020 for performing display position control dot by dot on a screen, and a multiplexer 1060.
  • ACRTC CRT controller
  • the access of a cursor pattern is performed not bit by bit but word by word of, for example, 16 or 32 bits.
  • each picture element is displayed on a screen not word by word, but, for example, bit by bit in the case of monochrome display, or by four bits in the case of 16-color display.
  • the above-mentioned circuit converts a one-word parallel signal into serial signals bit by bit while performing a dot position adjustment processing for the screen display of the cursor pattern. Since the above-mentioned serial signals are to be supplied as a video signal to a CRT, a high speed device is required for the above-mentioned circuit for producing the signals.
  • CMOS Complementary Metal Oxide Semiconductor
  • the cursor display control apparatus comprises pattern storage means for performing a cursor pattern, shift means for performing, at a cursor non-display time, the shift operation for the position adjustment on a display screen, and means for performing the parallel to serial conversion at a proper cursor display timing.
  • pattern data are shifted by the above-mentioned shift means in advance before the cursor display timing to thereby adjust the bit displacement within every word according to a display position. Then, at the cursor display timing, the pattern data are converted into serial data on the basis of the instruction by a cursor display signal, combined with screen display data, and then supplied to a display unit.
  • serial data converting processing for generating cursor pattern display data is separated from pattern data shift processing for adjusting the display position of the pattern, it is possible to realize a high speed movement of a cursor on a screen without operating dot position adjustment processing at a high speed for the screen display of the pattern.
  • the configuration of the above-mentioned apparatus can be built in an LSI, it is possible to realize an inexpensive display control apparatus having a cursor display function.
  • FIG. 1 is a block diagram of an embodiment of the display control apparatus in which the features of the present invention are illustrated;
  • FIG. 2 is a diagram illustrating a graphic display system using a display control apparatus according to the present invention
  • FIG. 3 is a diagram illustrating a conventional cursor display system
  • FIG. 4 is a block diagram illustrating a display control apparatus according to the present invention.
  • FIGS. 5 and 6 are time charts illustrating the operation of the apparatus of FIG. 4;
  • FIG. 7 is a diagram illustrating an example of the use of a cursor mask plane
  • FIG. 8 is a diagram illustrating a second embodiment in which the pattern shift operation is modified
  • FIG. 9 is a time chart illustrating the operation of the apparatus of FIG. 8.
  • FIG. 10 is a diagram illustrating a fourth embodiment in which the pattern shift operation is modified.
  • FIG. 11 is a time chart illustrating the operation of the apparatus of FIG. 10;
  • FIG. 12 is a diagram illustrating an example in which a cursor pattern is provided in a non-display region of a frame buffer
  • FIG. 13 is a diagram illustrating an example in which a cursor pattern is provided in a system memory.
  • FIG. 14 is a diagram illustrating an example in which a cursor pattern is written in a display region of a frame buffer.
  • FIG. 1 is a block diagram illustrating an embodiment of the display control apparatus which shows the features of the present invention.
  • the display control apparatus includes, in addition to a frame buffer 90 for storing, in the form of a bit map, characters and figures to be displayed on a CRT display unit and a parallel to serial converter 103 for converting the data of the bit map into a video signal, at least a cursor pattern memory 510 for storing a cursor pattern, a shift means 530 for shifting the data of the cursor pattern so as to adjust the display position thereof, a parallel to serial converter 101 for converting the data shifted by the shift means 530 into a video signal, a control circuit 560 for controlling the timing of cursor display, and a combiner 102 for combining video signals.
  • FIG. 2 shows an embodiment of a graphic display system in which a display control apparatus having a cursor display function according to the present invention is incorporated.
  • a central processing unit (CPU) 10 executes a program stored in a system memory 20 so as to control not only a display control apparatus 40 but the system through a system bus 30.
  • the display control apparatus 40 is constituted by a cursor control circuit 50 for controlling the display of a cursor, a display control circuit 60 for displaying the data of the frame buffer 90 on a CRT 110, and a drawing control circuit 70 for drawing characters or figures on the frame buffer 90.
  • the display control apparatus 40 is built in one LSI.
  • the CPU 10 issues a command to the drawing control circuit 70 for drawing a figure on the frame buffer 90.
  • FIGS. to be drawn are defined in advance in accordance with various commands, so that the drawing control circuit 70 can draw a figure such as a line, a circle or the like in accordance with the command given by the CPU 10.
  • the display control circuit 60 reads the frame buffer 90 periodically to make display on the CRT 110, and produces a synchronizing signal to be supplied to the CRT 110.
  • the data read from the frame buffer 90 are converted into a video signal by a video signal generating circuit 100, and the read-out video signal is supplied to the CRT 110.
  • the cursor control circuit 50 which is the pivot of the present invention, is constituted by cursor pattern RAMs 510 and 520, a shift register 530, a cursor display position register-X 540, a cursor display position register-Y 550, cursor data display reading registers 570 and 580, output control circuits 590 and 500, and a cursor display control circuit 560.
  • the cursor display position register-X 540 and the cursor display position register-Y 550 are connected to a slave register-X(S) 541 and a slave register-Y(S) 551 of FIG. 4 so as to constitute master to slave arrangements, respectively.
  • the timing of data transfer from the master side to the slave side is the start time of a vertical blanking interval.
  • the CPU 10 can change the set value for the slave register-X(S) 541 and the slave register-Y(S) 551 independently of the operation of the cursor control circuit 50.
  • the above-mentioned cursor data are supplied to the cursor signal generating circuit 80 so as to be converted into a video signal which is in turn mixed with the video data of the frame buffer 90 in the video signal generating circuit 100 so as to be displayed on the CRT 110.
  • FIG. 4 is a block diagram illustrating the cursor control circuit 50 in detail.
  • the shape of a cursor is defined in advance in the cursor pattern RAMs 510 and 520 by the CPU 10.
  • the display position is assigned in the cursor display position registers 540 and 550.
  • a shift control circuit 561 detects that the scanning line of the CRT 110 is in a vertical blanking interval.
  • the shift control circuit 561 reads the data of the RAM 510 by one word and sets the data in the shift register 530.
  • the number of bits of one word in the RAM 510 is the n-th power of 2 and coincides with the number of dots of a cursor pattern in the X direction.
  • the lower n bits of the X-coordinate value before renewal of the display position of the cursor are set in a shift offset register 563.
  • the set value is counted up one by one in a counter 564.
  • the contents of the shift register 530 are shifted bit by bit.
  • the shift register 530 is arranged so that its MSB output data are put into its LSB, so that data can be circulatingly shifted.
  • the count value of the counter 564 is compared in a comparator 565 with the lower n bits of the X-coordinate value after renewal of the display position, and when the value of the counter coincides with the lower n bits, the comparator 565 gives instructions to the counter 564 to stop the operation.
  • the shift control circuit 561 performs the above-mentioned shift operation upon the whole of the RAMs 510 and 520 in a vertical blanking interval.
  • FIG. 5 is a time chart for the operation.
  • a vertical blanking interval is about 1000 ⁇ s
  • the time required for shifting the whole data of the RAMs 510 and 520 is about 100 ⁇ s on the assumption that it takes 50 ns for one bit shift. Accordingly, there is enough shift time.
  • FIGS. 5 and 6 are time charts in the case of display of a cursor.
  • a dot clock is a basic one to transfer video data to the CRT 110 with the displacement of the scanning line of the CRT 110.
  • the memory cycle is an access period of the frame buffer 90. There are two purposes for accessing the frame buffer 90, one for drawing and the other for displaying. Accordingly, memory cycles are assigned for those two purposes so that the memory cycles for the two purposes are alternately executed.
  • the data read in the display cycle are latched by the video signal generating circuit 100 and converted into serial signals.
  • the display position control circuit 562 of FIG. 4 determines the display timing of the cursor on the basis of synchronizing signals (VSYNC and HSYNC) and the cursor display position registers 540 and 550.
  • the display position control circuit 562 reads the RAMs 510 and 520 into the display-read registers 570 and 580.
  • 32 bits of the data are sent out four bits by four bits through the output control circuits 590 and 500. Consequently, the operation at the same high frequency as that of the dot clock is reduced to 1/4 in the above-mentioned example, thereby facilitating the integration of the display control apparatus 40 into an LSI.
  • the output control circuit 500 forms a signal for assigning the region of bit displacement between the above-mentioned data of the registers 570 and 580, and outputs the signal after combining the signal with a signal of the register 580.
  • the cursor signal generating circuit 80 transfers a signal supplied from the output control circuit 590 to the video signal generating circuit 100. At this time, the display region of the cursor data is assigned by dot by a cursor mask signal. Therefore, by multiplexing the display and the cursor data of the frame buffer 90 by the above-mentioned cursor mask signal in the video signal generating circuit 100, it is possible to display a cursor which can be smoothly moved dot by dot on the CRT 110.
  • FIG. 7 shows an example of the operation.
  • the cursor pattern RAM 510 defines the shape to be displayed on the screen and uses the other RAM 520 as a cursor mask RAM.
  • As the pattern of the cursor mask RAM 520 a shape is defined so as to be a little larger by an order of one dot than that of the cursor pattern RAM 510. Display at the screen display portion corresponding to the mask signal is performed with a color different from the respective colors of the background and the cursor, the cursor is easy to see even if the background and the cursor are overlaid.
  • the cursor display position registers 540, 550, 541 and 551 are reset.
  • the RAMs are stored in a shifted state so as to adjust the bit displacement on the screen. Accordingly, the cursor cannot be displayed at a correct position if the contents of the RAMs are rewritten, and the above-mentioned registers are therefore reset.
  • FIG. 8 shows a system in which after reading data of cursor pattern RAMs 510 and 520 for display, the data are shifted and then returned to the RAMs 510 and 520.
  • FIG. 9 is a time chart in the system of FIG. 8. In synchronism with the cursor display timing, data are set in registers 570 and 580, and the data are also set in a shift register 530. Thereafter, the contents of the shift register 530 are shifted in the manner as shown in FIG. 4. The screen display is therefore on the basis of data before shifted. If one word of data has been shifted, the data is returned to its original address.
  • FIG. 10 shows a system in which data of cursor pattern RAMs 510 and 520 are read before display, shifted and then transferred to registers 570 and 580.
  • FIG. 11 is a time chart in the system of FIG. 10. A little before the timing to display a cursor, for example, before one raster, data are read and set in a shift register 530. Thereafter, the contents of the shift register 530 are shifted in the manner as shown in FIG. 4. After completion of shifting operation, the data are set into the registers 570 and 580, and transferred through output control circuits 590 and 500 to a cursor signal generating circuit 80 synchronously with the timing of display.
  • FIG. 12 shows an embodiment in which a cursor pattern is provided in a frame buffer 90.
  • the frame buffer 90 provided are two regions; one is to be displayed on the screen and the other is special for exclusive use for storing a cursor pattern.
  • a cursor for example, one raster of cursor data is read at the time of starting scanning one raster before the cursor is displayed, transferred to a shift means and shifted by the number of the bit displacement in order to adjust the display position.
  • the above-mentioned shifted data are transferred to a video signal generating circuit.
  • a special region for exclusive use for a cursor pattern is provided in a specific region of a system memory 20.
  • a memory access control portion 120 is started one raster before displaying the pattern, and data are read from the above-mentioned pattern region.
  • the thus read data are converted into a video signal so as to be displayed on a CRT, for example, in the manner as has been described in FIG. 12.
  • the present invention by separating a reading processing for displaying a cursor pattern from an adjusting processing for adjusting the dot position of the pattern data on a screen, it is possible to realize high speed movement of a cursor on the screen without requiring high speed operation of the pattern dot position adjusting processing. Moreover, since it is possible to reduce portions which require high speed operation, it is easy to integrate the system in an LSI, so that it is possible to realize an inexpensive display control apparatus.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
US07/583,584 1989-09-20 1990-09-17 Cursor display control method and apparatus in a graphic display system Expired - Fee Related US5192943A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1242256A JPH03105385A (ja) 1989-09-20 1989-09-20 表示制御装置
JP1-242256 1989-09-20

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US (1) US5192943A (ko)
EP (1) EP0418859B1 (ko)
JP (1) JPH03105385A (ko)
KR (1) KR100210496B1 (ko)
DE (1) DE69019649T2 (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5642132A (en) * 1993-05-10 1997-06-24 U.S. Philips Corporation Circuit arrangement for controlling the display of a cursor symbol of variable magnitude and shape in a cursor field of variable magnitude
US7158127B1 (en) * 2000-09-28 2007-01-02 Rockwell Automation Technologies, Inc. Raster engine with hardware cursor
US20110310011A1 (en) * 2010-06-22 2011-12-22 Hsni, Llc System and method for integrating an electronic pointing device into digital image data

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345252A (en) * 1991-07-19 1994-09-06 Silicon Graphics, Inc. High speed cursor generation apparatus
US5559533A (en) * 1994-04-02 1996-09-24 Vlsi Technology, Inc. Virtual memory hardware cusor and method
EP0734011A3 (en) * 1995-03-21 1999-01-20 Sun Microsystems, Inc. Field synchronization of independent frame buffers

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4326201A (en) * 1979-04-27 1982-04-20 Tokyo Shibaura Denki Kabushiki Kaisha Apparatus for displaying characters
US4454507A (en) * 1982-01-04 1984-06-12 General Electric Company Real-time cursor generator
US4706074A (en) * 1986-01-17 1987-11-10 International Business Machines Corporation Cursor circuit for a dual port memory
US4768029A (en) * 1986-05-28 1988-08-30 International Computers Limited Video display system with graphical cursor
US4835526A (en) * 1985-03-19 1989-05-30 Ascii Corporation Display controller

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4668947A (en) * 1983-08-11 1987-05-26 Clarke Jr Charles J Method and apparatus for generating cursors for a raster graphic display
JPS60256842A (ja) * 1984-06-04 1985-12-18 Yokogawa Hokushin Electric Corp 移動図形表示装置
JPS62269992A (ja) * 1986-05-19 1987-11-24 富士通株式会社 パタ−ン重畳方式

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4326201A (en) * 1979-04-27 1982-04-20 Tokyo Shibaura Denki Kabushiki Kaisha Apparatus for displaying characters
US4454507A (en) * 1982-01-04 1984-06-12 General Electric Company Real-time cursor generator
US4835526A (en) * 1985-03-19 1989-05-30 Ascii Corporation Display controller
US4706074A (en) * 1986-01-17 1987-11-10 International Business Machines Corporation Cursor circuit for a dual port memory
US4768029A (en) * 1986-05-28 1988-08-30 International Computers Limited Video display system with graphical cursor

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5642132A (en) * 1993-05-10 1997-06-24 U.S. Philips Corporation Circuit arrangement for controlling the display of a cursor symbol of variable magnitude and shape in a cursor field of variable magnitude
US7158127B1 (en) * 2000-09-28 2007-01-02 Rockwell Automation Technologies, Inc. Raster engine with hardware cursor
US7808448B1 (en) 2000-09-28 2010-10-05 Rockwell Automation Technologies, Inc. Raster engine with hardware cursor
US20110310011A1 (en) * 2010-06-22 2011-12-22 Hsni, Llc System and method for integrating an electronic pointing device into digital image data
US8717289B2 (en) * 2010-06-22 2014-05-06 Hsni Llc System and method for integrating an electronic pointing device into digital image data
US20140201790A1 (en) * 2010-06-22 2014-07-17 Hsni, Llc System and method for integrating an electronic pointing device into digital image data
US9094707B2 (en) * 2010-06-22 2015-07-28 Hsni Llc System and method for integrating an electronic pointing device into digital image data
US20150249706A1 (en) * 2010-06-22 2015-09-03 Hsni Llc System and method for integrating an electronic pointing device into digital image data
US9294556B2 (en) * 2010-06-22 2016-03-22 Hsni, Llc System and method for integrating an electronic pointing device into digital image data
US20160156705A1 (en) * 2010-06-22 2016-06-02 Hsni, Llc System and Method for Integrating an Electronic Pointing Device into Digital Image Data
US9948701B2 (en) * 2010-06-22 2018-04-17 Hsni, Llc System and method for integrating an electronic pointing device into digital image data
US10270844B2 (en) * 2010-06-22 2019-04-23 Hsni, Llc System and method for integrating an electronic pointing device into digital image data
US20190253479A1 (en) * 2010-06-22 2019-08-15 Hsni, Llc System and method for integrating an electronic pointing device into digital image data

Also Published As

Publication number Publication date
KR100210496B1 (ko) 1999-07-15
EP0418859B1 (en) 1995-05-24
JPH03105385A (ja) 1991-05-02
DE69019649T2 (de) 1995-10-19
EP0418859A1 (en) 1991-03-27
DE69019649D1 (de) 1995-06-29
KR910006865A (ko) 1991-04-30

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