US3808058A - Fabrication of mesa diode with channel guard - Google Patents

Fabrication of mesa diode with channel guard Download PDF

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Publication number
US3808058A
US3808058A US00281295A US28129572A US3808058A US 3808058 A US3808058 A US 3808058A US 00281295 A US00281295 A US 00281295A US 28129572 A US28129572 A US 28129572A US 3808058 A US3808058 A US 3808058A
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United States
Prior art keywords
mesa
mask
slice
silicon nitride
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US00281295A
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English (en)
Inventor
S Henning
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AT&T Corp
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Bell Telephone Laboratories Inc
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Filing date
Publication date
Application filed by Bell Telephone Laboratories Inc filed Critical Bell Telephone Laboratories Inc
Priority to US00281295A priority Critical patent/US3808058A/en
Priority to CA164,715A priority patent/CA967292A/en
Priority to FR7328497A priority patent/FR2196521A1/fr
Priority to NL7311147A priority patent/NL7311147A/xx
Priority to BE134506A priority patent/BE803528A/xx
Priority to IT51989/73A priority patent/IT990232B/it
Priority to DE19732341374 priority patent/DE2341374A1/de
Priority to JP48091819A priority patent/JPS4960479A/ja
Application granted granted Critical
Publication of US3808058A publication Critical patent/US3808058A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/113—Nitrides of boron or aluminum or gallium
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/114—Nitrides of silicon

Definitions

  • the silicon nitride mask is undercut 29/583 leaving an overhang which then is utilized as a shadow w mask for an ion implantation step.
  • the ion implanta- [56] References Cited tion step produces a channel guard zone which, be-
  • This invention relates to the fabrication of a semiconductor diode of the mesa type having a channel guard zone. More particularly, it is related to a fabrication process utilizing selective etching and ion implantation to produce advantageously a semiconductor rectifier having suitably high voltage breakdown.
  • High voltage semiconductor diodes of the P-N junction type require a relatively high level of breakdown in the reverse direction.
  • devices of this type have been fabricated in the planar configuration, such structures are more susceptible to breakdown as a consequence of the sharp curvature of the junction characterized by the planar form.
  • the surface effects of planar junctions require extraordinary measures to prevent surface breakdown. Consequently, the mesa configuration has generally been found more advantageous from the standpoint of high voltage characteristics.
  • this configuration avoids the junction curvature problem, there are still surface breakdown problems which are most conveniently overcome by the provision of a channel guard zone of suitable conductivity type material.
  • semiconductor diodes are fabricated in batch form in which a large number of diodes are produced from a single slice of silicon semiconductor material.
  • the slice is subjected to solid state diffusion or equivalent treatment to produce a P-N junction through the entire slice parallel to the major faces of the slice.
  • a mask of silicon nitride is formed on one major face of the slice in a pattern defining the top surface of the mesas of the individual diodes.
  • the mesas are formed by treating the masked surface of the slice with an etchant which attacks the exposed semiconductor material but does not substantially attack the silicon nitride mask.
  • etching treatment is isotropic, that is, it proceeds at a substantially equal rate in all directions against the semiconductor material, moats are formed by removal of material downward into the slice and laterally be-' neath the silicon nitride mask as well.
  • the etching step there is an undercutting therefore of the mask and the consequent overhang of the silicon nitride layer'is used to mask an ion implantation step which follows.
  • conductivity type zones of relatively high conductivity and of like conductivity to the bulk portion of the diode are formed in a zone at the bottom of each moat.
  • the lateral extent of these ion implanted zones is precisely determined and the implanted zones are suitably spaced away from the exposed boundary of the active P-N junction located in each mesa.
  • the slice then is cut apart approximately through the bottom of each moat to form a plurality of individual mesa diodes, each having a high conductivity channel guard zone adjoining the periphery of each diode and spaced away from the P-N junction edge.
  • the process in accordance with this invention advantageously provides a channel guard zone without significant addition of processing steps and without complex masking operations.
  • FIGS. 1 through 6 are cross sections of a portion of a semiconductor slice illustrating a sequence of fabrication steps in accordance with the invention.
  • FIG. 7 is a cross-sectional view of a completed semiconductor diode in accordance with the invention.
  • the portion 10 represents a segment of a slice which may be from one to two or more inches in diameter and about 9 or 10 mils in thickness, conventionally utilized as the base material for fabricating semiconductor devices in batch form.
  • the N-type portion 11 is subjected to solid state diffusion treatments, typically using boron and phosphorus as the significant impurities to produce a P-type zone 12 adjacent one face of the slice and a high conductivity N+ zone 13 adjacent the opposite face.
  • the depth of these zones is about 1.3 mils in a slice having a total thickness originally of 9 mils.
  • P and N+ terminal zones may be formed by a variety of techniques well known in the art. They may be formed by sequential selective diffusion or by simultaneous diffusion using paint-on techniques as well as by ion implantation.
  • the structure, as shown in FIG. 2, is a conventional configuration in the fabrication of P-N junction semiconductor diodes.
  • the slice is shown with a layer 14 of silicon nitride on the boron diffused, or junction face of the slice; that is, the face of the slice which is closest to the active P-N junction 17.
  • the layer 14, of silicon nitride is formed by any one of a number of deposition processes which are well known in the art. One convenient technique utilizes a reaction at high temperature using silicon tetrachloride and ammonia.
  • the layer 14 conveniently has a thickness of about 2,500 angstroms.
  • the silicon nitride is treated, typically by plasma etching with a fluorinecontaining plasma selectively, to produce the mask for etching the mesas of the diodes.
  • a technique for selective etching of silicon nitride is to form, by conventional photoresist techniques, an etch-resistant mask which resists the plasma etch and enables selective etching of the silicon nitride.
  • the masked surface of the slice of FIG. 4 then is treated with an etchant such as a mixture of hydrofluoric, nitric and acetic acids in the ratio 523:3, by volume, to etch the moats 15 shown in the view of FIG. 5.
  • an etchant such as a mixture of hydrofluoric, nitric and acetic acids in the ratio 523:3, by volume, to etch the moats 15 shown in the view of FIG. 5.
  • This etchant does not substantially attack the silicon nitride mask 14.
  • the moats 15 have a depth of about 3.5 mils, thus penetrating well below the level of the P-N junction 17.
  • the etchant is substantially isotropic, there is an undercutting of the silicon nitride mask 14. Such undercutting typically may produce an overhang of about 2 mils. As shown in FIG.
  • this overhang is taken advantage of in conjunction with an ion implantation treatment, represented by the arrows 16, to form shallow N+-type zones 18 adjacent the bottom of the moats.
  • the significant feature of this processing step is that the lateral extent of these N-type zones 18 is precisely defined by the overhanging edge of the undercut silicon nitride mask 14 and the straight line path which is characteristic of the ion beam. Consequently, the boundaries of the N+ zones 18 are inherently spaced away from the boundary of the active P-N junction 17 in the mesa by the lateral dimension of the mask overhang.
  • the ion implantation step typically implants phosphorus at about 30 Kev to an impurity concentration level of at least 1X10 per square centimeter.
  • a semiconductor device of similar configuration, but having reversed conductivity types may be similarly fabricated utilizing suitable significant impurities by following the same procedural steps.
  • the etching mask can be formed of other materials than silicon nitride, such as aluminum oxide or a silicone resin.
  • Individual semiconductor diodes are fabricated by dividing the slice of FIG. 6 into individual mesa containing dies. Prior to such division, conventional treatment steps for the slice may comprise removal of all masking layers, followed by the formation of a silicon oxide film over the active surface of the slice, followed by a second layer of silicon nitride. Contact windows then are opened by selective etching to expose a portion of the top surface of each mesa. Contact metal then is applied to opposite exposed semiconductor faces of the slice and the slice then divided into individual dies.
  • the final device, ready for mounting is as shown in FIG. 7 in which 22 and 23 are the two metallic contact members forming the device terminals and 21 is the dual dielectric coating of silicon nitride and the silicon oxide.
  • the peripherally disposed implanted zone 18 acts as a channel guard to stop surface leakage. In the absence of such a guard,
  • the diode exhibits a conductivity inversion at the surface in the presence of moisture, causing high leakage currents and unstable, low breakdown voltages.
  • the implanted guard zone 18, precisely spaced away from the exposed boundary of P-N junction 17, enables low leakage currents and stable, high breakdown voltages.
  • a method for fabricating semiconductor devices of the mesa type comprising providing a slice of semiconductor material of one conductivity type, said slice having plane, parallel major surfaces, converting a portion of said slice adjacent one surface to the opposite conductivity type thereby forming a P-N junction within said slice substantially parallel to the major surfaces of said slice, forming a masking layer of etch resistant material on said one surface in a pattern defining the top surfaces of the mesas to be formed by the etching process, treating said masked surface with an etchant which attacks the exposed semiconductor material substantially isotropically thereby forming an array of moats surrounding the mesas, said moats having a depth below the level of said P-N junction whereby an edge of said P-N junction is exposed on the wall of each mesa and thereby producing an overhanging portion of said masking layer on each mesa as a result of undercutting of the semiconductor material by the etchant, exposing said mesa etched surface to an ion

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
US00281295A 1972-08-17 1972-08-17 Fabrication of mesa diode with channel guard Expired - Lifetime US3808058A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US00281295A US3808058A (en) 1972-08-17 1972-08-17 Fabrication of mesa diode with channel guard
CA164,715A CA967292A (en) 1972-08-17 1973-02-27 Fabrication of mesa diode with channel guard
FR7328497A FR2196521A1 (de) 1972-08-17 1973-08-03
BE134506A BE803528A (fr) 1972-08-17 1973-08-13 Procede de fabrication de dispositifs semi-conducteurs
NL7311147A NL7311147A (de) 1972-08-17 1973-08-13
IT51989/73A IT990232B (it) 1972-08-17 1973-08-13 Fabbricazione di diodo mesa con guardia a canale
DE19732341374 DE2341374A1 (de) 1972-08-17 1973-08-16 Verfahren zur herstellung eines halbleiterbauelements in mesastruktur
JP48091819A JPS4960479A (de) 1972-08-17 1973-08-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00281295A US3808058A (en) 1972-08-17 1972-08-17 Fabrication of mesa diode with channel guard

Publications (1)

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US3808058A true US3808058A (en) 1974-04-30

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US00281295A Expired - Lifetime US3808058A (en) 1972-08-17 1972-08-17 Fabrication of mesa diode with channel guard

Country Status (8)

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US (1) US3808058A (de)
JP (1) JPS4960479A (de)
BE (1) BE803528A (de)
CA (1) CA967292A (de)
DE (1) DE2341374A1 (de)
FR (1) FR2196521A1 (de)
IT (1) IT990232B (de)
NL (1) NL7311147A (de)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4014714A (en) * 1974-08-08 1977-03-29 Siemens Aktiengesellschaft Method of producing a monolithic semiconductor device
US4030954A (en) * 1974-09-30 1977-06-21 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device
US4044454A (en) * 1975-04-16 1977-08-30 Ibm Corporation Method for forming integrated circuit regions defined by recessed dielectric isolation
US4046595A (en) * 1974-10-18 1977-09-06 Matsushita Electronics Corporation Method for forming semiconductor devices
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
US4080245A (en) * 1975-06-17 1978-03-21 Matsushita Electric Industrial Co., Ltd. Process for manufacturing a gallium phosphide electroluminescent device
US4091408A (en) * 1976-05-21 1978-05-23 Hughes Aircraft Company High frequency ion implanted passivated semiconductor devices and mircowave intergrated circuits and planar processes for fabricating both
US4149904A (en) * 1977-10-21 1979-04-17 Ncr Corporation Method for forming ion-implanted self-aligned gate structure by controlled ion scattering
US4276098A (en) * 1980-03-31 1981-06-30 Bell Telephone Laboratories, Incorporated Batch processing of semiconductor devices
US5268310A (en) * 1992-11-25 1993-12-07 M/A-Com, Inc. Method for making a mesa type PIN diode
US20060148185A1 (en) * 2004-12-31 2006-07-06 Shin Yong W Method for manufacturing high voltage transistor
WO2007142603A1 (en) * 2006-06-09 2007-12-13 Agency For Science, Technology And Research An integrated shadow mask and method of fabrication thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011161Y2 (ja) * 1979-05-16 1985-04-13 三菱重工業株式会社 コンクリ−トパイルの杭頭部破砕処理装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3484313A (en) * 1965-03-25 1969-12-16 Hitachi Ltd Method of manufacturing semiconductor devices
US3607449A (en) * 1968-09-30 1971-09-21 Hitachi Ltd Method of forming a junction by ion implantation
US3639975A (en) * 1969-07-30 1972-02-08 Gen Electric Glass encapsulated semiconductor device fabrication process
US3675313A (en) * 1970-10-01 1972-07-11 Westinghouse Electric Corp Process for producing self aligned gate field effect transistor
US3728179A (en) * 1970-05-20 1973-04-17 Radiation Inc Method of etching silicon crystals
US3730778A (en) * 1970-01-15 1973-05-01 Philips Corp Methods of manufacturing a semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3484313A (en) * 1965-03-25 1969-12-16 Hitachi Ltd Method of manufacturing semiconductor devices
US3607449A (en) * 1968-09-30 1971-09-21 Hitachi Ltd Method of forming a junction by ion implantation
US3639975A (en) * 1969-07-30 1972-02-08 Gen Electric Glass encapsulated semiconductor device fabrication process
US3730778A (en) * 1970-01-15 1973-05-01 Philips Corp Methods of manufacturing a semiconductor device
US3728179A (en) * 1970-05-20 1973-04-17 Radiation Inc Method of etching silicon crystals
US3675313A (en) * 1970-10-01 1972-07-11 Westinghouse Electric Corp Process for producing self aligned gate field effect transistor

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4014714A (en) * 1974-08-08 1977-03-29 Siemens Aktiengesellschaft Method of producing a monolithic semiconductor device
US4030954A (en) * 1974-09-30 1977-06-21 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device
US4046595A (en) * 1974-10-18 1977-09-06 Matsushita Electronics Corporation Method for forming semiconductor devices
US4044454A (en) * 1975-04-16 1977-08-30 Ibm Corporation Method for forming integrated circuit regions defined by recessed dielectric isolation
US4080245A (en) * 1975-06-17 1978-03-21 Matsushita Electric Industrial Co., Ltd. Process for manufacturing a gallium phosphide electroluminescent device
US4091408A (en) * 1976-05-21 1978-05-23 Hughes Aircraft Company High frequency ion implanted passivated semiconductor devices and mircowave intergrated circuits and planar processes for fabricating both
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
US4149904A (en) * 1977-10-21 1979-04-17 Ncr Corporation Method for forming ion-implanted self-aligned gate structure by controlled ion scattering
US4276098A (en) * 1980-03-31 1981-06-30 Bell Telephone Laboratories, Incorporated Batch processing of semiconductor devices
US5268310A (en) * 1992-11-25 1993-12-07 M/A-Com, Inc. Method for making a mesa type PIN diode
US20060148185A1 (en) * 2004-12-31 2006-07-06 Shin Yong W Method for manufacturing high voltage transistor
WO2007142603A1 (en) * 2006-06-09 2007-12-13 Agency For Science, Technology And Research An integrated shadow mask and method of fabrication thereof

Also Published As

Publication number Publication date
BE803528A (fr) 1973-12-03
FR2196521A1 (de) 1974-03-15
DE2341374A1 (de) 1974-03-14
IT990232B (it) 1975-06-20
NL7311147A (de) 1974-02-19
JPS4960479A (de) 1974-06-12
CA967292A (en) 1975-05-06

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