US3676789A

US3676789A - Low distortion agc amplifier

Info

Publication number: US3676789A
Application number: US89994A
Authority: US
Inventors: Derek Bray
Original assignee: Individual
Current assignee: Individual
Priority date: 1970-11-16
Filing date: 1970-11-16
Publication date: 1972-07-11
Anticipated expiration: 1989-07-11

Abstract

A linear amplifier in an automatic gain control circuit whose gain is a function of the ratio of two bias currents is obtained by selectively coupling two pairs of semiconductor devices such that the effects of nonlinearities due to the logarithmic relationship between voltage and current across a PN junction cancel. The relationship between the two pairs of devices is such that the output signal from the second pair of devices is linearly related to the input signal driving the first pair of devices.

Description

United States Patent Bray [451 July 11, 1972 [54] LOW DISTORTION AGC AMPLIFIER [72] Inventor: Derek Bray, Fuchstanzstrasse i2,

Stierstadt/Taunus. Germany [22] Filed: Nov. 16, 1970 [2] Appl. No.: 89,994

Related 0.8. Application Data [63] Continuation-impart of Ser. No. 827,749, May 26,

I969. abandoned.

[52 us. Cl. .330/29, 330/30 D, 330/134 51 1 Int. Cl. .1103; 3/30 [58] Field of Search ..330/293 OR, 30 D, 33 R, as M,

[56] References Cited UNITED STATES PATENTS McGraw et al. .....................330l30 D 3,444,472 5/1969 Johnson ..330/30 D X Primary Examiner-Roy Lake Assistant Examiner-Junes B. Mullins Anome \-Roger S. Borovoy and Alan H. MacPherson [57] ABSTRACT A linear amplifier in an automatic gain control circuit whose gain is a function of the ratio of two bias currents is obtained by selectively coupling two pairs of semiconductor devices such that the effects of nonlinearities due to the logarithmic relationship between voltage and current across a PN junction cancel. The relationship between the two pairs of devices is such that the output signal from the second pair of devices is linearly related to the input signal driving the first pair of devices.

10 Claims, 4 Drawing figures i t F w DETECTOR M g 3 Patented July 11, 1972 3 Sheets-Sheet l FIG.I

DETECTOR REFERENCE CURRENT SOURCE SOURCE CURRENT w V V a o Q l I I .J 7 4 .mm 5 m 6 w L7 m 2. GF F I I I I f INVENTOR.

DEREK BRAY BY mm x/ m ATTORNEYS Patented July 11, 1972 FIG. 3

(A) IN PUT 3 Sheets-Sheet A.c. CURRENT THROUGH 0 \/A.CTCURRENT THROUGH 06 INVENTOR,

DEREK BRAY BYM'L/MMV ATTORNEYS Patented July 11, 1972 I5 Sheets-Sheet 3 INVENTOR.

DEREK BRAY. BY dam H,

ATTORNEYS vdE LOW DISTORTION AGC AMPLIFIER CROSS-REFERENCE TO RELATED APPLICATION This is a continuation-in-part of application Ser. No. 827,749 filed May 26, I969, now abandoned.

BACKGROUND OF THE INVENTION I Field of the Invention This invention relates to automatic gain control amplifiers and in particular, to an automatic gain control amplifier, capable of being produced as an integrated circuit, which has low distortion and a gain which is independent of the non-linearities of the circuit elements.

2. Brief Description of the Prior Art Automatic gain control amplifiers using solid state components such as diodes and transistors are well known. However, such amplifiers typically have either poor linearity, poor signal handling capabilities, restricted frequency range, high noise, great temperature sensitivity, large power dissipation, poor inter-modulation performance, or restricted automatic gain control range. Circuits which overcome one or more of those limitations are known. However, no circuit is known which substantially overcomes all these limitations.

SUMMARY OF THE INVENTION This invention on the other hand, provides an automatic gain control circuit which substantially overcomes all of the above limitations. The circuit of this invention relies on the inherent logarithmic characteristics of semiconductor devices, such as diodes and transistors, to cancel out the effect of these nonlinear characteristics on signals processed by these devices. The gain of this circuit is dependent primarily on the ratio of two currents provided by current bias sources. Thus, the gain is substantially independent of temperature, provided the bias current ratio remains constant with temperature changes. When operated within the signal handling capabilities of the circuit, the output signal is undistorted and inter modulation is minimized.

According to this invention, an automatic gain control circuit contains two coupled pairs of active devices, each pair typically consisting of either transistors or diodes. An input signal passes through a differential amplifier to drive the first pair of devices and the output signal is taken from the second pair of devices. Two current sources bias the two coupled pairs of devices. The transconductance of the combined two pairs of devices and the difi'erential amplifier is primarily a function of the ratio of the currents from the two current sources. By selectively varying the ratio of the currents from the two current sources, the amplitude of the output signal from the second pair of devices is held constant despite variations in the amplitude of the input signal to the differential amplifier.

As a feature of this invention, the nonlinear characteristics of the first pair of active devices are compensated for by coupling the second pair of active devices to the first pair of devices in such a manner that current changes in the devices in the first pair are linearly related to the resulting current changes in the devices in the second pair over a wide range of signal amplitudes. The relationship between the two pairs of devices is such that the output signal from the second pair of devices is linearly related to the input signal driving the first pair of devices, the nonlinear characteristics of the devices cancelling due to the unique manner of connecting the two pairs of devices.

As a result of the linear relationship of the output signal to the input signal, harmonic distortion and intermodulation of the output signal are minimized. For example, harmonic distortion in a typical embodiment is usually down at least 30 db from the fundamental. Additionally, in one embodiment of this invention the linearity of the circuit caused intermodulation products from two equal-amplitude input signals separated by SOKIIz at both 500 KHz and 30 MHz center frequencies to be at least 50 db down from from either input signal. Significantly, the pairing of transistors and/or diodes as required by this invention is particularly suitable for producing an integrated circuit version of this invention.

Other characteristics and advantages of this invention will become apparent from the following detailed description of selected embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows schematically the basic system of this invention;

FIG. 2 shows in more detail the circuitry of selected ones of the components shown in FIG. I;

FIGS. 3a through 3d show the signals generated at various points throughout the circuit of FIG. 2;

FIG. 4 is a circuit diagram of a typical circuit using the principles of this invention.

DETAILED DESCRIPTION FIG. I shows schematically the circuit of this invention. An input signal, represented by voltage V,,,, is operated upon in amplifier l0 and passed to detector 50, which produces a DC signal with an amplitude proportional to the average amplitude of the output signal from amplifier l0. Detector 50 comprises in its simplest embodiment, a rectifier and a low pass filter. The output signal from detector 50 is, in turn, fed back and used to control the magnitudes of the currents from

current sources

20 and 30. Current source 20 supplies a current 1 to amplifier 10 while current source 30 supplies a current I, to amplifier l0. Amplifier I0 is arranged so that its transconductance l /V is a function solely of the ratio I,/I for given load resistors in amplifier I0. Thus, so long as the ratio of currents 1 remains constant and independent of temperature, the gain of amplifier 10 will likewise remain constant, independent of temperature.

During the operation of amplifier 10, which might for example, be a video amplifier, the amplitude of V will frequently vary. However, it is usually desired to maintain constant the amplitude of the output signal from amplifier 10. To do this, the ratio [,ll of currents from

current sources

20 and 30 must be appropriately varied to adjust the gain of amplifier 10 in the proper direction.

Current sources

20 and 30 are thus controlled to hold the amplitude of the output signal from detector S0 to a desired relationship to the amplitude of the output signal from reference source 40.

FIG. 2 shows in more detail the circuit of amplifier [0 together with

current sources

20 and 30. An input signal V is applied to leads I01 and 102. If V (for illustration purposes assumed to be a sinusoid initially increasingly positive with time as shown in FIG. 3a) is applied across leads 102 and [01 connected to the bases of transistors Q1 and Q2 respectively, O1 is driven positive and conducts an increasingly larger A.C. current I as shown in FIG. 3b. On the other hand, lead l0], connected to the base of transistor 02, is initially driven negative relative to lead 102 by V,,,. Thus the current through ()2 decreases by the amount I Current source 20 draws a constant current I Initially the current I divides equally between 01 and Q2 as a result of R3 and R4 being substantially equal. To maintain the total current supplied to current source 20 constant, an increase in current supplied by transistor Q1 must be matched by a decrease in current supplied by transistor Q2.

The currents drawn by transistors Q1 and Q2 pass through transistors 03 and 04 respectively, connected as diodes. A current increase through 03 is matched by an equal current decrease through Q4.

The voltage V across the emitter-base junction of a transistor increases logarithmically with the current I across this junction according to the well-known relationship 8. V=[kT/q]ln[l+l/l,,]

where I, is some initial current, 3

q is the electronic charge,

It is Boltzmanns constant, and

T is absolute temperature.

As the voltage across the emitter-base junction of transistor Q3 increases because of the increase in the current drawn by transistor Q1 across this junction, the voltage across the emitter-base junction of transistor Q4 decreases because of the decrease in the current drawn by transistor Q2 across Q4's emitter-base junction. Because, of the nonlinear relationship between current and voltage given by Equation (1), these two voltage changes across the emitter-base junctions of transistors Q3 and Q4 are not equal in magnitude. Rather, the voltage changes across Q3 and Q4 are very much dependent upon the direction in which the current changes as well as upon the magnitude of the current change. Thus, as shown in FIG. 30, the voltage V, on the emitter of transistor Q3 and the collector of transistor Ql varies in a highly nonlinear fashion, and is substantially 180 out of phase with the voltage V, on the emitter of transistor Q4 and the collector of transistor Q2.

Now, the voltage V, drives the base of transistor Q5, while the voltage V, drives the base of transistor Q6. As the voltage V, drops with an increase in current through transistor Q3, transistor Q6 is driven to conduct less current. Thus the voltage on the collector of Q6 increases. On the other hand, at the same instant, the voltage V is increasing. This drives transistor Q5 to conduct more current, thereby decreasing the voltage on its collector 103. Because of the cancelling effects of the logarithmic characteristics of Q3 and Q6, and Q4 and Q5, the output signal on leads I03 and 104 is linearly related to the input signal on leads l] and 102.

Transistors Q and Q6 are connected to current source 30. Because current source 30 draws the constant current I,, an increase in the current drawn by this source through transistor Q5 is matched by a decrease in the current drawn by this source through transistor Q6.

An analysis of the circuit of FIG. 2 shows that the AC. signal current I, in transistor 01 is given by 1,, v,,, R3 R4) 2. Likewise, the AC. signal current in transistor O2 is given by I, V,,, R3+R4) 3. The DC. current through each of transistors Q1, Q2, Q3 and Q4 equals I 12. The DC. current through each of transistors Q5 and Q6 equals I,/2. If the A.C. signal current in Q6 equals I,, and the AC signal current in Q5 equals +I,,, then taking equation l above, and assuming r:""" is much greater than unity, we can write for Q3 where V, equals the base voltage on Q3 and on Q4) and V, equals 03's steady state emitter voltage V plus the AC signal voltage on Q3s emitter, (v,). Thus where V equals the base voltage on Q4 (and on Q3) and V, equals Q4's steady state emitter voltage V plus the A.C. signal voltage on 04's emitter (v Thus (12 2 0 "w Combining equations (4) and (5) we get (I,+2 l,,)/(I,2I,,) ==e"a"""eb Likewise, combining equations (6) and (7) we get By combining equations (8), (9) and (2), we find that the AC output current I, is related to the input voltage V, by the following relationship It should be noted that I has been defined as positive when decreasing the emitter current through Q6. If I, is considered as positive when increasing the emitter current through 06, then a minus sign should precede the term on the right hand side of equation [0).

Equation (10) shows that the ratio of the output current I to the input voltage V is given by the ratio of currents IJI, from

current sources

30 and 20 divided by the sum of R3 and R4, the emitter resistors of transistors Q1 and 02 respectively. Therefore, the transconductance of the circuit shown in FIG. 2 is independent of all effects except those which affect the current sources I, and I,. As shown by the fact that the logarithmic terms cancel from equation 10), the logarithmic characteristics of transistors Q3, Q4, Q5 and Q6 have no effect upon the output gain of the circuit provided these transistors are always forward biased. Likewise, temperature changes and environmental changes have no effect on the output gain of the circuit provided R3 and R4 do not vary with temperature and provided the ratio l,/I is independent of temperature. In a properly designed circuit, such as shown in FIG. 4, I,/l is substantially constant over a wide range of temperature variations.

FIG. 4 shows the diagram of a circuit built using the principles of this invention. The circuit shown in FIG. 4 contains two automatic gain control stages of the type shown in FIG. 2. The first stage, driven by an input signal V,,, on leads 1 and 2, includes transistors 01 and Q2, connected as a differential amplifier, a first pair of semiconductor devices transistors 03 and Q4driven by a signal from the differential amplifier, and a second pair of semiconductor devicestransistors Q5 and Q6 coupled to Q3 and Q4 according to the principles of this invention to cancel out device nonlinearities.

A current source, consisting of transistors Q7 and Q9 draws a total current 1 through transistors 01 and Q2, their emitter resistors R5 and R6, and transistors Q3 and Q4.

As discussed earlier, in the absence of an input signal on leads I and 2, half this current passes through transistors 01 and Q3 and resistor R5 while the other half of this current passes through transistors Q2 and Q4 and resistor R6. Transistor Q9 is forward biased by transistor Q10 connected as a diode across Q9s base and emitter leads. Transistor Q7 is connected to input lead 4 which in turn is connected to detector circuit 50 (FIG. I). When the voltage on lead 4 increases due to an increase in the average amplitude of the rectified output signal from amplifier 10 (FIG. I), transistor Q7 draws more bias current I through transistors 01, Q2, Q3 and Q4. The emitter current through transistor Q7 thus changes, changing the voltage drop across resistor R10 which is part of a resistive network including resistors R8 and R9. An increase in voltage across resistor R10 increases the emitter voltage on transistor Q8, and thus decreases the bias current I, drawn by transistor Q8 and resistor R" through the output pair of transistors Q5 and Q6 in the first automatic gain-control stage.

The base voltage on Q8 is a reference voltage supplied from voltage source through the resistive network including resistors R12, R13, R14, R16 and R19, diodes DI and D2 and zener diode D3. Diodes DI and D2, together with transistor Q10 connected as a diode across the base-emitter junction of transistor Q9, assist in holding the current ratio IJI, constant despite temperature variations.

The output signal from transistor Q6 is passed through cascade-connected transistor Q27 which acts as an impedance transformer and then through coupling capacitor C1 (external to the integrated circuit version of this invention) to the base of transistor Q16, the input of the second automatic gain-control amplifier. Transistor Q28 serves to hold the base voltage on Q27 at a desired value and supplies to 027 its base current.

The second automatic gain-control amplifier is substantially identical to the first. It includes a differential amplifier consisting of transistors Q16 and Q17 connected to a first pair of semiconductor devices, transistors Q14 and Q15. Transistors Q14 and 015 are connected to a second pair of semiconductor devices, transistors Q20 and Q21, in such a manner as to cancel the non-linearities of the two pairs of devices. The input to this second AGC circuit is the base of Q16. The output, which is the collector voltage on Q21 developed across load resistor R29 by the emitter current of Q13, drives transistor Q22, connected as an emitter follower. The current through Q22 passes through a voltage divider network including transistor Q26, together with resistor R30 coupling the collector of 026 to its base, resistor R31 coupling the base of Q26 to its emitter, and resistor R32. Q26 effectively acts as a high impedance to DC. current but as a low impedance to A.C. current, thus efiiciently coupling the A.C. signal from 022 through to the output of the circuit while selectively reducing the DC bias voltage at the output of the circuit. Load resistor R32 connected to the emitter of Q26 has as produced across it an output voltage which drives the bases of transistors Q23 and 024, connected to form a differential amplifier. Circuit output leads 7 and 8 are connected to the collectors of Q24 and 023 respectively. However, the base of transistor Q24, which is connected to lead 6 of the integrated circuit version of this amplifier, is capacitively coupled to ground by capacitor C2 which forms an RF short circuit at the desired operating frequency of the circuit. Transistor 025, the base of which is driven by the reference voltage generated across resistor R12 (which likewise drives the base of Q8) acts as a constant current source drawing bias current through Q23 and Q24.

Two current sources likewise bias the second AGC amplifier. The first current source, consisting of transistor Q18 together with resistor R26 and R28, and transistor Q12, draws the current l through the transistors Q16 and Q17, their emitter resistors R24 and R25, and transistors Q14 and Q15. The second current source, consisting of transistor Q19 together with resistors R37, R27 and R28, draws the current l through transistors Q20 and Q21.

An increase in the amplitude of the output signal from this two-stage AGC amplifier increases the level of the DC. output signal from detector 50 (FIG. 1). This DC output signal is fed back to pin 4 of the integrated circuit version of FIG. 4. Pin 4 is connected both to the base of transistor Q7 in the first current source of the first AGC amplifier and to the base of transistor Q18 in the first current source in the second AGC amplifier. An increase in the level of this DC signal increases the current drawn by transistors Q7 and Q18. This increase in current increases the emitter voltages on transistors Q8 and 019. Because the base voltage on Q8 and Q19 is held constant by the voltage across resistor R12, transistors Q8 and Q19 conduct proportionately less current. As a result, the ratios of currents IJI, and IJI, from the four current sources associated with the two AGC stages drop. This lowers the gain of the two AGC stages in accordance with equation (l0), and thus the amplitude of the output signal from detector 50 (FIG. I). This process continues until the amplitude of the output signal from detector 50 again assumes its desired level.

Likewise, when the amplitude of the output signal from detector 50 drops beneath its desired value, the ratios [,II, and [J], associated with the two AGC amplifier stages increase, thereby increasing the amplitude of the output signal from detector 50 to its desired value. Changing R12 varies the reference voltage on the bases of transistors Q8 and Q19 and thus changes the nominal gain of the two stage AGC amplification circuit shown in FIG. 4.

In one embodiment, the resistive and capacitive elements of the circuit of FIG. 4 were given the following values. (Resistor R1 and capacitors Cl and C2 are external to the integrated circuit version of FIG. 4.)

R1 5.2KR11 IBK R21 5.2K R31 2.6K R2 5.2K R12 2.6K R22 5K R32 3.9K R3 5K R13 3.5K R23 5K R33 650 R4 5K R14 2.6K R24 3l0 R34 650 R5 3l0 R15 2K R25 3l0 R35 285 R6 310 R16 880 R26 190 R36 1K R7 5.2KR17 11.7K R27 I90 R37 6.6K R8 I90 R18 2.6K R28 360 C1 0.lyf R9 I90 R19 880 R29 1.3K (Bypasslt RF frequency) R10 390 R20 5.2K R30 8K C2 0.1 4

(Bypass at RF frequency) The transistors and diodes in this circuit are formed on a single wafer of silicon, using well-known planar double diffusion techniques. The resistors are also formed in the silicon wafer using planar techniques. One such technique is described in copending patent application Ser. No. 717,757, filed by Harold S. Crafts, entitled "Planar Epitaxial Resistors" and assigned to Fairchild Camera and Instrument Corp., the assignee of this application. Alternatively, these resistors can be deposited on insulation overlying the surface of the wafer. Diodes D1 and D2 are formed from base-collector junctions while zener diode D3 is formed from a base-emitter junction on this wafer.

A typical AGC stage constructed from discrete components in accordance with this invention had a voltage gain of 72 db at 500 KHz. This gain dropped to 46 db at 30 MHz. Harmonic distortion was found to be at least 30 db down from the fundamental over a wide range of frequencies varying from 500 KHz to l0 MHz. Intermodulation between two equal amplitude input signals separated by 50 KHz at center frequencies of 500 KHZ and 30 MHz was down at least 50 db from each input signal. And the AGC control voltage range was db.

Other embodiments of this invention, such as amplifiers using a plurality of AGC stages constructed according to the principles of this invention, will be obvious in view of this disclosure. In addition, control of the gain of each AGC stage independently of the gain of the other AGC stages is possible.

What is claimed is:

1. An automatic gain control circuit comprising:

means for amplifying an input signal to produce a first output signal;

means for comparing said first output signal to a reference signal and for producing a difference signal proportional to the difference between said first output signal and said reference signal; and

first and second current sources, the amplitudes of the currents drawn by said sources being controlled by said difference signal, said first and second current sources being coupled to said means for amplifying so that the currents from said first and second current sources control the gain of said means for amplifying such that said difference signal is driven to approximately zero amplitude;

said means for amplifying comprising:

a differential amplifier, the bias current through said differential amplifier being the current drawn by said first current source;

a first pair of semiconductor devices selectively coupled to said differential amplifier and biased by the current drawn by said first current source, the current through the first device in said first pair increasing in response to a positive input signal to said differential amplifier while the current through the second device in said first pair decreases an equal amount in response to said positive input signal; and

a second pair of semiconductor devices, each device in said second pair being selectively coupled to a corresponding device in said first pair of devices so that when the current through a selected one of said first pair of devices changes in one direction, the current through the corresponding device in said second pair of devices changes in the opposite direction in such a manner that the output signal comprises:

a first transistor the base of which serves as the first input lead to said differential amplifier, the emitter of which is connected through a first load resistor to said first current source, and the collector of which is connected to said first device in said first pair of semiconductor devices;

a second transistor, the base of which serves as a second input lead to said differential amplifier, the emitter of which is connected through a second load resistor to said first current source, and the collector of which is connected to said second device in said first pair of semiconductor devices;

said first and second transistors being connected in such a manner that a positive input voltage on said first input lead relative to said second input lead increases the current drawn through the first transistor and simultaneously decreases by an equal amount the current drawn through the second transistor, thereby changing in the same manner the current drawn through the corresponding devices in said first pair of semiconductor devices.

3. Structure as in claim 2 in which said first pair of semiconductor devices comprises:

a third transistor the emitter of which is connected to the collector of the first transistor in said difierential amplifier, the base of which is connected to a first supply voltage and the collector of which is connected to a second supply voltage; and

a fourth transistor, the emitter of which is connected to the collector of the second transistor in said differential amplifier, the base of which is connected to said first supply voltage and the collector of which is connected to said second supply voltage;

said third and fourth transistors being connected to said first and second transistors in said differential amplifier in such a manner that an increase in the collector current drawn by said first transistor and a corresponding decrease in the collector current drawn by said second transistor results in a corresponding emitter current increase in said third transistor and a corresponding emitter current decrease in said fourth transistor.

4. Structure as in claim 3, in which said second pair of semiconductor devices comprises:

a fifth transistor the emitter of which is connected to said second current source, the base of which is connected to the emitter of said fourth transistor in said first pair of semiconductor devices and the collector of which is connected both to said second voltage source and to a first output lead from said automatic gain control circuit; and

a sixth transistor the emitter of which is also connected to said second current source, the base of which is connected to the emitter of said third transistor, and the collector of which is connected both to a selected voltage source through a load resistor and to a second output lead from said automatic gain control circuit.

5. Structure as in claim 4 in which the collector of said fifth transistor is connected to said second voltage source through a load resistor.

6. An amplifier circuit comprising:

a first current source drawing the current l,;

a second current source drawing the current I,;

a differential amplifier connected to said first current source so that the bias current through said differential amplifier equals the current I, drawn by said first current source, said differential amplifier comprising first and second amplifying means connected to the input leads to said amplifier circuit in such a manner that a voltage of one polarity across said input leads causes the current through said first and second amplifying means to change equally in opposite directions;

a first pair of semiconductor devices, the first and second devices in said first pair being coupled to said first and second amplifying means respectively and drawing the bias current I said first and second devices in said first pair comprising diodes;

a second pair of semiconductor devices, the first and second devices in said second pair each being selectively coupled to a corresponding one of the devices in said first pair so that a current change in a device in the first pair results in a linearly related current change not necessarily of the same amplitude in the corresponding coupled device in said second pair such that the changes in currents through the devices in said second pair are linearly related to the voltage across the input leads to said first and second amplifying means, said second pair of devices being connected to said second current source and drawing the total bias current I,

7. Structure as in claim 6 in which said first and second devices in said first pair comprise first and second transistors connected as diodes.

8. Structure as in claim 7 in which said first and second devices in said second pair of semiconductor devices are third and fourth transistors.

9. An N stage amplifier, where N is a selected positive integer, wherein each stage comprises:

a first pair of semiconductor devices;

a differential amplifier selectively coupled to said first pair of semiconductor devices for passing an input signal to said first pair of devices,

a second pair of semiconductor devices, each device in said second pair being connected to a corresponding device in said first pair so that the effect on a signal of nonlinearities in said two connected devices cancel out;

a first current source for biasing said differential amplifier and said first pair of devices;

a second current source for biasing said second pair of devices; and

means for varying the currents produced by said first and second sources thereby to vary the gain of said stage.

10. An automatic gain control circuit comprising:

current source means for drawing a first current 1,;

current source means for drawing a second current I a difl'erential amplifier, the bias current through said differential amplifier being 1 a first pair of semiconductor devices directly coupled to said differential amplifier and biased by the current I the current through the first device in said first pair increasing in response to a positive input signal to said differential amplifier while the current through the second device in said first pair decreases an equal amount in response to said positive input signal;

a second pair of semiconductor devices biased by the current l,, each device in said second pair being directly coupled to a corresponding device in said first pair such that a current of l in one of said second pair of semiconductor devices is related to a current change I in a first pair of semiconductor devices by the equation l ll, l,ll,;

said differential amplifier comprising:

a first transistor the base of which serves as the first input lead to said differential amplifier, the emitter of which is connected through a first load resistor R3 to said means for drawing a first current, and the collector of which is connected to said first device of said first pair of semiconductor devices; and

a second transistor, the base of which serves as a second input lead to said differential amplifier, the emitter of which is connected through a second load resistor R4 to said means for drawing a first current, and the collector of which is connected to said second device in said first pair of semiconductor devices; and

wherein said current change I in a device in said second pair of semiconductor devices is related to the input voltage V to said differential amplifier by the equation

Claims

1. An automatic gain control circuit comprising: means for amplifying an input signal to produce a first output signal; means for comparing said first output signal to a reference signal and for producing a difference signal proportional to the difference between said first output signal and said reference signal; and first and second current sources, the amplitudes of the currents drawn by said sources being controlled by said difference signal, said first and second current sources being coupled to said means for amplifying so that the currents from said first and second current sources control the gain of said means for amplifying such that said difference signal is driven to approximately zero amplitude; said means for amplifying comprising: a differential amplifier, the bias current through said differential amplifier being the current drawn by said first current source; a first pair of semiconductor devices selectively coupled to said differential amplifier and biased by the current drawn by said first current source, the current through the first device in said first pair increasing in response to a positive input signal to said differential amplifier while the current through the second device in said first pair decreases an equal amount in response to said positive input signal; and a second pair of semiconductor devices, each device in said second pair being selectively coupled to a corresponding device in said first pair of devices so that when the current through a selected one of said first pair of devices changes in one direction, the current through the corresponding device in said second pair of devices changes in the opposite direction in such a manner that the output signal from said second pair of devices is linearly related to the input signal to said differential amplifier, the bias current through said second pair of devices being the current drawn by said second current source.

2. Structure as in claim 1 in which said differential amplifier comprises: a first transistor the base of which serves as the first input lead to said differential amplifier, the emitter of which is connected through a first load resistor to said first current source, and the collector of which is connected to said first device in said first pair of semiconductor devices; a second transistor, the base of which serves as a second input lead to said differential amplifier, the emitter of which is connected through a second load resistor to said first current source, and the collector of which is connected to said second device in said first pair of semiconductor devices; said first and second transistors being connected in such a manner that a positive input voltage on said first input lead relative to said second input lead increases the current drawn through the first transistor and simultaneously decreases by aN equal amount the current drawn through the second transistor, thereby changing in the same manner the current drawn through the corresponding devices in said first pair of semiconductor devices.

3. Structure as in claim 2 in which said first pair of semiconductor devices comprises: a third transistor the emitter of which is connected to the collector of the first transistor in said differential amplifier, the base of which is connected to a first supply voltage and the collector of which is connected to a second supply voltage; and a fourth transistor, the emitter of which is connected to the collector of the second transistor in said differential amplifier, the base of which is connected to said first supply voltage and the collector of which is connected to said second supply voltage; said third and fourth transistors being connected to said first and second transistors in said differential amplifier in such a manner that an increase in the collector current drawn by said first transistor and a corresponding decrease in the collector current drawn by said second transistor results in a corresponding emitter current increase in said third transistor and a corresponding emitter current decrease in said fourth transistor.

4. Structure as in claim 3, in which said second pair of semiconductor devices comprises: a fifth transistor the emitter of which is connected to said second current source, the base of which is connected to the emitter of said fourth transistor in said first pair of semiconductor devices and the collector of which is connected both to said second voltage source and to a first output lead from said automatic gain control circuit; and a sixth transistor the emitter of which is also connected to said second current source, the base of which is connected to the emitter of said third transistor, and the collector of which is connected both to a selected voltage source through a load resistor and to a second output lead from said automatic gain control circuit.

6. An amplifier circuit comprising: a first current source drawing the current I1; a second current source drawing the current I2; a differential amplifier connected to said first current source so that the bias current through said differential amplifier equals the current I1 drawn by said first current source, said differential amplifier comprising first and second amplifying means connected to the input leads to said amplifier circuit in such a manner that a voltage of one polarity across said input leads causes the current through said first and second amplifying means to change equally in opposite directions; a first pair of semiconductor devices, the first and second devices in said first pair being coupled to said first and second amplifying means respectively and drawing the bias current I1, said first and second devices in said first pair comprising diodes; a second pair of semiconductor devices, the first and second devices in said second pair each being selectively coupled to a corresponding one of the devices in said first pair so that a current change in a device in the first pair results in a linearly related current change not necessarily of the same amplitude in the corresponding coupled device in said second pair such that the changes in currents through the devices in said second pair are linearly related to the voltage across the input leads to said first and second amplifying means, said second pair of devices being connected to said second current source and drawing the total bias current I2.

9. An N stage amplifier, where N is a selected positive integer, wherein each stage comprises: a first pair of semiconductor devices; a differential amplifier selectively coupled to said first pair of semiconductor devices for passing an input signal to said first pair of devices, a second pair of semiconductor devices, each device in said second pair being connected to a corresponding device in said first pair so that the effect on a signal of nonlinearities in said two connected devices cancel out; a first current source for biasing said differential amplifier and said first pair of devices; a second current source for biasing said second pair of devices; and means for varying the currents produced by said first and second sources thereby to vary the gain of said stage.

10. An automatic gain control circuit comprising: current source means for drawing a first current I1; current source means for drawing a second current I2; a differential amplifier, the bias current through said differential amplifier being I1, a first pair of semiconductor devices directly coupled to said differential amplifier and biased by the current I1, the current through the first device in said first pair increasing in response to a positive input signal to said differential amplifier while the current through the second device in said first pair decreases an equal amount in response to said positive input signal; a second pair of semiconductor devices biased by the current I2, each device in said second pair being directly coupled to a corresponding device in said first pair such that a current of Is2in one of said second pair of semiconductor devices is related to a current change Is1 in a first pair of semiconductor devices by the equation Is1/Is2 I1/I2; said differential amplifier comprising: a first transistor the base of which serves as the first input lead to said differential amplifier, the emitter of which is connected through a first load resistor R3 to said means for drawing a first current, and the collector of which is connected to said first device of said first pair of semiconductor devices; and a second transistor, the base of which serves as a second input lead to said differential amplifier, the emitter of which is connected through a second load resistor R4 to said means for drawing a first current, and the collector of which is connected to said second device in said first pair of semiconductor devices; and wherein said current change Is2 in a device in said second pair of semiconductor devices is related to the input voltage Vin to said differential amplifier by the equation Is2/Vin I2/I1 (R3+R4).