US20220199842A1 - Solar cell emitter region fabrication using self-aligned implant and cap - Google Patents
Solar cell emitter region fabrication using self-aligned implant and cap Download PDFInfo
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- US20220199842A1 US20220199842A1 US17/693,054 US202217693054A US2022199842A1 US 20220199842 A1 US20220199842 A1 US 20220199842A1 US 202217693054 A US202217693054 A US 202217693054A US 2022199842 A1 US2022199842 A1 US 2022199842A1
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- solar cell
- layer
- capping layer
- silicon layer
- polycrystalline silicon
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- 239000007943 implant Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 70
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000002019 doping agent Substances 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 230000008569 process Effects 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 10
- 239000010955 niobium Substances 0.000 claims description 10
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 229910052735 hafnium Inorganic materials 0.000 claims description 5
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 5
- 238000007654 immersion Methods 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052758 niobium Inorganic materials 0.000 claims description 5
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 5
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 49
- 229910052710 silicon Inorganic materials 0.000 abstract description 49
- 239000010703 silicon Substances 0.000 abstract description 49
- 238000000137 annealing Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 112
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 125000004429 atom Chemical group 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000013459 approach Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910002804 graphite Inorganic materials 0.000 description 4
- 239000010439 graphite Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- -1 SiON Inorganic materials 0.000 description 3
- 238000000637 aluminium metallisation Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 208000029278 non-syndromic brachydactyly of fingers Diseases 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000001994 activation Methods 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022433—Particular geometry of the grid contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
-
- H—ELECTRICITY
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
- H01L31/03682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic System
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- H—ELECTRICITY
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1876—Particular processes or apparatus for batch treatment of the devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- Embodiments of the present disclosure are in the field of renewable energy and, in particular, methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells.
- Photovoltaic cells are well known devices for direct conversion of solar radiation into electrical energy.
- solar cells are fabricated on a semiconductor wafer or substrate using semiconductor processing techniques to form a p-n junction near a surface of the substrate.
- Solar radiation impinging on the surface of, and entering into, the substrate creates electron and hole pairs in the bulk of the substrate.
- the electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby generating a voltage differential between the doped regions.
- the doped regions are connected to conductive regions on the solar cell to direct an electrical current from the cell to an external circuit coupled thereto.
- Efficiency is an important characteristic of a solar cell as it is directly related to the capability of the solar cell to generate power. Likewise, efficiency in producing solar cells is directly related to the cost effectiveness of such solar cells. Accordingly, techniques for increasing the efficiency of solar cells, or techniques for increasing the efficiency in the manufacture of solar cells, are generally desirable. Some embodiments of the present disclosure allow for increased solar cell manufacture efficiency by providing novel processes for fabricating solar cell structures. Some embodiments of the present disclosure allow for increased solar cell efficiency by providing novel solar cell structures.
- FIGS. 1A-1F illustrate cross-sectional views of various stages in the fabrication of a solar cell, in accordance with an embodiment of the present disclosure.
- FIG. 2 is a flowchart listing operations in a method of fabricating a solar cell as corresponding to FIGS. 1A-1F , in accordance with an embodiment of the present disclosure.
- FIG. 3 is a flowchart listing operations in another method of fabricating a solar cell, in accordance with an embodiment of the present disclosure.
- FIG. 4 illustrates a plan of a back surface of an aluminum metallization back contact solar cell, in accordance with an embodiment of the present disclosure.
- FIG. 5A schematically illustrates a cross-sectional view of an inline platform for patterned implant and capping, in accordance with an embodiment of the present disclosure.
- FIG. 5B illustrates an implant and capping sequence through silicon contact masks in the apparatus of FIG. 5A , in accordance with an embodiment of the present disclosure.
- FIG. 6A schematically illustrates a cross-sectional view of an inline platform for patterned implant involving traveling wafer and stationary shadow mask, in accordance with an embodiment of the present disclosure.
- FIG. 6B illustrates an implant sequence through graphite proximity masks in the apparatus of FIG. 6A , in accordance with an embodiment of the present disclosure.
- FIG. 7A illustrates a plan view of the back side of an interdigitated back contact (IBC) solar cell having an adjacent “Short Finger” multibusbar layout, in accordance with an embodiment of the present disclosure.
- IBC interdigitated back contact
- FIG. 7B illustrates a plan view of the back side of an IBC solar cell having a metal foil backplane of copper (Cu) or aluminum (Al), in accordance with an embodiment of the present disclosure.
- FIG. 7C illustrates a plan view of the back side of an IBC solar cell having multiple contact points attached with solder, a conductive adhesive or by laser spot welding (e.g., Al to Al), in accordance with an embodiment of the present disclosure.
- first “First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, reference to a “first” solar cell does not necessarily imply that this solar cell is the first solar cell in a sequence; instead the term “first” is used to differentiate this solar cell from another solar cell (e.g., a “second” solar cell).
- Coupled means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.
- a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. The method also involves implanting, through a stencil mask, dopant impurity atoms in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. The method also involves forming, through the stencil mask, a capping layer on and substantially in alignment with the implanted regions of the silicon layer. The method also involves removing the non-implanted regions of the silicon layer, wherein the capping layer protects the implanted regions of the silicon layer during the removing. The method also involves annealing the implanted regions of the silicon layer to form doped polycrystalline silicon emitter regions.
- a method of fabricating alternating N-type and P-type emitter regions of a solar cell involves forming a polycrystalline silicon layer on a thin oxide layer disposed on a monocrystalline silicon substrate. The method also involves implanting, through a first stencil mask, dopant impurity atoms of a first conductivity type in the polycrystalline silicon layer to form first implanted regions of the polycrystalline silicon layer adjacent to non-implanted regions. The method also involves forming, through the first stencil mask, a first capping layer on and substantially in alignment with the first implanted regions of the polycrystalline silicon layer.
- the method also involves implanting, through a second stencil mask, dopant impurity atoms of a second, opposite, conductivity type in portions of the non-implanted regions of the polycrystalline silicon layer to form second implanted regions of the polycrystalline silicon layer and resulting in remaining non-implanted regions.
- the method also involves forming, through the second stencil mask, a second capping layer on and substantially in alignment with the second implanted regions of the polycrystalline silicon layer.
- the method also involves removing the remaining non-implanted regions of the polycrystalline silicon layer, wherein the first and second capping layers protect the first implanted regions and the second implanted regions, respectively, of the polycrystalline silicon layer during the removing.
- the method also involves annealing the first implanted regions and the second implanted regions of the polycrystalline silicon layer to form doped polycrystalline silicon emitter regions.
- an in-line process apparatus for fabricating an emitter region of a solar cell includes a first station for aligning a stencil mask with a substrate.
- a second station is included for implanting dopant impurity atoms above the substrate, through the stencil mask.
- a third station is included for forming a capping layer above the substrate, through the stencil mask. The stencil mask and the substrate can be moved together through the second and third stations.
- One or more embodiments described herein provides a simplified process flow for fabricating high efficiency, all back-contact solar cell devices involving the use of ion implant technology for generating both N+(e.g., typically phosphorus or arsenic doped) and P+(e.g., typically boron doped) polysilicon emitter layers.
- a fabrication approach involves the use of patterned shadow masks, preferably fabricated from silicon (Si), placed in close proximity or direct physical contact with the solar cell substrate being processed.
- the shadow mask moves with the substrate, first under an implant beam, and next (without moving the shadow mask) through a second processing zone/region where a sufficient thickness of a capping layer is deposited directly over and perfectly (or at least substantially) aligned with the implanted area.
- a same or similar process can then be applied to generate similarly capped patterns of a dopant type having opposite conductivity.
- the capping layer may consist of a SiO 2 or SiN (or a combination thereof) dielectric based-films, deposited using low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD).
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- HDPCVD high density plasma chemical vapor deposition
- HDPCVD may be preferred due to the more directional nature of the deposition and lower operating pressures more compatible with the preceding ion implant operation.
- the capping layer may also be deposited using an even higher vacuum physical vapor deposition (PVD) or sputtering based process permitting a more directional, collimated deposition of SiO 2 , SiON, or SiN based dielectric capping layers that provide good wet etch selectivity even when applied at relatively low temperatures (such as between room temperature and 400 C).
- PVD physical vapor deposition
- sputtering based process permitting a more directional, collimated deposition of SiO 2 , SiON, or SiN based dielectric capping layers that provide good wet etch selectivity even when applied at relatively low temperatures (such as between room temperature and 400 C).
- the as-deposited capping layer is sufficiently resistant to alkaline-based silicon etch and texturing chemistries to allow for complete removal of all non-implanted (and therefore also non-capped) polysilicon regions.
- the alkaline-based silicon etch and texturing chemistries are thus used to form trenches that isolate oppositely doped poly-Si regions, with the simultaneous texturing of the front (sun-facing) side of the wafer.
- a subsequent wet etch chemistry such as a hydrofluoric acid (HF) based chemistry (e.g., an NH 4 F buffered HF mixture, or buffered oxide etchant (BOE)) is applied to strip the residual capping layer.
- HF hydrofluoric acid
- BOE buffered oxide etchant
- the capping layer is a metallic layer with sufficient resistance to an alkaline chemistry. Such a metallic layer may remain in the device as a contact layer.
- one or more embodiments described herein provides such functionality by employing relatively low cost, non-contaminating silicon wafer stencil masks for applying both patterned ion implants and self-aligned capping layers in a single sequence through the same mask.
- the mask like the silicon wafer substrate, is composed of silicon it can be employed in contact mode without contamination issues or problems associated with different coefficients of thermal expansion.
- masking or stencil wafers can be sufficiently doped so as to be conducting and therefore be included as an integral part of the ion beam shaping electronics (or merely to avoid charging).
- subsequent implants can be blocked (e.g., stopped and trapped in) the surface dielectric, greatly facilitating the periodic cleaning and reuse of such stencil masks.
- FIGS. 1A-1F illustrate cross-sectional views of various stages in the fabrication of a solar cell, in accordance with an embodiment of the present disclosure.
- FIG. 2 is a flowchart 200 listing operations in a method of fabricating a solar cell as corresponding to FIGS. 1A-1F , in accordance with an embodiment of the present disclosure.
- a method of fabricating alternating N-type and P-type emitter regions of a solar cell involves forming a polycrystalline silicon layer 106 on a thin oxide layer 104 disposed on a substrate 102 .
- the substrate 102 is a monocrystalline silicon substrate, such as a bulk single crystalline N-type doped silicon substrate. It is to be understood, however, that substrate 102 may be a layer, such as a multi-crystalline silicon layer, disposed on a global solar cell substrate.
- the thin oxide layer is a tunnel dielectric silicon oxide layer having a thickness of approximately 2 nanometers or less. Although described as a polycrystalline silicon layer 106 , in an alternative embodiment, an amorphous silicon layer is used instead.
- the method also involves implanting, through a first stencil mask 108 , dopant impurity atoms of a first conductivity type 110 in the polycrystalline silicon layer 106 to form first implanted regions 112 of the polycrystalline silicon layer 106 and non-implanted regions (i.e., remaining portions of polycrystalline silicon layer 106 that have not been implanted at this stage in the process).
- the first stencil mask 108 is a silicon stencil mask.
- use of a silicon stencil mask enables placement on, or in close proximity to, the structure of FIG. 1A since the silicon of the stencil mask does not contaminate a silicon based solar cell.
- the implanting is performed by using ion beam implantation or plasma immersion implantation. In one embodiment, this first implanting provides P+ dopant atoms for silicon (e.g., boron atoms). In another embodiment, however, the first implanting provides N+ dopant atoms for silicon (e.g., phosphorus atoms or arsenic atoms).
- the conditions used to perform the implantation are tuned (e.g., by sequential or simultaneous electron bombardment) to enhance subsequent etch selectivity between implanted and non-implanted regions, as pertaining to later operations described below.
- Other conditions that may be tuned can include one or more of substrate biasing during implantation, temperature tuning, and dose tuning.
- the method also involves forming, through the first stencil mask 108 , a first capping layer 114 on and substantially in alignment with the first implanted regions 112 of the polycrystalline silicon layer 106 .
- the alignment can be viewed as ideally perfect since the stencil mask and substrate travel together. However, the process can tolerate some slight offset (e.g., less than a few percent in a translational direction) that may occur while the process is moved from an implant/doping chamber to a cap deposition chamber.
- the implanting and the forming of the first capping layer 114 are performed in an in-line process apparatus in which the first stencil mask 108 and the monocrystalline silicon substrate 102 are moved together through the in-line process apparatus, as described in greater detail in association with FIGS. 5A and 5B .
- the first capping layer 114 includes a material such as, but not limited to, silicon dioxide (SiO 2 ), silicon nitride (SiN) or silicon oxynitride (SiON).
- the first capping layer 114 is formed using a deposition technique such as, but not limited to, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD) or physical vapor deposition (PVD).
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- HDPCVD high density plasma chemical vapor deposition
- PVD physical vapor deposition
- the first capping layer 114 is formed by deposition at a temperature approximately in the range of 25-400 degrees Celsius.
- the material of capping layer 114 may also be deposited on the first stencil mask 108 .
- the material of capping layer 114 may also be deposited on the first stencil mask 108 .
- multiple material layers may ultimately accumulate, as is depicted in FIG. 1B .
- an optimal number of runs may be determined to balance throughput against an over-accumulation of material on the stencil mask 108 that could in some way impact later deposition processes.
- the accumulated capping material is removed by selective etching, and the first stencil mask 108 can then be reused.
- the method also involves implanting, through a second stencil mask 116 , dopant impurity atoms of a second, opposite, conductivity type 118 in portions of the non-implanted regions of the polycrystalline silicon layer 106 to form second implanted regions 120 of the polycrystalline silicon layer 106 and remaining non-implanted regions (i.e., remaining portions of polycrystalline silicon layer 106 that have not been implanted).
- the second stencil mask 116 is a silicon stencil mask.
- use of a silicon stencil mask enables placement on, or in close proximity to, the structure of FIG. 1B since the silicon of the stencil mask does not contaminate a silicon based solar cell.
- the implanting is performed by using ion beam implantation or plasma immersion implantation.
- this second implanting provides N+ dopant atoms for silicon (e.g., phosphorus atoms or arsenic atoms).
- the second implanting provides P+ dopant atoms for silicon (e.g., boron atoms).
- the conditions used to perform the implantation are tuned (e.g., by sequential or simultaneous electron bombardment) to enhance subsequent etch selectivity between implanted and non-implanted regions, as pertaining to later operations described below.
- Other conditions that may be tuned can include one or more of substrate biasing during implantation, temperature tuning, and dose tuning.
- the method also involves forming, through the second stencil mask 116 , a second capping layer 122 on and substantially in alignment with the second implanted regions 120 of the polycrystalline silicon layer 106 .
- the alignment can be viewed as ideally perfect since the stencil mask and substrate travel together. However, the process can tolerate some slight offset (e.g., less than a few percent in a translational direction) that may occur while the process is moved from an implant/doping chamber to a cap deposition chamber.
- the implanting and the forming of the second capping layer 122 are performed in an in-line process apparatus in which the second stencil mask 116 and the monocrystalline silicon substrate 102 are moved together through the in-line process apparatus, as described in greater detail in association with FIGS. 5A and 5B .
- the second capping layer 122 includes a material such as, but not limited to, silicon dioxide (SiO 2 ), silicon nitride (SiN) or silicon oxynitride (SiON).
- the second capping layer 122 is formed using a deposition technique such as, but not limited to, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD) or physical vapor deposition (PVD).
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- HDPCVD high density plasma chemical vapor deposition
- PVD physical vapor deposition
- the second capping layer 122 is formed by deposition at a temperature approximately in the range of 25-400 degrees Celsius.
- the material of second capping layer 122 may also be deposited on the second stencil mask 116 .
- the material of second capping layer 122 may also be deposited on the second stencil mask 116 .
- multiple material layers may ultimately accumulate, as is depicted in FIG. 1C .
- an optimal number of runs may be determined to balance throughput against an over-accumulation of material on the stencil mask 116 that could in some way impact later deposition processes.
- the accumulated capping material is removed by selective etching, and the second stencil mask 116 is then reused.
- the remaining non-implanted regions of the polycrystalline silicon layer 106 can be removed.
- the first capping layer 114 and the second capping layer 122 protect the first implanted regions 112 and the second implanted regions 120 , respectively, during removal of the remaining non-implanted portions of the polycrystalline silicon layer 106 .
- the capping layers 114 and 122 can also be removed.
- the capping layers 114 and 122 should be suitably less susceptible to the etch than the polycrystalline silicon layer 106 in order to provide at least a substantial amount of protection of the first implanted regions 112 and the second implanted regions 120 (e.g., without significantly eroding the implanted regions).
- the first and second capping layers 114 and 122 include a material such as, but not limited to, silicon dioxide (SiO 2 ), silicon nitride (SiN) or silicon oxynitride (SiON), and removing the remaining non-implanted regions of the polycrystalline silicon layer 106 involves using a hydroxide-based wet etch process.
- the first and second capping layers 114 and 122 are then removed in a subsequent process using an HF-based wet etch process, such as a buffered oxide etchant (BOE) process.
- a buffered oxide etchant BOE
- the first implanted regions 112 and the second implanted regions 120 of the polycrystalline silicon layer can be annealed to form first 124 and second 126 doped polycrystalline silicon emitter regions, respectively. While it may be generally most advantageous to complete the etch (i.e. removal) of non-implanted areas of polysilicon prior to performing a high temperature anneal and activation process, certain implant conditions may result in intrinsically higher reactivity in the texturizing etch (e.g., as relative to non-implanted regions), in which case a high temperature anneal can be performed prior to trench etch.
- the heating is performed at a temperature approximately in the range of 850-1100 degrees Celsius for a duration approximately in the range of 1-100 minutes.
- a light P+ dopant drive is performed during the heating or annealing.
- trenches 128 are formed between the first 124 and second 126 doped polycrystalline silicon emitter regions. Furthermore, in an embodiment, the trenches and/or the light receiving surface 101 of the substrate 102 are texturized. The ordering of operations of the trench formation and the annealing of the first implanted regions 112 and the second implanted regions 120 of the polycrystalline silicon layer to form first 124 and second 126 doped polycrystalline silicon emitter regions can be varied. In one embodiment, the trench formation and the texturizing are both performed in a same hydroxide-based etch process prior to the annealing, e.g., as part of the process used to remove non-implanted regions of the silicon layer 106 .
- the trench formation and the texturizing are performed subsequent to the annealing (as is depicted in FIGS. 1D and 1E ).
- texturizing of surface 101 may be performed in an operation different from the operation used to form and texturize trenches 128 .
- a texturized surface may be one which has a regular or an irregular shaped surface for scattering incoming light, decreasing the amount of light reflected off of the light-receiving surface of the solar cell.
- Additional embodiments can include formation of a passivation or anti-reflective coating layer 129 on the light-receiving surface 101 , as depicted in FIG. 1E .
- conductive contacts 130 and 132 are fabricated to contact the first 124 and second 126 doped polycrystalline silicon emitter regions, respectively.
- the contacts are fabricated by first depositing and patterning an insulating layer 150 to have openings and then forming one or more conductive layers in the openings.
- the conductive contacts 130 and 132 include metal and are formed by a deposition, lithographic, and etch approach or, alternatively, a printing process.
- the capping layers 114 and 122 (or at least remnants thereof) are retained in the final structure.
- the contacts 130 and 132 are formed through the capping layers 114 and 122 , e.g., by patterning the capping layers during the contact trench formation.
- one or both of the capping layers 114 and 122 include a refractory metal such as, but not limited to, titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), molybdenum (Mo) or tungsten (W).
- Such a refractory metal can be deposited onto a polycrystalline silicon surface and withstand an anneal process used to activate dopants in the polycrystalline silicon layer.
- a thin metal capping layer is used and includes a material such as, but not limited to, titanium (Ti), cobalt (Co) or nickel (Ni).
- the thin metal capping layer can be used to undergo silicidation with an upper portion of the polycrystalline layer.
- the conductive contacts 130 and 132 are formed to include the conductive capping layers.
- one or both of the capping layers 114 and 122 include a surface carbosilane based film having a thickness between 50 and 1000 A and deposited using chemical vapor deposition techniques employing volatile carbosilane precursors. Such a layer can be removed or patterned prior to conductive contact formation.
- FIG. 3 is a flowchart 300 listing operations in another method of fabricating a solar cell, in accordance with an embodiment of the present disclosure.
- a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate.
- dopant impurity atoms are implanted in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions.
- a capping layer is formed on and substantially in alignment with the implanted regions of the silicon layer.
- the non-implanted regions of the silicon layer are removed. The capping layer protects the implanted regions of the silicon layer during the removing.
- the implanted regions of the silicon layer are annealed to form doped polycrystalline silicon emitter regions.
- FIG. 4 illustrates a plan of a back surface of an aluminum metallization back contact solar cell 400 , in accordance with an embodiment of the present disclosure.
- FIG. 5A schematically illustrates a cross-sectional view of an inline platform for patterned implant and capping, in accordance with an embodiment of the present disclosure.
- FIG. 5B illustrates an implant and capping sequence through silicon contact masks in the apparatus of FIG. 5A , in accordance with an embodiment of the present disclosure.
- an in-line process apparatus 500 for fabricating an emitter region of a solar cell includes a first station 502 for aligning a stencil mask 504 with a substrate 506 .
- a second station 508 is included for implanting dopant impurity atoms (e.g., boron or phosphorus) above the substrate 506 , through the stencil mask 504 .
- a third station 510 is included for forming a capping layer above the substrate 506 , through the stencil mask 504 .
- Other aspects of the in-line process apparatus 500 can include a wafer input area 512 and a mask removal and wafer output area 514 .
- the stencil mask 504 and the substrate 506 are moved together at least through the second 508 and third 510 stations.
- the direction of wafer flow through the in-line process apparatus 500 is shown by arrows 550 .
- the in-line process apparatus 500 enables implant and capping or regions of a silicon layer 507 on the substrate 506 through the stencil mask 504 .
- the implanted regions 507 A and the capping layer 509 are self-aligned since the capping layer is formed using the same mask in the same position as is used to perform the implanting.
- the first station 502 is for aligning the stencil mask 504 as in contact with on or in close proximity to the substrate 506 .
- the second station 508 includes an ion-implantation or plasma immersion implantation chamber.
- the third station 510 includes a deposition chamber such as, but not limited to, a low pressure chemical vapor deposition (LPCVD), a plasma enhanced chemical vapor deposition (PECVD) chamber, a high density plasma chemical vapor deposition (HDPCVD) chamber, or a physical vapor deposition (PVD) chamber.
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- HDPCVD high density plasma chemical vapor deposition
- PVD physical vapor deposition
- FIG. 6A schematically illustrates a cross-sectional view of an inline platform for patterned implant involving traveling wafer and stationary shadow mask, in accordance with an embodiment of the present disclosure.
- FIG. 6B illustrates an implant sequence through graphite proximity masks in the apparatus of FIG. 6A , in accordance with an embodiment of the present disclosure.
- an inline platform 600 includes a wafer input region 602 , an implant source 604 (e.g., ion implantation or plasma immersion), and an output region 606 .
- a stationary stencil mask 608 such as a stationary graphite mask, is held in proximity to, but not in contact with, a substrate 610 to provide an implanted substrate 612 .
- FIG. 7A illustrates a plan view of the back side of an IBC solar cell 700 A having an adjacent “Short Finger” multibusbar layout, in accordance with an embodiment of the present disclosure.
- FIG. 7B illustrates a plan view of the back side of an IBC solar cell 700 B having a metal foil backplane of copper (Cu) or aluminum (Al), in accordance with an embodiment of the present disclosure.
- FIG. 7C illustrates a plan view of the back side of an IBC solar cell 700 C having multiple contact points 750 attached with solder, a conductive adhesive or by laser spot welding (e.g., Al to Al), in accordance with an embodiment of the present disclosure.
- embodiments described herein may be implemented to provide lower cost, high throughput ion implant platforms for the fabrication of high efficiency IBC-type solar cells.
- Specific embodiments can offer an advantageous approach for generating self-aligned implants and capping layers through a single Si contact stencil mask.
- the combination of Si stencil masks with a process that automatically applies a dielectric capping film can address many of the cost, contamination, lifetime, and cleaning/reuse issues generally limiting the application of implant technology to solar cell fabrication.
- the deposition of a capping film without breaking vacuum can reduce the degradation of implanted regions by air oxidation.
- Embodiments may be particularly useful for the fabrication of solar cells that incorporate polycrystalline silicon or amorphous silicon (e.g., a-Si:H) derived emitters.
Abstract
Description
- This application is a Divisional of U.S. patent application Ser. No. 15/436,239, filed on Feb. 17, 2017, which is a Continuation of U.S. patent application Ser. No. 14/100,540, filed on Dec. 9, 2013, now U.S. Pat. No. 9,577,134 issued on Feb. 21, 2017, the entire contents of which are hereby incorporated by reference herein.
- Embodiments of the present disclosure are in the field of renewable energy and, in particular, methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells.
- Photovoltaic cells, commonly known as solar cells, are well known devices for direct conversion of solar radiation into electrical energy. Generally, solar cells are fabricated on a semiconductor wafer or substrate using semiconductor processing techniques to form a p-n junction near a surface of the substrate. Solar radiation impinging on the surface of, and entering into, the substrate creates electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby generating a voltage differential between the doped regions. The doped regions are connected to conductive regions on the solar cell to direct an electrical current from the cell to an external circuit coupled thereto.
- Efficiency is an important characteristic of a solar cell as it is directly related to the capability of the solar cell to generate power. Likewise, efficiency in producing solar cells is directly related to the cost effectiveness of such solar cells. Accordingly, techniques for increasing the efficiency of solar cells, or techniques for increasing the efficiency in the manufacture of solar cells, are generally desirable. Some embodiments of the present disclosure allow for increased solar cell manufacture efficiency by providing novel processes for fabricating solar cell structures. Some embodiments of the present disclosure allow for increased solar cell efficiency by providing novel solar cell structures.
-
FIGS. 1A-1F illustrate cross-sectional views of various stages in the fabrication of a solar cell, in accordance with an embodiment of the present disclosure. -
FIG. 2 is a flowchart listing operations in a method of fabricating a solar cell as corresponding toFIGS. 1A-1F , in accordance with an embodiment of the present disclosure. -
FIG. 3 is a flowchart listing operations in another method of fabricating a solar cell, in accordance with an embodiment of the present disclosure. -
FIG. 4 illustrates a plan of a back surface of an aluminum metallization back contact solar cell, in accordance with an embodiment of the present disclosure. -
FIG. 5A schematically illustrates a cross-sectional view of an inline platform for patterned implant and capping, in accordance with an embodiment of the present disclosure. -
FIG. 5B illustrates an implant and capping sequence through silicon contact masks in the apparatus ofFIG. 5A , in accordance with an embodiment of the present disclosure. -
FIG. 6A schematically illustrates a cross-sectional view of an inline platform for patterned implant involving traveling wafer and stationary shadow mask, in accordance with an embodiment of the present disclosure. -
FIG. 6B illustrates an implant sequence through graphite proximity masks in the apparatus ofFIG. 6A , in accordance with an embodiment of the present disclosure. -
FIG. 7A illustrates a plan view of the back side of an interdigitated back contact (IBC) solar cell having an adjacent “Short Finger” multibusbar layout, in accordance with an embodiment of the present disclosure. -
FIG. 7B illustrates a plan view of the back side of an IBC solar cell having a metal foil backplane of copper (Cu) or aluminum (Al), in accordance with an embodiment of the present disclosure. -
FIG. 7C illustrates a plan view of the back side of an IBC solar cell having multiple contact points attached with solder, a conductive adhesive or by laser spot welding (e.g., Al to Al), in accordance with an embodiment of the present disclosure. - The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
- This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.
- Terminology. The following paragraphs provide definitions and/or context for terms found in this disclosure (including the appended claims):
- “Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps.
- “Configured To.” Various units or components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units/components include structure that performs those task or tasks during operation. As such, the unit/component can be said to be configured to perform the task even when the specified unit/component is not currently operational (e.g., is not on/active). Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, sixth paragraph, for that unit/component.
- “First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, reference to a “first” solar cell does not necessarily imply that this solar cell is the first solar cell in a sequence; instead the term “first” is used to differentiate this solar cell from another solar cell (e.g., a “second” solar cell).
- “Coupled”—The following description refers to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.
- In addition, certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, “side”, “outboard”, and “inboard” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
- Methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells, are described herein. In the following description, numerous specific details are set forth, such as specific process flow operations, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known fabrication techniques, such as lithography and patterning techniques, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
- Disclosed herein are methods of fabricating solar cells. In one embodiment, a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. The method also involves implanting, through a stencil mask, dopant impurity atoms in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. The method also involves forming, through the stencil mask, a capping layer on and substantially in alignment with the implanted regions of the silicon layer. The method also involves removing the non-implanted regions of the silicon layer, wherein the capping layer protects the implanted regions of the silicon layer during the removing. The method also involves annealing the implanted regions of the silicon layer to form doped polycrystalline silicon emitter regions.
- In another embodiment, a method of fabricating alternating N-type and P-type emitter regions of a solar cell involves forming a polycrystalline silicon layer on a thin oxide layer disposed on a monocrystalline silicon substrate. The method also involves implanting, through a first stencil mask, dopant impurity atoms of a first conductivity type in the polycrystalline silicon layer to form first implanted regions of the polycrystalline silicon layer adjacent to non-implanted regions. The method also involves forming, through the first stencil mask, a first capping layer on and substantially in alignment with the first implanted regions of the polycrystalline silicon layer. The method also involves implanting, through a second stencil mask, dopant impurity atoms of a second, opposite, conductivity type in portions of the non-implanted regions of the polycrystalline silicon layer to form second implanted regions of the polycrystalline silicon layer and resulting in remaining non-implanted regions. The method also involves forming, through the second stencil mask, a second capping layer on and substantially in alignment with the second implanted regions of the polycrystalline silicon layer. The method also involves removing the remaining non-implanted regions of the polycrystalline silicon layer, wherein the first and second capping layers protect the first implanted regions and the second implanted regions, respectively, of the polycrystalline silicon layer during the removing. The method also involves annealing the first implanted regions and the second implanted regions of the polycrystalline silicon layer to form doped polycrystalline silicon emitter regions.
- Also disclosed herein are apparatuses for fabricating solar cells. In one embodiment, an in-line process apparatus for fabricating an emitter region of a solar cell includes a first station for aligning a stencil mask with a substrate. A second station is included for implanting dopant impurity atoms above the substrate, through the stencil mask. A third station is included for forming a capping layer above the substrate, through the stencil mask. The stencil mask and the substrate can be moved together through the second and third stations.
- One or more embodiments described herein provides a simplified process flow for fabricating high efficiency, all back-contact solar cell devices involving the use of ion implant technology for generating both N+(e.g., typically phosphorus or arsenic doped) and P+(e.g., typically boron doped) polysilicon emitter layers. In one embodiment, a fabrication approach involves the use of patterned shadow masks, preferably fabricated from silicon (Si), placed in close proximity or direct physical contact with the solar cell substrate being processed. In one such embodiment, the shadow mask moves with the substrate, first under an implant beam, and next (without moving the shadow mask) through a second processing zone/region where a sufficient thickness of a capping layer is deposited directly over and perfectly (or at least substantially) aligned with the implanted area. A same or similar process can then be applied to generate similarly capped patterns of a dopant type having opposite conductivity.
- Some embodiments involve the composition of the capping layer as selected such that a selective wet or dry etch removal of adjacent non-implanted (and, therefore, also uncapped) polysilicon layer is enabled. Such etch selectivity permits patterned trench isolation between emitter regions of, e.g., a back contact solar cell. In some examples, the capping film may consist of a SiO2 or SiN (or a combination thereof) dielectric based-films, deposited using low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD). In one embodiment, HDPCVD may be preferred due to the more directional nature of the deposition and lower operating pressures more compatible with the preceding ion implant operation. However, the capping layer may also be deposited using an even higher vacuum physical vapor deposition (PVD) or sputtering based process permitting a more directional, collimated deposition of SiO2, SiON, or SiN based dielectric capping layers that provide good wet etch selectivity even when applied at relatively low temperatures (such as between room temperature and 400 C).
- In particular embodiments, the as-deposited capping layer is sufficiently resistant to alkaline-based silicon etch and texturing chemistries to allow for complete removal of all non-implanted (and therefore also non-capped) polysilicon regions. The alkaline-based silicon etch and texturing chemistries are thus used to form trenches that isolate oppositely doped poly-Si regions, with the simultaneous texturing of the front (sun-facing) side of the wafer. In one embodiment, once the front side texturing and trench isolation etch is complete, a subsequent wet etch chemistry such as a hydrofluoric acid (HF) based chemistry (e.g., an NH4F buffered HF mixture, or buffered oxide etchant (BOE)) is applied to strip the residual capping layer. In an alternative embodiment, however, the capping layer is a metallic layer with sufficient resistance to an alkaline chemistry. Such a metallic layer may remain in the device as a contact layer.
- To provide further context, there has been recent significant interest and progress towards the delivery of lower cost and higher throughput ion implant systems applicable to solar cell fabrication with particular promise to interdigitated back contact (IBC) type solar cells. The assumption is that both N+ and P+ implants could be accomplished with good alignment. However, in order to be applicable to high performance back contact type solar cell structures using a process flow that could actually reduce process steps, costs, and thermal budget, an approach is required that provides not only for cost effectively providing patterned and aligned ion implants but also the selective or self aligned removal of non-implanted polycrystalline silicon regions. Addressing such concerns, one or more embodiments described herein provides such functionality by employing relatively low cost, non-contaminating silicon wafer stencil masks for applying both patterned ion implants and self-aligned capping layers in a single sequence through the same mask. Since the mask, like the silicon wafer substrate, is composed of silicon it can be employed in contact mode without contamination issues or problems associated with different coefficients of thermal expansion. In an embodiment, masking or stencil wafers can be sufficiently doped so as to be conducting and therefore be included as an integral part of the ion beam shaping electronics (or merely to avoid charging). Furthermore, by automatically performing the deposition of a dielectric layer after each ion implant operation, subsequent implants can be blocked (e.g., stopped and trapped in) the surface dielectric, greatly facilitating the periodic cleaning and reuse of such stencil masks.
- More specifically, like other patterning processes requiring the use of stencil masks, generating masks with sufficient mechanical integrity may place significant restrictions on the types of patterns employed, or may require that the desired pattern for each implant polarity be performed in two separate and perfectly aligned steps (e.g., using a total of four separate masks). One such scenario that may be impacted is the fabrication of interdigitation using long fingers extending nearly the length of the solar cell. However, in accordance with embodiments described herein, other possible interdigitation layouts are described that may be less challenging. For example, as described in greater detail below, using alternative multibusbar designs may provide distinct advantages when migrating to next generation (e.g., lower cost) metallization strategies.
- In an exemplary process flow,
FIGS. 1A-1F illustrate cross-sectional views of various stages in the fabrication of a solar cell, in accordance with an embodiment of the present disclosure.FIG. 2 is aflowchart 200 listing operations in a method of fabricating a solar cell as corresponding toFIGS. 1A-1F , in accordance with an embodiment of the present disclosure. - Referring to
FIG. 1A andcorresponding operation 202 offlowchart 200, a method of fabricating alternating N-type and P-type emitter regions of a solar cell involves forming apolycrystalline silicon layer 106 on athin oxide layer 104 disposed on asubstrate 102. - In an embodiment, the
substrate 102 is a monocrystalline silicon substrate, such as a bulk single crystalline N-type doped silicon substrate. It is to be understood, however, thatsubstrate 102 may be a layer, such as a multi-crystalline silicon layer, disposed on a global solar cell substrate. In an embodiment, the thin oxide layer is a tunnel dielectric silicon oxide layer having a thickness of approximately 2 nanometers or less. Although described as apolycrystalline silicon layer 106, in an alternative embodiment, an amorphous silicon layer is used instead. - Referring to
FIG. 1B andcorresponding operation 204 offlowchart 200, the method also involves implanting, through afirst stencil mask 108, dopant impurity atoms of afirst conductivity type 110 in thepolycrystalline silicon layer 106 to form first implantedregions 112 of thepolycrystalline silicon layer 106 and non-implanted regions (i.e., remaining portions ofpolycrystalline silicon layer 106 that have not been implanted at this stage in the process). - In an embodiment, the
first stencil mask 108 is a silicon stencil mask. In one embodiment, use of a silicon stencil mask enables placement on, or in close proximity to, the structure ofFIG. 1A since the silicon of the stencil mask does not contaminate a silicon based solar cell. In an embodiment, the implanting is performed by using ion beam implantation or plasma immersion implantation. In one embodiment, this first implanting provides P+ dopant atoms for silicon (e.g., boron atoms). In another embodiment, however, the first implanting provides N+ dopant atoms for silicon (e.g., phosphorus atoms or arsenic atoms). In an embodiment, the conditions used to perform the implantation are tuned (e.g., by sequential or simultaneous electron bombardment) to enhance subsequent etch selectivity between implanted and non-implanted regions, as pertaining to later operations described below. Other conditions that may be tuned can include one or more of substrate biasing during implantation, temperature tuning, and dose tuning. - Referring again to
FIG. 1B and now tocorresponding operation 206 offlowchart 200, the method also involves forming, through thefirst stencil mask 108, afirst capping layer 114 on and substantially in alignment with the first implantedregions 112 of thepolycrystalline silicon layer 106. The alignment can be viewed as ideally perfect since the stencil mask and substrate travel together. However, the process can tolerate some slight offset (e.g., less than a few percent in a translational direction) that may occur while the process is moved from an implant/doping chamber to a cap deposition chamber. - In an embodiment, the implanting and the forming of the
first capping layer 114 are performed in an in-line process apparatus in which thefirst stencil mask 108 and themonocrystalline silicon substrate 102 are moved together through the in-line process apparatus, as described in greater detail in association withFIGS. 5A and 5B . In an embodiment, thefirst capping layer 114 includes a material such as, but not limited to, silicon dioxide (SiO2), silicon nitride (SiN) or silicon oxynitride (SiON). In an embodiment, thefirst capping layer 114 is formed using a deposition technique such as, but not limited to, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD) or physical vapor deposition (PVD). In an embodiment, thefirst capping layer 114 is formed by deposition at a temperature approximately in the range of 25-400 degrees Celsius. - Referring again to
FIG. 1B , the material of cappinglayer 114 may also be deposited on thefirst stencil mask 108. After numerous runs of thestencil mask 108 through the deposition environment, multiple material layers may ultimately accumulate, as is depicted inFIG. 1B . It is to be appreciated that an optimal number of runs may be determined to balance throughput against an over-accumulation of material on thestencil mask 108 that could in some way impact later deposition processes. In one such embodiment, after a certain number of runs, the accumulated capping material is removed by selective etching, and thefirst stencil mask 108 can then be reused. - Referring to
FIG. 1C andcorresponding operation 208 offlowchart 200, the method also involves implanting, through asecond stencil mask 116, dopant impurity atoms of a second, opposite,conductivity type 118 in portions of the non-implanted regions of thepolycrystalline silicon layer 106 to form second implantedregions 120 of thepolycrystalline silicon layer 106 and remaining non-implanted regions (i.e., remaining portions ofpolycrystalline silicon layer 106 that have not been implanted). - In an embodiment, the
second stencil mask 116 is a silicon stencil mask. In one embodiment, use of a silicon stencil mask enables placement on, or in close proximity to, the structure ofFIG. 1B since the silicon of the stencil mask does not contaminate a silicon based solar cell. In an embodiment, the implanting is performed by using ion beam implantation or plasma immersion implantation. In one embodiment, this second implanting provides N+ dopant atoms for silicon (e.g., phosphorus atoms or arsenic atoms). In another embodiment, however, the second implanting provides P+ dopant atoms for silicon (e.g., boron atoms). In an embodiment, the conditions used to perform the implantation are tuned (e.g., by sequential or simultaneous electron bombardment) to enhance subsequent etch selectivity between implanted and non-implanted regions, as pertaining to later operations described below. Other conditions that may be tuned can include one or more of substrate biasing during implantation, temperature tuning, and dose tuning. - Referring again to
FIG. 1C and now tocorresponding operation 210 offlowchart 200, the method also involves forming, through thesecond stencil mask 116, asecond capping layer 122 on and substantially in alignment with the second implantedregions 120 of thepolycrystalline silicon layer 106. The alignment can be viewed as ideally perfect since the stencil mask and substrate travel together. However, the process can tolerate some slight offset (e.g., less than a few percent in a translational direction) that may occur while the process is moved from an implant/doping chamber to a cap deposition chamber. - In an embodiment, the implanting and the forming of the
second capping layer 122 are performed in an in-line process apparatus in which thesecond stencil mask 116 and themonocrystalline silicon substrate 102 are moved together through the in-line process apparatus, as described in greater detail in association withFIGS. 5A and 5B . In an embodiment, thesecond capping layer 122 includes a material such as, but not limited to, silicon dioxide (SiO2), silicon nitride (SiN) or silicon oxynitride (SiON). In an embodiment, thesecond capping layer 122 is formed using a deposition technique such as, but not limited to, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD) or physical vapor deposition (PVD). In an embodiment, thesecond capping layer 122 is formed by deposition at a temperature approximately in the range of 25-400 degrees Celsius. - Referring again to
FIG. 1C , the material ofsecond capping layer 122 may also be deposited on thesecond stencil mask 116. As was the case with the first capping layer on the first stencil mask, after numerous runs of thesecond stencil mask 116 through the deposition environment, multiple material layers may ultimately accumulate, as is depicted inFIG. 1C . It is to be appreciated that an optimal number of runs may be determined to balance throughput against an over-accumulation of material on thestencil mask 116 that could in some way impact later deposition processes. In one such embodiment, after a certain number of runs, the accumulated capping material is removed by selective etching, and thesecond stencil mask 116 is then reused. - Referring to
FIG. 1D andcorresponding operation 212 offlowchart 200, the remaining non-implanted regions of thepolycrystalline silicon layer 106 can be removed. In an embodiment, thefirst capping layer 114 and thesecond capping layer 122 protect the first implantedregions 112 and the second implantedregions 120, respectively, during removal of the remaining non-implanted portions of thepolycrystalline silicon layer 106. In an embodiment, referring again toFIG. 1D , subsequent to and/or during the removal of the remaining non-implanted portions of thepolycrystalline silicon layer 106, the capping layers 114 and 122 can also be removed. In either case, the capping layers 114 and 122 should be suitably less susceptible to the etch than thepolycrystalline silicon layer 106 in order to provide at least a substantial amount of protection of the first implantedregions 112 and the second implanted regions 120 (e.g., without significantly eroding the implanted regions). - In an embodiment, the first and second capping layers 114 and 122 include a material such as, but not limited to, silicon dioxide (SiO2), silicon nitride (SiN) or silicon oxynitride (SiON), and removing the remaining non-implanted regions of the
polycrystalline silicon layer 106 involves using a hydroxide-based wet etch process. In one embodiment, the first and second capping layers 114 and 122 are then removed in a subsequent process using an HF-based wet etch process, such as a buffered oxide etchant (BOE) process. - Referring to
FIG. 1E andcorresponding operation 214 offlowchart 200, the first implantedregions 112 and the second implantedregions 120 of the polycrystalline silicon layer can be annealed to form first 124 and second 126 doped polycrystalline silicon emitter regions, respectively. While it may be generally most advantageous to complete the etch (i.e. removal) of non-implanted areas of polysilicon prior to performing a high temperature anneal and activation process, certain implant conditions may result in intrinsically higher reactivity in the texturizing etch (e.g., as relative to non-implanted regions), in which case a high temperature anneal can be performed prior to trench etch. - In an embodiment, the heating is performed at a temperature approximately in the range of 850-1100 degrees Celsius for a duration approximately in the range of 1-100 minutes. In an embodiment, a light P+ dopant drive is performed during the heating or annealing.
- Referring to both
FIGS. 1D and 1E , in an embodiment,trenches 128 are formed between the first 124 and second 126 doped polycrystalline silicon emitter regions. Furthermore, in an embodiment, the trenches and/or thelight receiving surface 101 of thesubstrate 102 are texturized. The ordering of operations of the trench formation and the annealing of the first implantedregions 112 and the second implantedregions 120 of the polycrystalline silicon layer to form first 124 and second 126 doped polycrystalline silicon emitter regions can be varied. In one embodiment, the trench formation and the texturizing are both performed in a same hydroxide-based etch process prior to the annealing, e.g., as part of the process used to remove non-implanted regions of thesilicon layer 106. Alternatively, the trench formation and the texturizing are performed subsequent to the annealing (as is depicted inFIGS. 1D and 1E ). In yet another embodiment, texturizing ofsurface 101 may be performed in an operation different from the operation used to form and texturizetrenches 128. It is to be appreciated that a texturized surface may be one which has a regular or an irregular shaped surface for scattering incoming light, decreasing the amount of light reflected off of the light-receiving surface of the solar cell. Additional embodiments can include formation of a passivation oranti-reflective coating layer 129 on the light-receivingsurface 101, as depicted inFIG. 1E . - Referring to
FIG. 1F ,conductive contacts layer 150 to have openings and then forming one or more conductive layers in the openings. In an embodiment, theconductive contacts - In one embodiment, the capping layers 114 and 122 (or at least remnants thereof) are retained in the final structure. In one such embodiment, the
contacts conductive contacts - It is to be appreciated that such a stencil mask based approach to self-aligned implant and capping regions and layers can be used for only one dopant type instead of for both dopant types. For example, the process may be particularly advantageous for one of P+ or N+ doping and is thus only used for fabrication of one of the two conductivity types of emitter regions. As an example,
FIG. 3 is aflowchart 300 listing operations in another method of fabricating a solar cell, in accordance with an embodiment of the present disclosure. - Referring to
operation 302 offlowchart 300, a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. Referring tooperation 304 offlowchart 300, through a stencil mask, dopant impurity atoms are implanted in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. Referring tooperation 306 offlowchart 300, through the stencil mask, a capping layer is formed on and substantially in alignment with the implanted regions of the silicon layer. Referring tooperation 308 offlowchart 300, the non-implanted regions of the silicon layer are removed. The capping layer protects the implanted regions of the silicon layer during the removing. Referring tooperation 310 offlowchart 300, the implanted regions of the silicon layer are annealed to form doped polycrystalline silicon emitter regions. - The above described processes can be used to enable patterned boron (or phosphorus or arsenic, etc.) implant and cap through a laser cut Si mask. The approach involves integrating implant with cap to address coefficient of temperature expansion (CTE) mismatch, contamination, and/or cleaning challenges. Approaches may be suitable for current solar cell designs. However, in one embodiment, mask integrity requirements may favor designs with reduced finger dimensions, such as a design fabricated to for an all Al metallization cell. As an example,
FIG. 4 illustrates a plan of a back surface of an aluminum metallization back contactsolar cell 400, in accordance with an embodiment of the present disclosure. - As described briefly above, the processes referred to herein may be performed on an in-line process apparatus. As an example,
FIG. 5A schematically illustrates a cross-sectional view of an inline platform for patterned implant and capping, in accordance with an embodiment of the present disclosure.FIG. 5B illustrates an implant and capping sequence through silicon contact masks in the apparatus ofFIG. 5A , in accordance with an embodiment of the present disclosure. - Referring to
FIG. 5A , an in-line process apparatus 500 for fabricating an emitter region of a solar cell includes afirst station 502 for aligning astencil mask 504 with asubstrate 506. Asecond station 508 is included for implanting dopant impurity atoms (e.g., boron or phosphorus) above thesubstrate 506, through thestencil mask 504. Athird station 510 is included for forming a capping layer above thesubstrate 506, through thestencil mask 504. Other aspects of the in-line process apparatus 500 can include awafer input area 512 and a mask removal andwafer output area 514. - In an embodiment, the
stencil mask 504 and thesubstrate 506 are moved together at least through the second 508 and third 510 stations. The direction of wafer flow through the in-line process apparatus 500 is shown byarrows 550. Referring toFIG. 5B , in an embodiment, the in-line process apparatus 500 enables implant and capping or regions of asilicon layer 507 on thesubstrate 506 through thestencil mask 504. The implantedregions 507A and thecapping layer 509 are self-aligned since the capping layer is formed using the same mask in the same position as is used to perform the implanting. In an embodiment, thefirst station 502 is for aligning thestencil mask 504 as in contact with on or in close proximity to thesubstrate 506. In an embodiment, thesecond station 508 includes an ion-implantation or plasma immersion implantation chamber. In an embodiment, thethird station 510 includes a deposition chamber such as, but not limited to, a low pressure chemical vapor deposition (LPCVD), a plasma enhanced chemical vapor deposition (PECVD) chamber, a high density plasma chemical vapor deposition (HDPCVD) chamber, or a physical vapor deposition (PVD) chamber. - In alternative embodiments, other stencil masks that may be contaminating for a silicon substrate may be used, so long as contact is not made between the mask and the substrate. For example, a graphite shadow mask may be used. Furthermore, in other embodiments, the stencil mask does not travel with the substrate. As an example of both alternatives,
FIG. 6A schematically illustrates a cross-sectional view of an inline platform for patterned implant involving traveling wafer and stationary shadow mask, in accordance with an embodiment of the present disclosure.FIG. 6B illustrates an implant sequence through graphite proximity masks in the apparatus ofFIG. 6A , in accordance with an embodiment of the present disclosure. Referring toFIG. 6A , aninline platform 600 includes awafer input region 602, an implant source 604 (e.g., ion implantation or plasma immersion), and anoutput region 606. A stationary stencil mask 608, such as a stationary graphite mask, is held in proximity to, but not in contact with, a substrate 610 to provide an implantedsubstrate 612. - As described briefly in association with
FIG. 4 , in an embodiment, mask integrity may favor solar cell designs with reduced finger dimensions, e.g., for interdigitated back contact (IBC) cells with thin wafer contact metal. Provided as examples,FIG. 7A illustrates a plan view of the back side of an IBCsolar cell 700A having an adjacent “Short Finger” multibusbar layout, in accordance with an embodiment of the present disclosure.FIG. 7B illustrates a plan view of the back side of an IBCsolar cell 700B having a metal foil backplane of copper (Cu) or aluminum (Al), in accordance with an embodiment of the present disclosure.FIG. 7C illustrates a plan view of the back side of an IBCsolar cell 700C havingmultiple contact points 750 attached with solder, a conductive adhesive or by laser spot welding (e.g., Al to Al), in accordance with an embodiment of the present disclosure. - Overall, although certain materials are described specifically above, some materials may be readily substituted with others with other such embodiments remaining within the spirit and scope of embodiments of the present disclosure. For example, in an embodiment, a different material substrate, such as a group material substrate, can be used instead of a silicon substrate. Furthermore, it is to be understood that, where N+ and P+ type doping is described specifically, other embodiments contemplated include the opposite conductivity type, e.g., P+ and N+ type doping, respectively.
- In general, embodiments described herein may be implemented to provide lower cost, high throughput ion implant platforms for the fabrication of high efficiency IBC-type solar cells. Specific embodiments can offer an advantageous approach for generating self-aligned implants and capping layers through a single Si contact stencil mask. In addition, to ensure implanted areas and capping films are automatically self-aligned, the combination of Si stencil masks with a process that automatically applies a dielectric capping film can address many of the cost, contamination, lifetime, and cleaning/reuse issues generally limiting the application of implant technology to solar cell fabrication. In addition to providing a self-aligned cap to serve as an etch mask for trench removal, the deposition of a capping film without breaking vacuum can reduce the degradation of implanted regions by air oxidation. Embodiments may be particularly useful for the fabrication of solar cells that incorporate polycrystalline silicon or amorphous silicon (e.g., a-Si:H) derived emitters.
- Thus, methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells, have been disclosed.
- Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.
- The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.
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US9577134B2 (en) | 2013-12-09 | 2017-02-21 | Sunpower Corporation | Solar cell emitter region fabrication using self-aligned implant and cap |
US9263625B2 (en) | 2014-06-30 | 2016-02-16 | Sunpower Corporation | Solar cell emitter region fabrication using ion implantation |
US20160072000A1 (en) * | 2014-09-05 | 2016-03-10 | David D. Smith | Front contact heterojunction process |
US20160284913A1 (en) | 2015-03-27 | 2016-09-29 | Staffan WESTERBERG | Solar cell emitter region fabrication using substrate-level ion implantation |
JP2018073969A (en) * | 2016-10-28 | 2018-05-10 | 株式会社アルバック | Method for manufacturing solar battery |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100240169A1 (en) * | 2009-03-19 | 2010-09-23 | Tswin Creeks Technologies, Inc. | Method to make electrical contact to a bonded face of a photovoltaic cell |
US20110041911A1 (en) * | 2009-08-18 | 2011-02-24 | Sungeun Lee | Solar cell and method of manufacturing the same |
US20120266951A1 (en) * | 2011-04-25 | 2012-10-25 | Bo Li | Method of forming emitters for a back-contact solar cell |
Family Cites Families (119)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2695852A (en) | 1952-02-15 | 1954-11-30 | Bell Telephone Labor Inc | Fabrication of semiconductors for signal translating devices |
US3736425A (en) | 1972-03-27 | 1973-05-29 | Implama Ag Z U G | Screen for ion implantation |
US3790412A (en) | 1972-04-07 | 1974-02-05 | Bell Telephone Labor Inc | Method of reducing the effects of particle impingement on shadow masks |
US4086102A (en) | 1976-12-13 | 1978-04-25 | King William J | Inexpensive solar cell and method therefor |
DE3135933A1 (en) * | 1980-09-26 | 1982-05-19 | Unisearch Ltd., Kensington, New South Wales | SOLAR CELL AND METHOD FOR THEIR PRODUCTION |
US4448797A (en) | 1981-02-04 | 1984-05-15 | Xerox Corporation | Masking techniques in chemical vapor deposition |
US4381956A (en) | 1981-04-06 | 1983-05-03 | Motorola, Inc. | Self-aligned buried channel fabrication process |
DE3176643D1 (en) | 1981-10-30 | 1988-03-10 | Ibm Deutschland | Shadow projecting mask for ion implantation and lithography by ion beam radiation |
US4557037A (en) | 1984-10-31 | 1985-12-10 | Mobil Solar Energy Corporation | Method of fabricating solar cells |
US4994405A (en) * | 1989-11-21 | 1991-02-19 | Eastman Kodak Company | Area image sensor with transparent electrodes |
US5356488A (en) * | 1991-12-27 | 1994-10-18 | Rudolf Hezel | Solar cell and method for its manufacture |
JP2970307B2 (en) * | 1993-05-17 | 1999-11-02 | 日本電気株式会社 | Method for manufacturing solid-state imaging device |
JPH11512886A (en) * | 1995-10-05 | 1999-11-02 | エバラ・ソーラー・インコーポレーテッド | Self-aligned partially deep diffused emitter solar cells. |
US5708264A (en) * | 1995-11-07 | 1998-01-13 | Eastman Kodak Company | Planar color filter array for CCDs from dyed and mordant layers |
US5641362A (en) * | 1995-11-22 | 1997-06-24 | Ebara Solar, Inc. | Structure and fabrication process for an aluminum alloy junction self-aligned back contact silicon solar cell |
TW335503B (en) * | 1996-02-23 | 1998-07-01 | Semiconductor Energy Lab Kk | Semiconductor thin film and manufacturing method and semiconductor device and its manufacturing method |
US5907766A (en) | 1996-10-21 | 1999-05-25 | Electric Power Research Institute, Inc. | Method of making a solar cell having improved anti-reflection passivation layer |
US5871591A (en) * | 1996-11-01 | 1999-02-16 | Sandia Corporation | Silicon solar cells made by a self-aligned, selective-emitter, plasma-etchback process |
JP3060979B2 (en) * | 1997-02-10 | 2000-07-10 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
JPH10260523A (en) * | 1997-03-18 | 1998-09-29 | Nikon Corp | Production of silicon stencil mask |
US6087274A (en) | 1998-03-03 | 2000-07-11 | The United States Of America As Represented By The Secretary Of The Navy | Nanoscale X-Y-Z translation of nanochannel glass replica-based masks for making complex structures during patterning |
US6335534B1 (en) | 1998-04-17 | 2002-01-01 | Kabushiki Kaisha Toshiba | Ion implantation apparatus, ion generating apparatus and semiconductor manufacturing method with ion implantation processes |
US6253441B1 (en) * | 1999-04-16 | 2001-07-03 | General Electric Company | Fabrication of articles having a coating deposited through a mask |
US6417078B1 (en) | 2000-05-03 | 2002-07-09 | Ibis Technology Corporation | Implantation process using sub-stoichiometric, oxygen doses at different energies |
JP2002203806A (en) | 2000-10-31 | 2002-07-19 | Toshiba Corp | Method for manufacturing semiconductor device, stencil mask and its manufacturing method |
JP2002185002A (en) * | 2000-12-15 | 2002-06-28 | Matsushita Electric Ind Co Ltd | Liquid crystal image display device and method for manufacturing semiconductor device for image display device |
US20030015700A1 (en) * | 2001-07-20 | 2003-01-23 | Motorola, Inc. | Suitable semiconductor structure for forming multijunction solar cell and method for forming the same |
JP2004193350A (en) | 2002-12-11 | 2004-07-08 | Sharp Corp | Solar battery cell and its manufacturing method |
JP3790215B2 (en) | 2002-12-26 | 2006-06-28 | 株式会社東芝 | Semiconductor device manufacturing method and semiconductor manufacturing apparatus |
US7388147B2 (en) * | 2003-04-10 | 2008-06-17 | Sunpower Corporation | Metal contact structure for solar cell and method of manufacture |
US7199395B2 (en) * | 2003-09-24 | 2007-04-03 | Sanyo Electric Co., Ltd. | Photovoltaic cell and method of fabricating the same |
US20060060238A1 (en) * | 2004-02-05 | 2006-03-23 | Advent Solar, Inc. | Process and fabrication methods for emitter wrap through back contact solar cells |
KR100598035B1 (en) | 2004-02-24 | 2006-07-07 | 삼성전자주식회사 | Manufacturing method of charge transfer image element |
US7531216B2 (en) | 2004-07-28 | 2009-05-12 | Advantech Global, Ltd | Two-layer shadow mask with small dimension apertures and method of making and using same |
US8420435B2 (en) | 2009-05-05 | 2013-04-16 | Solexel, Inc. | Ion implantation fabrication process for thin-film crystalline silicon solar cells |
JP2009507363A (en) * | 2005-07-27 | 2009-02-19 | シリコン・ジェネシス・コーポレーション | Method and structure for forming multiple tile portions on a plate using a controlled cleavage process |
EP1964165B1 (en) * | 2005-12-21 | 2018-03-14 | Sunpower Corporation | Fabrication processes of back side contact solar cells |
US20080000522A1 (en) * | 2006-06-30 | 2008-01-03 | General Electric Company | Photovoltaic device which includes all-back-contact configuration; and related processes |
FR2906406B1 (en) * | 2006-09-26 | 2008-12-19 | Commissariat Energie Atomique | PROCESS FOR PRODUCING A PHOTOVOLTAIC CELL WITH REAR-SIDE HETEROJUNCTION |
WO2008039461A2 (en) | 2006-09-27 | 2008-04-03 | Thinsilicon Corp. | Back contact device for photovoltaic cells and method of manufacturing a back contact |
US20100304521A1 (en) * | 2006-10-09 | 2010-12-02 | Solexel, Inc. | Shadow Mask Methods For Manufacturing Three-Dimensional Thin-Film Solar Cells |
US7999174B2 (en) * | 2006-10-09 | 2011-08-16 | Solexel, Inc. | Solar module structures and assembly methods for three-dimensional thin-film solar cells |
US8035028B2 (en) * | 2006-10-09 | 2011-10-11 | Solexel, Inc. | Pyramidal three-dimensional thin-film solar cells |
US7638438B2 (en) | 2006-12-12 | 2009-12-29 | Palo Alto Research Center Incorporated | Solar cell fabrication using extrusion mask |
US20080173347A1 (en) * | 2007-01-23 | 2008-07-24 | General Electric Company | Method And Apparatus For A Semiconductor Structure |
CN102569477A (en) * | 2007-02-08 | 2012-07-11 | 无锡尚德太阳能电力有限公司 | Hybrid silicon solar cell and manufacturing method thereof |
KR101441346B1 (en) * | 2007-04-27 | 2014-09-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method of fabricating the same |
US7838062B2 (en) * | 2007-05-29 | 2010-11-23 | Sunpower Corporation | Array of small contacts for solar cell fabrication |
WO2009029900A1 (en) | 2007-08-31 | 2009-03-05 | Applied Materials, Inc. | Improved methods of emitter formation in solar cells |
US7820460B2 (en) | 2007-09-07 | 2010-10-26 | Varian Semiconductor Equipment Associates, Inc. | Patterned assembly for manufacturing a solar cell and a method thereof |
US8876963B2 (en) * | 2007-10-17 | 2014-11-04 | Heraeus Precious Metals North America Conshohocken Llc | Dielectric coating for single sided back contact solar cells |
US20090139868A1 (en) * | 2007-12-03 | 2009-06-04 | Palo Alto Research Center Incorporated | Method of Forming Conductive Lines and Similar Features |
DE102007059486A1 (en) | 2007-12-11 | 2009-06-18 | Institut Für Solarenergieforschung Gmbh | Rear contact solar cell with elongated, interleaved emitter and base regions at the back and manufacturing method thereof |
GB0801787D0 (en) | 2008-01-31 | 2008-03-05 | Reclaim Resources Ltd | Apparatus and method for treating waste |
US8563352B2 (en) * | 2008-02-05 | 2013-10-22 | Gtat Corporation | Creation and translation of low-relief texture for a photovoltaic cell |
US8461032B2 (en) | 2008-03-05 | 2013-06-11 | Varian Semiconductor Equipment Associates, Inc. | Use of dopants with different diffusivities for solar cell manufacture |
US7727866B2 (en) | 2008-03-05 | 2010-06-01 | Varian Semiconductor Equipment Associates, Inc. | Use of chained implants in solar cells |
US20090227061A1 (en) | 2008-03-05 | 2009-09-10 | Nicholas Bateman | Establishing a high phosphorus concentration in solar cells |
JPWO2009110403A1 (en) * | 2008-03-07 | 2011-07-14 | 国立大学法人東北大学 | Photoelectric conversion element structure and solar cell |
TW200945596A (en) | 2008-04-16 | 2009-11-01 | Mosel Vitelic Inc | A method for making a solar cell with a selective emitter |
CN102150277A (en) | 2008-06-11 | 2011-08-10 | 因特瓦克公司 | Solar cell fabrication with faceting and ion implantation |
US7851698B2 (en) * | 2008-06-12 | 2010-12-14 | Sunpower Corporation | Trench process and structure for backside contact solar cells with polysilicon doped regions |
US8207444B2 (en) * | 2008-07-01 | 2012-06-26 | Sunpower Corporation | Front contact solar cell with formed electrically conducting layers on the front side and backside |
US8309446B2 (en) * | 2008-07-16 | 2012-11-13 | Applied Materials, Inc. | Hybrid heterojunction solar cell fabrication using a doping layer mask |
US7951637B2 (en) * | 2008-08-27 | 2011-05-31 | Applied Materials, Inc. | Back contact solar cells using printed dielectric barrier |
WO2010031011A2 (en) * | 2008-09-15 | 2010-03-18 | Udt Sensors, Inc. | Thin active layer fishbone photodiode with a shallow n+ layer and method of manufacturing the same |
US20120104460A1 (en) * | 2010-11-03 | 2012-05-03 | Alta Devices, Inc. | Optoelectronic devices including heterojunction |
US7816239B2 (en) | 2008-11-20 | 2010-10-19 | Varian Semiconductor Equipment Associates, Inc. | Technique for manufacturing a solar cell |
US20100184250A1 (en) | 2009-01-22 | 2010-07-22 | Julian Blake | Self-aligned selective emitter formed by counterdoping |
US20100229928A1 (en) * | 2009-03-12 | 2010-09-16 | Twin Creeks Technologies, Inc. | Back-contact photovoltaic cell comprising a thin lamina having a superstrate receiver element |
US8288645B2 (en) * | 2009-03-17 | 2012-10-16 | Sharp Laboratories Of America, Inc. | Single heterojunction back contact solar cell |
US9318644B2 (en) | 2009-05-05 | 2016-04-19 | Solexel, Inc. | Ion implantation and annealing for thin film crystalline solar cells |
US8551866B2 (en) * | 2009-05-29 | 2013-10-08 | Solexel, Inc. | Three-dimensional thin-film semiconductor substrate with through-holes and methods of manufacturing |
DE102009024807B3 (en) * | 2009-06-02 | 2010-10-07 | Helmholtz-Zentrum Berlin Für Materialien Und Energie Gmbh | Solar cell has photo-active, semiconducting absorber layer, where alternating adjacent arrangement of electrically insulating passivation areas on back of absorber layer with thickness |
KR101161807B1 (en) * | 2009-08-21 | 2012-07-03 | 주식회사 효성 | Method of manufacturing Back junction solar cell by using plasma doping and diffusion and the solar cell |
US20110073175A1 (en) * | 2009-09-29 | 2011-03-31 | Twin Creeks Technologies, Inc. | Photovoltaic cell comprising a thin lamina having emitter formed at light-facing and back surfaces |
KR101161482B1 (en) * | 2009-10-09 | 2012-07-02 | 한양대학교 산학협력단 | Polishing slurry composition having improved etch selectivity of silicon oxide to poly silicon and method for fabricating semiconductor device using the same |
US8465909B2 (en) * | 2009-11-04 | 2013-06-18 | Varian Semiconductor Equipment Associates, Inc. | Self-aligned masking for solar cell manufacture |
KR20110071375A (en) * | 2009-12-21 | 2011-06-29 | 현대중공업 주식회사 | Back contact type hetero-junction solar cell and method of fabricating the same |
US8241945B2 (en) * | 2010-02-08 | 2012-08-14 | Suniva, Inc. | Solar cells and methods of fabrication thereof |
US8921149B2 (en) | 2010-03-04 | 2014-12-30 | Varian Semiconductor Equipment Associates, Inc. | Aligning successive implants with a soft mask |
US8912082B2 (en) * | 2010-03-25 | 2014-12-16 | Varian Semiconductor Equipment Associates, Inc. | Implant alignment through a mask |
US8110431B2 (en) | 2010-06-03 | 2012-02-07 | Suniva, Inc. | Ion implanted selective emitter solar cells with in situ surface passivation |
CN201859877U (en) * | 2010-07-07 | 2011-06-08 | 无锡尚德太阳能电力有限公司 | Solar battery component |
KR20120026813A (en) * | 2010-09-10 | 2012-03-20 | 삼성전기주식회사 | Method for forming electrode structure and method for manufaturing the solar cell battery with the same, and solar cell battery manufactured by the method for manufaturing the solar cell battery |
US20120103406A1 (en) * | 2010-11-03 | 2012-05-03 | Alta Devices, Inc. | Metallic contacts for photovoltaic devices and low temperature fabrication processes thereof |
WO2012061593A2 (en) | 2010-11-03 | 2012-05-10 | Applied Materials, Inc. | Apparatus and methods for deposition of silicon carbide and silicon carbonitride films |
KR20140009984A (en) * | 2010-11-17 | 2014-01-23 | 히타치가세이가부시끼가이샤 | Method for producing solar cell |
US20120142140A1 (en) * | 2010-12-02 | 2012-06-07 | Applied Nanotech Holdings, Inc. | Nanoparticle inks for solar cells |
US8492253B2 (en) * | 2010-12-02 | 2013-07-23 | Sunpower Corporation | Method of forming contacts for a back-contact solar cell |
KR101241708B1 (en) * | 2011-01-27 | 2013-03-11 | 엘지이노텍 주식회사 | Solar cell apparatus and method of fabricating the same |
US8962424B2 (en) * | 2011-03-03 | 2015-02-24 | Palo Alto Research Center Incorporated | N-type silicon solar cell with contact/protection structures |
CN102760777A (en) * | 2011-04-29 | 2012-10-31 | 无锡尚德太阳能电力有限公司 | Solar cell, solar cell module and preparation method thereof |
KR101724005B1 (en) * | 2011-04-29 | 2017-04-07 | 삼성에스디아이 주식회사 | Solar cell and manufacturing method thereof |
US8658458B2 (en) * | 2011-06-15 | 2014-02-25 | Varian Semiconductor Equipment Associates, Inc. | Patterned doping for polysilicon emitter solar cells |
US8372737B1 (en) * | 2011-06-28 | 2013-02-12 | Varian Semiconductor Equipment Associates, Inc. | Use of a shadow mask and a soft mask for aligned implants in solar cells |
US20130228221A1 (en) * | 2011-08-05 | 2013-09-05 | Solexel, Inc. | Manufacturing methods and structures for large-area thin-film solar cells and other semiconductor devices |
US20130213469A1 (en) * | 2011-08-05 | 2013-08-22 | Solexel, Inc. | High efficiency solar cell structures and manufacturing methods |
US20140318611A1 (en) * | 2011-08-09 | 2014-10-30 | Solexel, Inc. | Multi-level solar cell metallization |
TW201319299A (en) | 2011-09-13 | 2013-05-16 | Applied Materials Inc | Activated silicon precursors for low temperature plasma enhanced deposition |
US8575033B2 (en) | 2011-09-13 | 2013-11-05 | Applied Materials, Inc. | Carbosilane precursors for low temperature film deposition |
KR101863294B1 (en) * | 2011-11-25 | 2018-05-31 | 인텔렉츄얼 키스톤 테크놀로지 엘엘씨 | Solar cell and method for fabricating the same |
KR101349505B1 (en) * | 2011-12-19 | 2014-01-10 | 엘지이노텍 주식회사 | Solar cell and method of fabricating the same |
US8597970B2 (en) * | 2011-12-21 | 2013-12-03 | Sunpower Corporation | Hybrid polysilicon heterojunction back contact cell |
DE102012205375A1 (en) * | 2012-04-02 | 2013-10-02 | Robert Bosch Gmbh | A multilayer back electrode for a photovoltaic thin film solar cell, the use of the multilayer back electrode for the production of thin film solar cells and modules, photovoltaic thin film solar cells and modules containing the multilayer back electrode, and a method of manufacturing photovoltaic thin film solar cells and modules |
US8962425B2 (en) * | 2012-05-23 | 2015-02-24 | Great Wall Semiconductor Corporation | Semiconductor device and method of forming junction enhanced trench power MOSFET having gate structure embedded within trench |
US20130319502A1 (en) * | 2012-05-31 | 2013-12-05 | Aqt Solar, Inc. | Bifacial Stack Structures for Thin-Film Photovoltaic Cells |
CN102931269A (en) * | 2012-11-29 | 2013-02-13 | 山东力诺太阳能电力股份有限公司 | N-type silicon substrate based back contact type HIT (Heterojunction with Intrinsic Thin layer) solar cell structure and preparation method thereof |
US9312406B2 (en) * | 2012-12-19 | 2016-04-12 | Sunpower Corporation | Hybrid emitter all back contact solar cell |
CN203038931U (en) * | 2012-12-21 | 2013-07-03 | 常州天合光能有限公司 | IBC solar cell structure with passivated back |
KR20140143278A (en) * | 2013-06-05 | 2014-12-16 | 엘지전자 주식회사 | Solar cell and method for manufacturing the same |
CN103337540B (en) * | 2013-06-28 | 2015-11-25 | 英利能源(中国)有限公司 | A kind of photovoltaic module |
WO2015084896A1 (en) * | 2013-12-02 | 2015-06-11 | Solexel, Inc. | Passivated contacts for back contact back junction solar cells |
US9577134B2 (en) | 2013-12-09 | 2017-02-21 | Sunpower Corporation | Solar cell emitter region fabrication using self-aligned implant and cap |
US9401450B2 (en) * | 2013-12-09 | 2016-07-26 | Sunpower Corporation | Solar cell emitter region fabrication using ion implantation |
US9196758B2 (en) * | 2013-12-20 | 2015-11-24 | Sunpower Corporation | Solar cell emitter region fabrication with differentiated p-type and n-type region architectures |
US20150270421A1 (en) * | 2014-03-20 | 2015-09-24 | Varian Semiconductor Equipment Associates, Inc. | Advanced Back Contact Solar Cells |
US9722105B2 (en) * | 2014-03-28 | 2017-08-01 | Sunpower Corporation | Conversion of metal seed layer for buffer material |
US9525083B2 (en) * | 2015-03-27 | 2016-12-20 | Sunpower Corporation | Solar cell emitter region fabrication with differentiated P-type and N-type architectures and incorporating a multi-purpose passivation and contact layer |
-
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- 2013-12-09 US US14/100,540 patent/US9577134B2/en active Active
-
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- 2014-11-25 WO PCT/US2014/067497 patent/WO2015088782A1/en active Application Filing
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100240169A1 (en) * | 2009-03-19 | 2010-09-23 | Tswin Creeks Technologies, Inc. | Method to make electrical contact to a bonded face of a photovoltaic cell |
US20110041911A1 (en) * | 2009-08-18 | 2011-02-24 | Sungeun Lee | Solar cell and method of manufacturing the same |
US20120266951A1 (en) * | 2011-04-25 | 2012-10-25 | Bo Li | Method of forming emitters for a back-contact solar cell |
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US20170162729A1 (en) | 2017-06-08 |
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