US20210005728A1 - Storage memory device - Google Patents

Storage memory device Download PDF

Info

Publication number
US20210005728A1
US20210005728A1 US16/579,086 US201916579086A US2021005728A1 US 20210005728 A1 US20210005728 A1 US 20210005728A1 US 201916579086 A US201916579086 A US 201916579086A US 2021005728 A1 US2021005728 A1 US 2021005728A1
Authority
US
United States
Prior art keywords
hafnium oxide
oxide
doped hafnium
doped
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US16/579,086
Inventor
Chun-Hu CHENG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Taiwan Normal University NTNU
Original Assignee
National Taiwan Normal University NTNU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW108123213A external-priority patent/TWI683420B/en
Priority claimed from TW108123214A external-priority patent/TWI744663B/en
Application filed by National Taiwan Normal University NTNU filed Critical National Taiwan Normal University NTNU
Assigned to NATIONAL TAIWAN NORMAL UNIVERSITY reassignment NATIONAL TAIWAN NORMAL UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHENG, CHUN-HU
Publication of US20210005728A1 publication Critical patent/US20210005728A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H01L27/11568—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2293—Timing circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Definitions

  • the disclosure relates to a memory device, and more particularly to a storage memory device.
  • a conventional non-volatile memory device includes a substrate, an insulating layer formed on a portion of the substrate, a source and a drain formed on opposite sides of the insulating layer, a charge trapping layer formed on the insulating layer, an insulating barrier formed on the charge trapping layer, and a gate formed on the insulating barrier.
  • a high dielectric constant (high-k) oxide such as silicon oxide, hafnium oxide and aluminum oxide, is commonly used as the insulating barrier.
  • the memory device including the high-k oxide would have higher off-state current and higher subthreshold swing, which is generally 70 mV/dec, as well as slower reading/erasing speed (about 100 ⁇ s to 1 ms).
  • U.S. Invention Patent Application Publication No. 2018182769 A1 discloses a flash memory that includes a stacked structure, which has a ferroelectric layer exhibiting a negative capacitance and a charge trapping layer. With such stacked structure, the flash memory has improved properties such as reduced leakage current, faster operating speed, lower subthreshold swing, and increased reading and writing speed.
  • an object of the disclosure is to provide a storage memory device having greater operating endurance and faster operating speed.
  • the storage memory device includes a field effect transistor including a semiconductor substrate, a first insulating layer, a source, a drain, a stacked structure, and a gate.
  • the first insulating layer is disposed on the semiconductor substrate.
  • the source and the drain are formed on the semiconductor substrate and are spaced apart from each other.
  • the stacked structure is disposed on the first insulating layer opposite to the semiconductor substrate, and includes a charge trapping layer and a composite element that has a ferroelectric layer and an antiferroelectric layer.
  • the ferroelectric layer is made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and that exhibits a negative capacitance.
  • the antiferroelectric layer is made of a zirconium oxide-based material having a predominantly tetragonal phase.
  • the gate is disposed on the stacked structure opposite to the first insulating layer.
  • FIG. 1 is a schematic view illustrating a field effect transistor of a first embodiment of a storage memory device according to the disclosure
  • FIG. 2 is a schematic view illustrating a variation of the field effect transistor of the embodiment
  • FIG. 3 is a graph showing simulated transfer characteristics of two different structures of the field effect transistors
  • FIG. 4 is a graph showing a pulse sequence during programming, reading and erasing operations of the embodiment
  • FIG. 5 is a graph showing the operating endurance of the embodiment.
  • FIG. 6 is a schematic perspective view illustrating a second embodiment of the field effect transistor of the storage memory device according to the disclosure.
  • a first embodiment of the storage memory device 2 includes a plurality of storage cells.
  • Each of the storage cells includes a planar field effect transistor 200 (1T) (see FIG. 1 ) and at least one capacitor (1C) (not shown).
  • FIG. 1 only illustrates the planar field effect transistor 200 of one of the storage cells of the storage memory device 2 .
  • the field effect transistor 200 includes a semiconductor substrate 21 , a source 22 , a drain 23 , a first insulating layer 24 , a stacked structure 25 and a gate 26 .
  • the first insulating layer 24 is disposed on the semiconductor substrate 21 .
  • the source 22 and the drain 23 are formed on the semiconductor substrate 21 and spaced apart from each other. In one aspect, the source 22 and the drain 23 are positioned on opposite sides of the insulating layer 24 .
  • the stacked structure 25 is disposed on the insulating layer 24 opposite to the semiconductor substrate 21 , and the gate 26 is disposed on the stacked structure 25 opposite to the first insulating layer 24 .
  • the semiconductor substrate 21 may be made of monocrystalline silicon, polycrystalline silicon, germanium or other suitable semiconductor materials.
  • the first insulating layer 24 may be a monolayer or multilayers of insulating material stacked together. Examples of the insulating material may include silicon oxide, aluminum oxide, etc.
  • the stacked structure 25 includes a charge trapping layer 251 and a composite element 252 .
  • the charge trapping layer 251 is made of a conductor, a semiconductor or an insulating material having a high dielectric constant.
  • the insulating material may be selected from the group consisting of silicon nitride (SiN x ), silicon carbide (SiC), a high dielectric constant (high-k) oxide having a non-orthorhombic phase (predominant crystalline phases of the high-k oxide are generally monoclinic or tetragonal phases), and combinations thereof.
  • the high-k oxide is selected from the group consisting of zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (TaO), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), silicon oxynitride (SiON), aluminum oxynitride (AlON), titanium oxynitride (TiON), tantalum oxynitride (TaON), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), and combinations thereof.
  • the composite element 252 has a ferroelectric layer 2521 and an antiferroelectric layer 2522 .
  • the ferroelectric layer 2521 is made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and that exhibits a negative capacitance. It is noted that a negative capacitance is observed in the doped hafnium oxide-based material having a predominantly orthorhombic phase.
  • Examples of the doped hafnium oxide-based material may include, but are not limited to, aluminum (Al)-doped hafnium oxide (HfAlO x ), silicon (Si)-doped hafnium oxide (HfSiO x ), strontium (Sr)-doped hafnium oxide (HfSrO x ), zirconium (Zr)-doped hafnium oxide (HfZrO x ), lanthanum (La)-doped hafnium oxide (HfLaO x ), yttrium (Y)-doped hafnium oxide (HfYO x ), gadolinium (Gd)-doped hafnium oxide (HfGdO x ), and combinations thereof.
  • the doped hafnium oxide-based material is Al-doped hafnium oxide
  • Al is present in an amount ranging from 2 mol % to 10 mol % based on a total molar amount of the Al-doped hafnium oxide.
  • Si is present in an amount ranging from 2 mol % to 10 mol % based on a total molar amount of the Si-doped hafnium oxide.
  • the doped hafnium oxide-based material is Sr-doped hafnium oxide
  • Sr is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of the Sr-doped hafnium oxide.
  • Zr is present in an amount ranging from 1 mol % to 50 mol % based on a total molar amount of the Zr-doped hafnium oxide.
  • the doped hafnium oxide-based material is La-doped hafnium oxide
  • La is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of the La-doped hafnium oxide.
  • Y is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of the Y-doped hafnium oxide.
  • Gd is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of the Gd-doped hafnium oxide.
  • the antiferroelectric layer 2522 is made of a zirconium oxide-based material having a predominantly tetragonal phase.
  • the zirconium oxide-based material may include undoped zirconium oxide (ZrO 2 ), doped zirconium oxide or the combination thereof.
  • the doped zirconium oxide may be doped with a dopant that is selected from the group consisting of silicon (i.e., the doped zirconium oxide being ZrSiO x ), aluminum (i.e., the doped zirconium oxide being ZrAlO x ), germanium (i.e., the doped zirconium oxide being ZrGeO x ), yttrium (i.e., the doped zirconium oxide being ZrYO x ), hafnium (i.e., the doped zirconium oxide being ZrHfO x ), and nitrogen (i.e., the doped zirconium oxide being ZrNO x ).
  • silicon i.e., the doped zirconium oxide being ZrSiO x
  • aluminum i.e., the doped zirconium oxide being ZrAlO x
  • germanium i.e., the doped zirconium oxide being Zr
  • the dopant may be present in an amount greater than 0 mol % and not greater than 50 mol % based on a total molar amount of the doped zirconium oxide.
  • the zirconium oxide-based material may include a combination of more than one of the doped zirconium oxides as mentioned above.
  • the zirconium oxide-based material may include ZrSiO x and ZrAlO x .
  • the doping concentration of the aforementioned doped hafnium oxide-based material and doped zirconium oxide may be adjusted according to the dopant properties and the crystalline phases of the ferroelectric and antiferroelectric layers to be formed.
  • the charge trapping layer 251 is formed on the first insulating layer 24
  • the composite element 252 is formed on the charge trapping layer 251 .
  • the composite element 252 may be formed on the first insulating layer 24
  • the charge trapping layer 251 is formed on the composite element 252 .
  • the ferroelectric layer 2521 is formed on the charge trapping layer 251
  • the antiferroelectric layer 2522 is formed on the ferroelectric layer 2521
  • the antiferroelectric layer 2522 is formed on the charge trapping layer 251
  • the ferroelectric layer 2521 is formed on the antiferroelectric layer 2522 .
  • the order of forming the ferroelectric layer 2521 and the antiferroelectric layer 2522 would not influence the object of this disclosure, and may be changed according to practical requirements.
  • the charge trapping layer 251 , the antiferroelectric layer 2522 and the ferroelectric layer 2521 may be formed on the first insulating layer 24 in such order, or in the order of antiferroelectric layer 2522 , ferroelectric layer 2521 , charge trapping layer 251 .
  • each of the ferroelectric layer 2521 , the antiferroelectric layer 2522 and the charge trapping layer 251 has a thickness ranging from 1 nm to 30 nm. In one aspect, to maintain better ferroelectricity, the ferroelectric layer 2521 may have a thickness ranging from 3 nm to 20 nm.
  • the gate 26 may be a monolayer or multilayer structure and is made of a metal or semiconductor material.
  • the metal material may be metal nitride or metal carbide having stress-induced strain effect, such that the doped hafnium oxide-based material of the ferroelectric layer 2521 having predominantly orthorhombic phase may be formed from a doped hafnium oxide-based material having a predominantly monoclinic phase through strain by the gate metal.
  • metal nitride or metal carbide may include, but are not limited to, tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum aluminum carbide (TaAlC).
  • the field effect transistor 200 further includes a second insulating layer 27 disposed between the stacked structure 25 and the gate 26 , and a third insulating layer 253 disposed between the charge trapping layer 251 and the composite element 252 .
  • Both of the second insulating layer 27 and the third insulating layer 253 are made of a dielectric insulating material having a non-orthorhombic phase and a high dielectric constant. It is noted that the second insulating layer 27 and the third insulating layer 253 are optionally positioned individually or simultaneously according to characteristics and requirements of the storage memory devices 2 .
  • the graph shows simulated transfer characteristics of two different structures of field effect transistors, one of which is the field effect transistor 200 of FIG. 1 having the antiferroelectric layer 2522 , the ferroelectric layer 2521 and the charge trapping layer 251 (shown as AFE/FE/CT in FIG. 3 ), and the other is a field effect transistor containing a ferroelectric layer and a charge trapping layer without an antiferroelectric layer (shown as FE/CT in FIG. 3 ).
  • the semiconductor substrate is made of silicon
  • the ferroelectric layer is made of HfZrO x with Zr being present in an amount of 40 mol % and has a thickness of 10 nm
  • the charge trapping layer is made of HfON and has a thickness of 6 nm.
  • the antiferroelectric layer is made of ZrO 2 and has a thickness of 10 nm.
  • drain voltages (V D ) applied to the two types of field effect transistors are both 0.2 V.
  • the minimum subthreshold swing (SS min ) of the AFE/FE/CT storage memory device is 56 mV/dec, which is smaller than that (i.e., 69 mV/dec) of the FE/CT storage memory device. This indicates that the AFE/FE/CT storage memory device has better control of the gate 26 of the field effect transistor 200 .
  • FIG. 4 which shows a pulse sequence during programming, reading and erasing operations of the embodiment
  • higher operating speed ⁇ 100 ns
  • FIG. 5 which shows the operating endurance of the embodiment
  • the simulation result shows that when programming and erasing voltages of ⁇ 10 V is applied for 100 ns, the AFE/FE/CT storage memory device according to the disclosure is capable of withstanding at least 10 8 program and erase cycles (P/E cycles), which means the AFE/FE/CT storage memory device according to the disclosure has better operating endurance and reliability than that of the conventional flash memory devices.
  • a second embodiment of the storage memory device 2 ′ includes a plurality of storage cells.
  • Each of the storage cells includes a fin field effect transistor 300 (1T) (see FIG. 6 ) and at least one capacitor (1C) (not shown).
  • FIG. 6 only illustrates the fin field effect transistor 300 of one of storage cells of the storage memory device 2 ′.
  • the fin field effect transistor 300 includes the semiconductor substrate 21 , the source 22 , the drain 23 , the first insulating layer 24 , the stacked structure 25 and the gate 26 .
  • the materials used for forming the above elements are the same as those used in the field effect transistor 200 and thus, are not illustrated herein for the sake of brevity.
  • the differences between the fin field effect transistor 300 and the field effect transistor 200 are illustrated in the following.
  • the fin field effect transistor 300 further includes a fin structure 20 that is disposed on the semiconductor substrate 21 and that contains the source 22 , the drain 23 and a connecting section 201 that is disposed between the source 22 and the drain 23 .
  • the stacked structure 25 is disposed on the connecting section 201 and covers a portion of the first insulating layer 24 .
  • the fin structure 20 extends upwardly from the semiconductor substrate 21 , and the first insulating layer 24 covers a portion of the semiconductor substrate 21 and a portion of a peripheral surface of the fin structure 20 .
  • the negative capacitance observed in the ferroelectric layer 2521 leads to smaller subthreshold swing of the storage memory devices 2 , 2 ′, thus reduces the power consumption during switching and off-state current of the field effect transistors 200 , 300 .
  • the antiferroelectric layer 2522 has a larger coercive field, the saturated polarization of the ferroelectric layer 2521 during erasing operation under high electric fields can be maximized. Further, reduction of the electric field across the ferroelectric layer 2521 and the charge trapping layer 251 minimizes the occurrence of failure and leakage current during repeated reading and programming operations. Therefore, the storage memory devices 2 , 2 ′ according to this disclosure have superior operating endurance and reliability.

Abstract

A storage memory device includes a field effect transistor including a semiconductor substrate, a first insulating layer that is disposed on the semiconductor substrate, a source and a drain that are formed on the semiconductor substrate and spaced apart from each other, a stacked structure, and a gate. The stacked structure includes a charge trapping layer and a composite element that has a ferroelectric layer and an antiferroelectric layer. The ferroelectric layer is made of a doped hafnium oxide-based material having a predominantly orthorhombic phase and exhibiting a negative capacitance. The antiferroelectric layer is made of a zirconium oxide-based material having a predominantly tetragonal phase.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims priority of Taiwanese Invention Patent Application Nos. 108123213 and 108123214, filed on Jul. 2, 2019.
    • FIELD
  • The disclosure relates to a memory device, and more particularly to a storage memory device.
    • BACKGROUND
  • A conventional non-volatile memory device includes a substrate, an insulating layer formed on a portion of the substrate, a source and a drain formed on opposite sides of the insulating layer, a charge trapping layer formed on the insulating layer, an insulating barrier formed on the charge trapping layer, and a gate formed on the insulating barrier. To effectively reduce the operating voltage of the memory device, a high dielectric constant (high-k) oxide, such as silicon oxide, hafnium oxide and aluminum oxide, is commonly used as the insulating barrier. However, the memory device including the high-k oxide would have higher off-state current and higher subthreshold swing, which is generally 70 mV/dec, as well as slower reading/erasing speed (about 100 μs to 1 ms).
  • U.S. Invention Patent Application Publication No. 2018182769 A1 discloses a flash memory that includes a stacked structure, which has a ferroelectric layer exhibiting a negative capacitance and a charge trapping layer. With such stacked structure, the flash memory has improved properties such as reduced leakage current, faster operating speed, lower subthreshold swing, and increased reading and writing speed.
  • Despite the rapid development of memory device, there is still a need for further improvement of the operating speed and the operating endurance of the memory device.
    • SUMMARY
  • Therefore, an object of the disclosure is to provide a storage memory device having greater operating endurance and faster operating speed.
  • The storage memory device includes a field effect transistor including a semiconductor substrate, a first insulating layer, a source, a drain, a stacked structure, and a gate. The first insulating layer is disposed on the semiconductor substrate. The source and the drain are formed on the semiconductor substrate and are spaced apart from each other. The stacked structure is disposed on the first insulating layer opposite to the semiconductor substrate, and includes a charge trapping layer and a composite element that has a ferroelectric layer and an antiferroelectric layer. The ferroelectric layer is made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and that exhibits a negative capacitance. The antiferroelectric layer is made of a zirconium oxide-based material having a predominantly tetragonal phase. The gate is disposed on the stacked structure opposite to the first insulating layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiments with reference to the accompanying drawings, of which:
  • FIG. 1 is a schematic view illustrating a field effect transistor of a first embodiment of a storage memory device according to the disclosure;
  • FIG. 2 is a schematic view illustrating a variation of the field effect transistor of the embodiment;
  • FIG. 3 is a graph showing simulated transfer characteristics of two different structures of the field effect transistors;
  • FIG. 4 is a graph showing a pulse sequence during programming, reading and erasing operations of the embodiment;
  • FIG. 5 is a graph showing the operating endurance of the embodiment; and
  • FIG. 6 is a schematic perspective view illustrating a second embodiment of the field effect transistor of the storage memory device according to the disclosure.
    •  DETAILED DESCRIPTION
  • Before the disclosure is described in greater detail, it should be noted that where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.
  • A first embodiment of the storage memory device 2 according to the disclosure includes a plurality of storage cells. Each of the storage cells includes a planar field effect transistor 200 (1T) (see FIG. 1) and at least one capacitor (1C) (not shown). FIG. 1 only illustrates the planar field effect transistor 200 of one of the storage cells of the storage memory device 2.
  • Referring to FIG. 1, the field effect transistor 200 includes a semiconductor substrate 21, a source 22, a drain 23, a first insulating layer 24, a stacked structure 25 and a gate 26.
  • The first insulating layer 24 is disposed on the semiconductor substrate 21. The source 22 and the drain 23 are formed on the semiconductor substrate 21 and spaced apart from each other. In one aspect, the source 22 and the drain 23 are positioned on opposite sides of the insulating layer 24. The stacked structure 25 is disposed on the insulating layer 24 opposite to the semiconductor substrate 21, and the gate 26 is disposed on the stacked structure 25 opposite to the first insulating layer 24.
  • Specifically, the semiconductor substrate 21 may be made of monocrystalline silicon, polycrystalline silicon, germanium or other suitable semiconductor materials. The first insulating layer 24 may be a monolayer or multilayers of insulating material stacked together. Examples of the insulating material may include silicon oxide, aluminum oxide, etc.
  • The stacked structure 25 includes a charge trapping layer 251 and a composite element 252. The charge trapping layer 251 is made of a conductor, a semiconductor or an insulating material having a high dielectric constant. The insulating material may be selected from the group consisting of silicon nitride (SiNx), silicon carbide (SiC), a high dielectric constant (high-k) oxide having a non-orthorhombic phase (predominant crystalline phases of the high-k oxide are generally monoclinic or tetragonal phases), and combinations thereof. The high-k oxide is selected from the group consisting of zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (TaO), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), silicon oxynitride (SiON), aluminum oxynitride (AlON), titanium oxynitride (TiON), tantalum oxynitride (TaON), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), and combinations thereof.
  • The composite element 252 has a ferroelectric layer 2521 and an antiferroelectric layer 2522. The ferroelectric layer 2521 is made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and that exhibits a negative capacitance. It is noted that a negative capacitance is observed in the doped hafnium oxide-based material having a predominantly orthorhombic phase. Examples of the doped hafnium oxide-based material may include, but are not limited to, aluminum (Al)-doped hafnium oxide (HfAlOx), silicon (Si)-doped hafnium oxide (HfSiOx), strontium (Sr)-doped hafnium oxide (HfSrOx), zirconium (Zr)-doped hafnium oxide (HfZrOx), lanthanum (La)-doped hafnium oxide (HfLaOx), yttrium (Y)-doped hafnium oxide (HfYOx), gadolinium (Gd)-doped hafnium oxide (HfGdOx), and combinations thereof.
  • When the doped hafnium oxide-based material is Al-doped hafnium oxide, Al is present in an amount ranging from 2 mol % to 10 mol % based on a total molar amount of the Al-doped hafnium oxide. When the doped hafnium oxide-based material is Si-doped hafnium oxide, Si is present in an amount ranging from 2 mol % to 10 mol % based on a total molar amount of the Si-doped hafnium oxide. When the doped hafnium oxide-based material is Sr-doped hafnium oxide, Sr is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of the Sr-doped hafnium oxide. When the doped hafnium oxide-based material is Zr-doped hafnium oxide, Zr is present in an amount ranging from 1 mol % to 50 mol % based on a total molar amount of the Zr-doped hafnium oxide. When the doped hafnium oxide-based material is La-doped hafnium oxide, La is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of the La-doped hafnium oxide. When the doped hafnium oxide-based material is Y-doped hafnium oxide, Y is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of the Y-doped hafnium oxide. When the doped hafnium oxide-based material is Gd-doped hafnium oxide, Gd is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of the Gd-doped hafnium oxide.
  • The antiferroelectric layer 2522 is made of a zirconium oxide-based material having a predominantly tetragonal phase. The zirconium oxide-based material may include undoped zirconium oxide (ZrO2), doped zirconium oxide or the combination thereof. The doped zirconium oxide may be doped with a dopant that is selected from the group consisting of silicon (i.e., the doped zirconium oxide being ZrSiOx), aluminum (i.e., the doped zirconium oxide being ZrAlOx), germanium (i.e., the doped zirconium oxide being ZrGeOx), yttrium (i.e., the doped zirconium oxide being ZrYOx), hafnium (i.e., the doped zirconium oxide being ZrHfOx), and nitrogen (i.e., the doped zirconium oxide being ZrNOx). The dopant may be present in an amount greater than 0 mol % and not greater than 50 mol % based on a total molar amount of the doped zirconium oxide. It is worth mentioning that the zirconium oxide-based material may include a combination of more than one of the doped zirconium oxides as mentioned above. For example, the zirconium oxide-based material may include ZrSiOx and ZrAlOx.
  • It is noted that the doping concentration of the aforementioned doped hafnium oxide-based material and doped zirconium oxide may be adjusted according to the dopant properties and the crystalline phases of the ferroelectric and antiferroelectric layers to be formed.
  • In this embodiment, the charge trapping layer 251 is formed on the first insulating layer 24, and the composite element 252 is formed on the charge trapping layer 251. In one aspect, the composite element 252 may be formed on the first insulating layer 24, and the charge trapping layer 251 is formed on the composite element 252.
  • In addition, in this embodiment, the ferroelectric layer 2521 is formed on the charge trapping layer 251, and the antiferroelectric layer 2522 is formed on the ferroelectric layer 2521. In other aspects, the antiferroelectric layer 2522 is formed on the charge trapping layer 251, and the ferroelectric layer 2521 is formed on the antiferroelectric layer 2522. The order of forming the ferroelectric layer 2521 and the antiferroelectric layer 2522 would not influence the object of this disclosure, and may be changed according to practical requirements. That is, the charge trapping layer 251, the antiferroelectric layer 2522 and the ferroelectric layer 2521 may be formed on the first insulating layer 24 in such order, or in the order of antiferroelectric layer 2522, ferroelectric layer 2521, charge trapping layer 251.
  • In this embodiment, each of the ferroelectric layer 2521, the antiferroelectric layer 2522 and the charge trapping layer 251 has a thickness ranging from 1 nm to 30 nm. In one aspect, to maintain better ferroelectricity, the ferroelectric layer 2521 may have a thickness ranging from 3 nm to 20 nm.
  • The gate 26 may be a monolayer or multilayer structure and is made of a metal or semiconductor material. In some aspects, the metal material may be metal nitride or metal carbide having stress-induced strain effect, such that the doped hafnium oxide-based material of the ferroelectric layer 2521 having predominantly orthorhombic phase may be formed from a doped hafnium oxide-based material having a predominantly monoclinic phase through strain by the gate metal. Examples of the metal nitride or metal carbide may include, but are not limited to, tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum aluminum carbide (TaAlC).
  • Referring to FIG. 2, in a variation of the first embodiment, the field effect transistor 200 further includes a second insulating layer 27 disposed between the stacked structure 25 and the gate 26, and a third insulating layer 253 disposed between the charge trapping layer 251 and the composite element 252. Both of the second insulating layer 27 and the third insulating layer 253 are made of a dielectric insulating material having a non-orthorhombic phase and a high dielectric constant. It is noted that the second insulating layer 27 and the third insulating layer 253 are optionally positioned individually or simultaneously according to characteristics and requirements of the storage memory devices 2.
  • Referring to FIG. 3, the graph shows simulated transfer characteristics of two different structures of field effect transistors, one of which is the field effect transistor 200 of FIG. 1 having the antiferroelectric layer 2522, the ferroelectric layer 2521 and the charge trapping layer 251 (shown as AFE/FE/CT in FIG. 3), and the other is a field effect transistor containing a ferroelectric layer and a charge trapping layer without an antiferroelectric layer (shown as FE/CT in FIG. 3). In these two types of field effect transistors, the semiconductor substrate is made of silicon, the ferroelectric layer is made of HfZrOx with Zr being present in an amount of 40 mol % and has a thickness of 10 nm, and the charge trapping layer is made of HfON and has a thickness of 6 nm. For the AFE/FE/CT storage memory device, the antiferroelectric layer is made of ZrO2 and has a thickness of 10 nm.
  • In simulation, drain voltages (VD) applied to the two types of field effect transistors are both 0.2 V. As shown in FIG. 3, the minimum subthreshold swing (SSmin) of the AFE/FE/CT storage memory device is 56 mV/dec, which is smaller than that (i.e., 69 mV/dec) of the FE/CT storage memory device. This indicates that the AFE/FE/CT storage memory device has better control of the gate 26 of the field effect transistor 200.
  • Referring to FIG. 4, which shows a pulse sequence during programming, reading and erasing operations of the embodiment, higher operating speed (<100 ns) may be obtained in the AFE/FE/CT storage memory device according to the disclosure compared to the FE/CT storage memory device, which has an operating speed around 800 ns. Moreover, referring to FIG. 5, which shows the operating endurance of the embodiment, the simulation result shows that when programming and erasing voltages of ±10 V is applied for 100 ns, the AFE/FE/CT storage memory device according to the disclosure is capable of withstanding at least 108 program and erase cycles (P/E cycles), which means the AFE/FE/CT storage memory device according to the disclosure has better operating endurance and reliability than that of the conventional flash memory devices.
  • In addition, a second embodiment of the storage memory device 2′ according to the disclosure includes a plurality of storage cells. Each of the storage cells includes a fin field effect transistor 300 (1T) (see FIG. 6) and at least one capacitor (1C) (not shown). FIG. 6 only illustrates the fin field effect transistor 300 of one of storage cells of the storage memory device 2′.
  • Similar to the field effect transistor 200 of FIG. 1, the fin field effect transistor 300 includes the semiconductor substrate 21, the source 22, the drain 23, the first insulating layer 24, the stacked structure 25 and the gate 26. The materials used for forming the above elements are the same as those used in the field effect transistor 200 and thus, are not illustrated herein for the sake of brevity. The differences between the fin field effect transistor 300 and the field effect transistor 200 are illustrated in the following.
  • The fin field effect transistor 300 further includes a fin structure 20 that is disposed on the semiconductor substrate 21 and that contains the source 22, the drain 23 and a connecting section 201 that is disposed between the source 22 and the drain 23. The stacked structure 25 is disposed on the connecting section 201 and covers a portion of the first insulating layer 24. The fin structure 20 extends upwardly from the semiconductor substrate 21, and the first insulating layer 24 covers a portion of the semiconductor substrate 21 and a portion of a peripheral surface of the fin structure 20. Similar to the first embodiment of the storage memory device 2 having the stacked structure 25 that includes the ferroelectric layer 2521 and the antiferroelectric layer 2522, power consumption during switching and the off-state current of the field effect transistor 300 are reduced, thereby enhancing the operating endurance of the storage memory device 2′.
  • In conclusion, the negative capacitance observed in the ferroelectric layer 2521 leads to smaller subthreshold swing of the storage memory devices 2, 2′, thus reduces the power consumption during switching and off-state current of the field effect transistors 200, 300. In addition, since the antiferroelectric layer 2522 has a larger coercive field, the saturated polarization of the ferroelectric layer 2521 during erasing operation under high electric fields can be maximized. Further, reduction of the electric field across the ferroelectric layer 2521 and the charge trapping layer 251 minimizes the occurrence of failure and leakage current during repeated reading and programming operations. Therefore, the storage memory devices 2, 2′ according to this disclosure have superior operating endurance and reliability.
  • In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects, and that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure.
  • While the disclosure has been described in connection with what are considered the exemplary embodiments, it is understood that this disclosure is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.

Claims (15)

What is claimed is:
1. A storage memory device, comprising a field effect transistor including:
a semiconductor substrate;
a first insulating layer disposed on said semiconductor substrate;
a source and a drain formed on said semiconductor substrate and spaced apart from each other;
a stacked structure disposed on said first insulating layer opposite to said semiconductor substrate and including a charge trapping layer and a composite element that has a ferroelectric layer and an antiferroelectric layer, said ferroelectric layer being made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and that exhibits a negative capacitance, said antiferroelectric layer being made of a zirconium oxide-based material having a predominantly tetragonal phase; and
a gate disposed on said stacked structure opposite to said first insulating layer.
2. The storage memory device of claim 1, wherein said charge trapping layer is made of a material selected from the group consisting of silicon nitride, silicon carbide, a high dielectric constant oxide having a non-orthorhombic phase, and combinations thereof.
3. The storage memory device of claim 2, wherein said high dielectric constant oxide is selected from the group consisting of zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zirconium oxynitride, hafnium oxynitride, silicon oxynitride, aluminum oxynitride, titanium oxynitride, tantalum oxynitride, hafnium silicon oxide, zirconium silicon oxide, and combinations thereof.
4. The storage memory device of claim 1, wherein said doped hafnium oxide-based material is selected from the group consisting of aluminum (Al)-doped hafnium oxide, silicon (Si)-doped hafnium oxide, strontium (Sr)-doped hafnium oxide, zirconium (Zr)-doped hafnium oxide, lanthanum (La)-doped hafnium oxide, yttrium (Y)-doped hafnium oxide, gadolinium (Gd)-doped hafnium oxide, and combinations thereof.
5. The storage memory device of claim 4, wherein:
when said doped hafnium oxide-based material is Al-doped hafnium oxide, Al is present in an amount ranging from 2 mol % to 10 mol % based on a total molar amount of said Al-doped hafnium oxide;
when said doped hafnium oxide-based material is Si-doped hafnium oxide, Si is present in an amount ranging from 2 mol % to 10 mol % based on a total molar amount of said Si-doped hafnium oxide;
when said doped hafnium oxide-based material is Sr-doped hafnium oxide, Sr is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of said Sr-doped hafnium oxide;
when said doped hafnium oxide-based material is Zr-doped hafnium oxide, Zr is present in an amount ranging from 1 mol % to 50 mol % based on a total molar amount of said Zr-doped hafnium oxide;
when said doped hafnium oxide-based material is La-doped hafnium oxide, La is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of said La-doped hafnium oxide;
when said doped hafnium oxide-based material is Y-doped hafnium oxide, Y is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of said Y-doped hafnium oxide; and
when said doped hafnium oxide-based material is Gd-doped hafnium oxide, Gd is present in an amount ranging from 2 mol % to 15 mol % based on a total molar amount of said Gd-doped hafnium oxide.
6. The storage memory device of claim 1, wherein said zirconium oxide-based material includes one of undoped zirconium oxide, doped zirconium oxide and the combination thereof.
7. The storage memory device of claim 6, wherein said zirconium oxide-based material includes at least one of doped zirconium oxide that is zirconium oxide doped with a dopant, said dopant being selected from the group consisting of silicon, aluminum, germanium, yttrium, hafnium and nitrogen, and being present in an amount greater than 0 mol % and not greater than 50 mol % based on a total molar amount of said doped zirconium oxide.
8. The storage memory device of claim 1, wherein each of said ferroelectric layer, said antiferroelectric layer and said charge trapping layer has a thickness ranging from 1 nm to 30 nm.
9. The storage memory device of claim 1, wherein said field effect transistor further includes a second insulating layer disposed between said stacked structure and said gate.
10. The storage memory device of claim 9, wherein said second insulating layer is made of a dielectric insulating material having a non-orthorhombic phase.
11. The storage memory device of claim 1, wherein said stacked structure further includes a third insulating layer disposed between said charge trapping layer and said composite element.
12. The storage memory device of claim 11, wherein said third insulating layer is made of a dielectric insulating material having a non-orthorhombic phase.
13. The storage memory device of claim 1, wherein said field effect transistor is a fin field effect transistor.
14. The storage memory device of claim 13, wherein said fin field effect transistor includes a fin structure that is disposed on said semiconductor substrate and that contains said source, said drain and a connecting section between said source and said drain, said stacked structure being disposed on said connecting section and covering a portion of said first insulating layer.
15. The storage memory device of claim 14, wherein said fin structure extending upwardly from said semiconductor substrate, said first insulating layer covering at least a portion of said semiconductor substrate and a portion of a peripheral surface of said fin structure.
US16/579,086 2019-07-02 2019-09-23 Storage memory device Abandoned US20210005728A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW108123213A TWI683420B (en) 2019-07-02 2019-07-02 Hybrid storage memory having vertical type of fet
TW108123214 2019-07-02
TW108123213 2019-07-02
TW108123214A TWI744663B (en) 2019-07-02 2019-07-02 Hybrid storage memory

Publications (1)

Publication Number Publication Date
US20210005728A1 true US20210005728A1 (en) 2021-01-07

Family

ID=73823590

Family Applications (2)

Application Number Title Priority Date Filing Date
US16/579,086 Abandoned US20210005728A1 (en) 2019-07-02 2019-09-23 Storage memory device
US16/676,669 Active US10872966B1 (en) 2019-07-02 2019-11-07 Storage memory device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US16/676,669 Active US10872966B1 (en) 2019-07-02 2019-11-07 Storage memory device

Country Status (1)

Country Link
US (2) US20210005728A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10978125B1 (en) * 2020-04-21 2021-04-13 Namlab Ggmbh Transistor with adjustable rectifying transfer characteristic
US20210358694A1 (en) * 2020-05-13 2021-11-18 Samsung Electronics Co., Ltd. Capacitor, method of controlling the same, and transistor including the same
US11217661B2 (en) * 2020-02-03 2022-01-04 Industrial Technology Research Institute Ferroelectric memories
US20230099330A1 (en) * 2021-09-24 2023-03-30 SK Hynix Inc. Semiconductor device including ferroelectric layer and insulation layer with metal particles and methods of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11889701B2 (en) 2021-04-22 2024-01-30 Globalfoundries U.S. Inc. Memory cell including polarization retention member(s) including antiferroelectric layer over ferroelectric layer

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269785B2 (en) * 2014-01-27 2016-02-23 Globalfoundries Inc. Semiconductor device with ferroelectric hafnium oxide and method for forming semiconductor device
US10242989B2 (en) * 2014-05-20 2019-03-26 Micron Technology, Inc. Polar, chiral, and non-centro-symmetric ferroelectric materials, memory cells including such materials, and related devices and methods
US9299799B2 (en) * 2014-06-10 2016-03-29 International Business Machines Corporation Semiconductor devices containing an epitaxial perovskite/doped strontium titanate structure
DE102014109147A1 (en) * 2014-06-30 2015-12-31 Infineon Technologies Ag Field effect semiconductor device and method for its operation and production
US9293556B2 (en) * 2014-07-29 2016-03-22 Globalfoundries Inc. Semiconductor structure including a ferroelectric transistor and method for the formation thereof
US9337045B2 (en) * 2014-08-13 2016-05-10 Globalfoundries Inc. Methods of forming a semiconductor circuit element and semiconductor circuit element
US20160064510A1 (en) * 2014-08-26 2016-03-03 Globalfoundries Inc. Device including a floating gate electrode and a layer of ferroelectric material and method for the formation thereof
US9412600B2 (en) * 2014-08-28 2016-08-09 Globalfoundries Inc. Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor
US20160071947A1 (en) * 2014-09-10 2016-03-10 Globalfoundries Inc. Method including a replacement of a dummy gate structure with a gate structure including a ferroelectric material
US9159829B1 (en) * 2014-10-07 2015-10-13 Micron Technology, Inc. Recessed transistors containing ferroelectric material
US20160118404A1 (en) * 2014-10-09 2016-04-28 Haibing Peng Three-dimensional non-volatile ferroelectric random access memory
DE102014221371B4 (en) * 2014-10-21 2018-04-19 Globalfoundries Inc. A method of forming a semiconductor circuit element and semiconductor circuit element
EP3038141B1 (en) * 2014-12-23 2019-08-28 IMEC vzw Method of reading a memory cell of a vertical ferroelectric memory device
TWI611515B (en) 2016-11-15 2018-01-11 National Taiwan Normal University Strained-gate engineered dynamic random access memory including ferroelectric negative capacitance dielectrics and manufacturing method thereof
US10515857B2 (en) 2017-09-28 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor devices
KR20200083981A (en) 2017-11-30 2020-07-09 인텔 코포레이션 Pin patterning for advanced integrated circuit structure fabrication

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11217661B2 (en) * 2020-02-03 2022-01-04 Industrial Technology Research Institute Ferroelectric memories
US10978125B1 (en) * 2020-04-21 2021-04-13 Namlab Ggmbh Transistor with adjustable rectifying transfer characteristic
US20210358694A1 (en) * 2020-05-13 2021-11-18 Samsung Electronics Co., Ltd. Capacitor, method of controlling the same, and transistor including the same
US11765887B2 (en) * 2020-05-13 2023-09-19 Samsung Electronics Co., Ltd. Capacitor, method of controlling the same, and transistor including the same
US11980023B2 (en) 2020-05-13 2024-05-07 Samsung Electronics Co., Ltd. Capacitor, method of controlling the same, and transistor including the same
US20230099330A1 (en) * 2021-09-24 2023-03-30 SK Hynix Inc. Semiconductor device including ferroelectric layer and insulation layer with metal particles and methods of manufacturing the same

Also Published As

Publication number Publication date
US10872966B1 (en) 2020-12-22
US20210005733A1 (en) 2021-01-07

Similar Documents

Publication Publication Date Title
US20210005728A1 (en) Storage memory device
US9837435B1 (en) Three-dimensional non-volatile memory structure and manufacturing method thereof
US10374054B2 (en) Ferroelectric memory devices
US7053448B2 (en) SONOS type memory device
US7816727B2 (en) High-κ capped blocking dielectric bandgap engineered SONOS and MONOS
US6858906B2 (en) Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
JP5027381B2 (en) Nonvolatile semiconductor memory device having OHA film on gate stack and manufacturing method thereof
US7804120B2 (en) Non-volatile semiconductor memory devices
US10833091B2 (en) Ferroelectric memories
US10403721B2 (en) Field effect transistor, memory element and manufacturing method of charge storage structure using paraelectric and ferroelectric material
US11804536B2 (en) Thin film structure and semiconductor device including the same
TW201637172A (en) Memory structure
US20190148540A1 (en) Floating gate non-volatile memory device
TWI709227B (en) Non-volatile memory device and operation method thereof
KR20090052682A (en) Non-volatile memory device, and memory card and system including the same
KR100456580B1 (en) Floating trap type memory device of non-volatile semiconductor memory device
TWI683420B (en) Hybrid storage memory having vertical type of fet
TWI744663B (en) Hybrid storage memory
US8237214B2 (en) Non-volatile memory device including metal-insulator transition material
JP2023016792A (en) Antiferroelectric thin film structure and electronic device including the same
KR100615098B1 (en) Non-volatile Flash memory cell having folating gates
KR20220060458A (en) Semiconductor device
KR20220060450A (en) Thin film structure and semiconductor device comprising the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: NATIONAL TAIWAN NORMAL UNIVERSITY, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHENG, CHUN-HU;REEL/FRAME:050680/0594

Effective date: 20190924

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION