US20190318930A1 - Patterning method - Google Patents
Patterning method Download PDFInfo
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- US20190318930A1 US20190318930A1 US15/975,730 US201815975730A US2019318930A1 US 20190318930 A1 US20190318930 A1 US 20190318930A1 US 201815975730 A US201815975730 A US 201815975730A US 2019318930 A1 US2019318930 A1 US 2019318930A1
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- 238000000034 method Methods 0.000 title claims abstract description 132
- 238000000059 patterning Methods 0.000 title claims abstract description 79
- 238000005530 etching Methods 0.000 claims abstract description 31
- 238000009832 plasma treatment Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 26
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 238000011282 treatment Methods 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000005984 hydrogenation reaction Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 117
- 238000013459 approach Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910021324 titanium aluminide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Definitions
- the present invention relates to a patterning method, and more particularly, to a patterning method including a trim process.
- the integrated circuit is constructed by devices and interconnections, which are formed by patterned feature in a substrate or in different layers.
- photolithography process has been an essential technique.
- the photolithography process is applied to form designed patterns such as layout patterns on one or more photomask, and then to transfer such patterns to a photoresist layer on a film by exposure and development steps for precisely transferring the complicated layout pattern to a semiconductor chip.
- the double patterning technique includes a litho-etch-litho-etch (LELE) double patterning approach, a litho-freeze-litho-etch (LFLE) double patterning approach, and a self-aligned double patterning (SADP) approach.
- LELE litho-etch-litho-etch
- LFLE litho-freeze-litho-etch
- SADP self-aligned double patterning
- the layout pattern cannot be ideally transferred because there are still many manufacturing issues in the conventional SADP approach, such as the uniformity of etching recessing loading and spacer bending issue.
- the manufacturing yield and the operation performance of the device formed by the conventional SADP approach are influenced accordingly.
- a patterning method is provided in the present invention.
- a first mask layer and a second mask layer are patterned concurrently for becoming a first mask pattern and a second mask pattern respectively.
- a first trim process is performed to the second mask pattern so that a width of the second mask pattern becomes smaller than a width of the first mask pattern.
- the second mask pattern with the smaller width may be formed self-aligned on the first mask pattern, and the second mask pattern may be used to form a pattern with a critical dimension (CD) smaller than the first mask pattern.
- CD critical dimension
- a patterning method includes the following steps.
- a second mask layer is formed on a first mask layer.
- a patterning process is performed to the first mask layer and the second mask layer.
- the first mask layer is patterned to be a first mask pattern
- the second mask layer is patterned to be a second mask pattern formed on the first mask pattern.
- a first trim process is performed to the second mask pattern.
- a width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process.
- a cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process.
- An etching process is performed to the first mask pattern after the step of forming the cover layer.
- FIG. 11 is a schematic drawing illustrating a patterning method according to a second embodiment of the present invention.
- FIG. 12 is a schematic drawing illustrating a patterning method according to a third embodiment of the present invention.
- FIGS. 1-10 are schematic drawings illustrating a patterning method according to a first embodiment of the present invention.
- the patterning method in this embodiment may include the following steps.
- a second mask layer 40 is formed on a first mask layer 30 .
- the material of the second mask layer 40 is different from the material of the first mask layer 30 .
- the second mask layer 40 may include a nitrogen doped silicon carbide layer
- the first mask layer 30 may be a silicon layer, but not limited thereto.
- the second mask layer 40 and the first mask layer 30 may include other materials capable of having different treated effects required in the subsequent trim process and/or the required etching selectivity in the subsequent etching process.
- the first mask layer 30 may be formed on a material layer 10 , and a cap layer 20 may be optionally formed between the first mask layer 30 and the material layer 10 .
- the material layer 10 and/or the cap layer 20 may be the etching target layer in the patterning method, but not limited thereto.
- the material layer 10 may be a structure composed of a single layer or multiple layers of conductive material and/or dielectric material layers.
- the material layer 10 may include a substrate 11 , a dielectric layer 12 , a first conductive layer 13 , and a second conductive layer 14 sequentially stacked in a thickness direction Z.
- the substrate 11 may include a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto.
- the dielectric layer 12 may include silicon oxide or other suitable dielectric materials.
- the first conductive layer 13 may include a non-metal conductive material such as polysilicon and amorphous silicon, or other suitable conductive materials.
- the second conductive layer 14 may include a metal material such as aluminum, tungsten, copper, titanium aluminide, or other suitable conductive materials.
- the cap layer 20 may include silicon nitride or other suitable insulation materials.
- a patterning process 91 is performed to the first mask layer 30 and the second mask layer 40 .
- the first mask layer 30 is patterned to be a first mask pattern 30 A by the patterning process 91
- the second mask layer 40 is patterned to be a second mask pattern 40 A by the patterning process 91 .
- the first mask layer 30 and the second mask layer 40 are patterned by the patterning process 91 concurrently, and the second mask pattern 40 A is formed on the first mask pattern 30 A accordingly.
- the projection pattern of the second mask pattern 40 A in the thickness direction Z of the material layer 10 may be substantially the same as the projection pattern of the first mask pattern 30 A in the thickness direction Z of the material layer 10 , but not limited thereto.
- the critical dimension (CD) of the second mask pattern 40 A formed by the patterning process 91 may be substantially equal to the CD of the first mask pattern 30 A formed by the patterning process 91 , and the width of the second mask pattern 40 A may be equal to the width of the first mask pattern 30 A (such as a first width W 1 shown in FIG. 2 ).
- the patterning process 91 may include forming an organic dielectric layer 51 , an anti-reflection layer 52 , and a patterned photoresist layer 53 sequentially on the second mask layer 40 and performing one or more etching steps for forming the first mask pattern 30 A and the second mask pattern 40 A.
- the organic dielectric layer 51 may include an organic distribution layer (ODL)
- the anti-reflection layer 52 may include a silicon-containing hard mask bottom anti-reflecting coating (SHB), but not limited thereto.
- a plurality of first openings H 1 penetrating the organic dielectric layer 51 , the second mask layer 40 , and the first mask layer 30 may be formed by the patterning process 91 for defining the first mask pattern 30 A, the second mask pattern 40 A, and a patterned organic dielectric layer 51 A overlapping with one another in the thickness direction Z, and the patterned organic dielectric layer 51 A may be removed after the patterning process 91 .
- the first mask pattern 30 A may include a plurality of first sub patterns P 1 separated from one another
- the second mask pattern 40 A may include a plurality of second sub patterns P 2 separated from one another.
- the second sub patterns P 2 and the first sub patterns P 1 may overlap one another in the thickness direction Z, and the width of each of the second sub patterns P 2 may be substantially equal to the width of each of the first sub patterns P 1 (such as the first width W 1 described above).
- a first trim process may be performed to the second mask pattern 40 A, and a width of the second mask pattern 40 A may be smaller than a width of the first mask pattern 30 A after the first trim process.
- the first trim process may include but is not limited to the following steps. As shown in FIG. 3 and FIG. 4 , a plasma treatment 92 may performed to the second mask pattern 40 A. A part of the second mask pattern 40 A is converted into a treated layer 41 by the plasma treatment 92 , and the treated layer 41 may encompass the second mask pattern 40 A. A removing process 93 may be performed after the plasma treatment 92 for removing the treated layer 41 , and the width of the second mask pattern 40 A (such as a second width W 2 shown in FIG.
- the first trim process may include the plasma treatment 92 and the removing process 93 configured to remove the treated layer after the plasma treatment 92 , but the present invention is not limited to this.
- the first trim process may include other suitable approaches for reducing the width of the second mask pattern 40 A.
- the plasma treatment 92 may include an oxidation treatment, a hydrogenation treatment, or other suitable types of plasma treatments, and a part of the second mask pattern 40 A may be oxidized or hydrogenated by the plasma treatment 92 to be the treated layer 41 . Therefore, the treated layer 41 may include an oxide layer, a hydrogenated layer, or other material layers different from the composition of the second mask pattern 40 A. Therefore, the removing process 93 configured to remove the treated layer 41 maybe modified depending on the type of the plasma treatment 92 and the material condition of the treated layer 41 . For instance, the removing process 93 may include an oxide removing process such as a dilute hydrofluoric acid (DHF) clean when the treated layer is an oxide layer, but not limited thereto.
- DHF dilute hydrofluoric acid
- the treated layer 41 may be formed by consuming a part of each of the second sub patterns P 2 in the plasma treatment 92 , and the width of each of the second sub patterns P 2 may be smaller than the width of each of the first sub patterns P 1 after the plasma treatment 92 accordingly. Therefore, the width of the second mask pattern 40 A may be substantially equal to the width of the first mask pattern 30 A before the plasma treatment, and the width of the second mask pattern 40 A after the plasma treatment 92 may be smaller than the width of the second mask pattern 40 A before the plasma treatment 92 .
- the width of the second mask pattern 40 A may be substantially equal to the width of the first mask pattern 30 A before the first trim process, and the width of the second mask pattern 40 A after the first trim process may be smaller than the width of the second mask pattern 40 A before the first trim process.
- the required thickness of the treated layer 41 may be obtained and the oxidized or hydrogenated degree of the first mask patterned 30 A in the plasma treatment 92 may be lowered by modifying the process condition of the plasma treatment 92 and the material difference between the second mask pattern 40 A and the first mask pattern 30 A.
- the oxidation treatment may be a thermal oxidation treatment or other suitable oxidation approaches, and the process temperature of the oxidation treatment may be higher than or equal to 250° C. for forming the required treated layer 41 .
- an oxygen pressure used in the oxidation treatment may be higher than or equal to 1 bar for avoiding that the material formed by oxidizing the second mask pattern 40 is evaporated directly and the consumption rate of the second mask pattern 40 is too high and out of control when the oxygen pressure used in the oxidation treatment is too low, but not limited thereto.
- the material of the second mask pattern 40 A is nitrogen doped silicon carbide
- the nitride doped in the silicon carbide may be used to generate lattice mismatch and enhance the effect of being oxidized, and other components in the nitrogen doped silicon carbide may be modified for generating the required effect of being oxidized.
- the carbon concentration in the nitrogen doped silicon carbide may be higher than or equal to 40%, but not limited thereto.
- the plasma treatment 92 is performed to the second mask pattern 40 A after the step of forming the first mask pattern 30 A and the second mask pattern 40 A so that the CD of the second mask pattern 40 A may be smaller than the CS of the first mask pattern 30 A.
- the second mask pattern 40 A with smaller CD may be formed on the first mask pattern 30 A by a self-aligned approach, and the second mask pattern 40 A with smaller CD may be used for further patterning the first mask pattern 30 and forming features with further smaller CD. The purpose of multiple patterning may be achieved accordingly.
- a cover layer 60 may be formed covering the first mask pattern 30 A and the second mask pattern 40 A after the first trim process described above.
- the cover layer 60 may include a planarization layer, and the space in the second mask pattern 40 A and the first mask pattern 30 A may be filled with the cover layer 60 .
- the space between the first sub patterns P 1 adjacent to one another and the space between the second sub patterns P 2 adjacent to one another maybe filled with the cover layer 60 , and the top surface of the cover layer 60 may be higher than the topmost surface of each of the second sub patterns P 2 in the thickness direction Z.
- the material of the cover layer 60 may be different from the material of the first mask pattern 30 A and the material of the second mask pattern 40 A.
- the cover layer 60 may include an organic distribution layer or other suitable materials having higher etching selectivity to the first mask pattern 30 A and the second mask pattern 40 A.
- an etching back process 94 is then performed to the cover layer 60 for removing a part of the cover layer 60 and exposing a top surface of the second mask pattern 40 A.
- the second mask pattern 40 A is removed for forming openings (such as second openings H 2 shown in FIG. 7 ) in the cover layer 60 .
- Each of the second openings H 2 exposes a part of the first mask pattern 30 A.
- the first mask pattern 30 A is patterned using the cover layer 60 as a mask after the step of removing the second mask pattern 40 A, and the first mask pattern 30 A is patterned to be a third mask pattern 30 B.
- each of the second openings H 2 may be formed self-aligned on the corresponding first sub pattern P 1 also because the second openings H 2 in the cover layer 50 are formed by removing the second sub patterns P 2 of the second mask pattern 40 A, and each of the first sub patterns P 1 may be partly exposed by the corresponding second opening H 2 and partly covered by the cover layer 60 . Therefore, an etching process 95 may be performed to the first mask pattern 30 A with the cover layer 60 having the second openings H 2 as an etching mask for removing the first mask pattern 30 A exposed by the second openings H 2 and forming the third mask pattern 30 B including a plurality of third sub patterns P 3 .
- the etching process 95 is performed to the first mask pattern 30 A after the step of forming the cover layer 60 .
- the etching process 95 may be performed using the cover layer 60 as a mask after the step of removing the second mask pattern 40 A, and the first mask pattern 30 A is etched to be the third mask pattern 30 B by the etching process 95 .
- Each of the first sub patterns P 1 may be etched for forming two third sub patterns P 3 , and the width of each of the third sub patterns P 3 (such as a third width W 3 shown in FIG. 8 ) may be smaller than the width of the first sub pattern P 1 accordingly.
- the third sub patterns P 3 formed by the second openings H 2 may have the same width substantially because the second openings H 2 may be formed self-aligned on the corresponding first sub patterns P 1 .
- a distance SP between two of the first sub patterns P 1 adjacent to each other may be substantially equal to the second width W 2 of each of the second sub patterns P 2 after the first trim process described above, and the width of each of the second openings H 2 may be substantially equal to the distance SP between two of the first sub patterns P 1 adjacent to each other, but not limited thereto.
- the width of each of the third sub patterns P 3 may be modified by the above-mentioned patterning process 91 in FIG. 2 and the above-mentioned plasma treatment 92 in FIG. 3 respectively, and the CD control of the patterning method may be improved.
- the cover layer 60 may be removed, and the pattern of the third mask pattern 30 B may be transferred to the cap layer 20 and the material layer 10 .
- an etching process may be used to transfer the pattern of the third mask pattern 30 B to the cap layer 20 first, and the patterned cap layer 20 may be used as an etching mask for etching the material layer 10 , but not limited thereto.
- the patterning method described above may be used to form bit line structures in a memory cell region of a semiconductor memory device, gate structures in a peripheral region of the semiconductor memory device, and/or other patterned structures in a semiconductor device, for example.
- the patterning method of the present invention may be used to control the process condition of the patterning process 91 shown in FIG.
- the shape, the size, and the pitch of the third mask pattern 30 used for patterning in the present invention may be modified by the related processes (such as the patterning process 91 shown in FIG. 2 , the plasma treatment 92 shown in FIG. 3 , and the etching process 95 shown in FIG. 9 ), the pattern may be transferred more ideally, and the manufacturing yield and the operation performance of the device formed by the patterning method of the present invention may be improved.
- FIG. 11 is a schematic drawing illustrating a patterning method according to a second embodiment of the present invention.
- FIG. 11 may be regarded as a schematic drawing in a step subsequent to 2
- FIG. 4 may be regarded as a schematic drawing in a step subsequent to FIG. 11 .
- the difference between the patterning method in this embodiment and the patterning method in the first embodiment is that the treated layer 41 in this embodiment may further cover a side surface of each of the first sub patterns P 1 .
- the first sub patterns may be oxidized or hydrogenated by the plasma treatment 92 also, but the oxidation level or the hydrogenation level of the first sub patterns P 1 may be lower than the oxidation level or the hydrogenation level of the second sub patterns P 2 . Therefore, the treated layer 41 on the side surfaces of the first sub patterns P 1 may be formed by consuming a part of each of the first sub patterns Pl, but not limited thereto.
- the CD of the first mask pattern 30 A may be further shrunk by the approach described above, and that is beneficial for forming tinier patterned structures.
- FIG. 12 is a schematic drawing illustrating a patterning method according to a third embodiment of the present invention.
- FIG. 12 may be regarded as a schematic drawing in a step subsequent to 6
- FIG. 8 may be regarded as a schematic drawing in a step subsequent to FIG. 12 .
- FIG. 6 , FIG. 12 , and FIG. 8 are schematic drawing in a patterning method according to a third embodiment of the present invention.
- FIG. 12 may be regarded as a schematic drawing in a step subsequent to 6
- FIG. 8 may be regarded as a schematic drawing in a step subsequent to FIG. 12 .
- the difference between the patterning method in this embodiment and the patterning method in the first embodiment is that the patterning method in this embodiment may further include performing a second trim process 96 to the cover layer 60 after the step of removing the second mask pattern 40 A and before the etching process 95 for further modifying the size of the second openings H 2 in the cover layer 60 .
- the second trim process 96 may be performed to the cover layer 60 before the step of patterning the first mask pattern 30 A for enlarging the size of the second openings H 2 in the cover layer 60 when the width of each of the second sub patterns P 2 in the second mask pattern 40 A is too small.
- the width of the second opening H 2 in the cover layer 60 after the second trim process 96 may be larger than the second width W 2 of each of the second sub patterns P 2 , but not limited thereto.
- the plasma treatment may be performed to the second mask pattern so that the width of the second mask pattern becomes smaller than the width of the first mask pattern.
- the second mask pattern with the smaller width may be formed self-aligned on the first mask pattern, and the second mask pattern may be used for further patterning the first mask pattern and forming a pattern and a patterned structure with smaller CD.
- the related problems cause by using the spacers for patterning in the conventional self-aligned double patterning may be avoided in the patterning method of the present invention.
- the etching recess loading control on the surface of the cap layer may be improved, and the size and the alignment pitch of the third mask pattern may be controlled more effectively by the patterning method of the present invention.
- the pattern may be transferred more ideally by the patterning method of the present invention, and the manufacturing yield and the operation performance of the device formed by the patterning method of the present invention may be improved accordingly.
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Abstract
Description
- The present invention relates to a patterning method, and more particularly, to a patterning method including a trim process.
- The integrated circuit (IC) is constructed by devices and interconnections, which are formed by patterned feature in a substrate or in different layers. In the fabrication of IC, photolithography process has been an essential technique. The photolithography process is applied to form designed patterns such as layout patterns on one or more photomask, and then to transfer such patterns to a photoresist layer on a film by exposure and development steps for precisely transferring the complicated layout pattern to a semiconductor chip.
- Along with miniaturization of semiconductor devices and progress in fabrication of semiconductor device, the conventional lithography process meets the bottleneck and the limitation. Therefore, the double patterning technique (DPT) is developed for manufacturing semiconductor devices with a further smaller dimension. Generally, the double patterning technique includes a litho-etch-litho-etch (LELE) double patterning approach, a litho-freeze-litho-etch (LFLE) double patterning approach, and a self-aligned double patterning (SADP) approach. In the conventional SADP approach, a spacer is formed on sidewalls of a feature formed by a photo-etching process, the feature is then removed, and the pattern of the spacer is then transferred to a material layer underneath the spacer for forming a pattern with a smaller critical dimension. However, the layout pattern cannot be ideally transferred because there are still many manufacturing issues in the conventional SADP approach, such as the uniformity of etching recessing loading and spacer bending issue. The manufacturing yield and the operation performance of the device formed by the conventional SADP approach are influenced accordingly.
- A patterning method is provided in the present invention. A first mask layer and a second mask layer are patterned concurrently for becoming a first mask pattern and a second mask pattern respectively. A first trim process is performed to the second mask pattern so that a width of the second mask pattern becomes smaller than a width of the first mask pattern. The second mask pattern with the smaller width may be formed self-aligned on the first mask pattern, and the second mask pattern may be used to form a pattern with a critical dimension (CD) smaller than the first mask pattern. The multiple patterning effect may be realized accordingly.
- According to an embodiment of the present invention, a patterning method is provided. The patterning method includes the following steps. A second mask layer is formed on a first mask layer. A patterning process is performed to the first mask layer and the second mask layer. The first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern. A first trim process is performed to the second mask pattern. A width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process. A cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process. An etching process is performed to the first mask pattern after the step of forming the cover layer.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-10 are schematic drawings illustrating a patterning method according to a first embodiment of the present invention, whereinFIG. 2 is a schematic drawing in a step subsequent toFIG. 1 ,FIG. 3 is a schematic drawing in a step subsequent toFIG. 2 ,FIG. 4 is a schematic drawing in a step subsequent toFIG. 3 ,FIG. 5 is a schematic drawing in a step subsequent toFIG. 4 ,FIG. 6 is a schematic drawing in a step subsequent toFIG. 5 ,FIG. 7 is a schematic drawing in a step subsequent toFIG. 6 ,FIG. 8 is a schematic drawing in a step subsequent toFIG. 7 ,FIG. 9 is a schematic drawing in a step subsequent toFIG. 8 , andFIG. 10 is a schematic drawing in a step subsequent toFIG. 9 . -
FIG. 11 is a schematic drawing illustrating a patterning method according to a second embodiment of the present invention. -
FIG. 12 is a schematic drawing illustrating a patterning method according to a third embodiment of the present invention. - Please refer to
FIGS. 1-10 .FIGS. 1-10 are schematic drawings illustrating a patterning method according to a first embodiment of the present invention. The patterning method in this embodiment may include the following steps. As shown inFIG. 1 , asecond mask layer 40 is formed on afirst mask layer 30. The material of thesecond mask layer 40 is different from the material of thefirst mask layer 30. For example, thesecond mask layer 40 may include a nitrogen doped silicon carbide layer, and thefirst mask layer 30 may be a silicon layer, but not limited thereto. In some embodiments, thesecond mask layer 40 and thefirst mask layer 30 may include other materials capable of having different treated effects required in the subsequent trim process and/or the required etching selectivity in the subsequent etching process. - Additionally, in some embodiments, the
first mask layer 30 may be formed on a material layer 10, and acap layer 20 may be optionally formed between thefirst mask layer 30 and the material layer 10. The material layer 10 and/or thecap layer 20 may be the etching target layer in the patterning method, but not limited thereto. For example, the material layer 10 may be a structure composed of a single layer or multiple layers of conductive material and/or dielectric material layers. For instance, the material layer 10 may include asubstrate 11, a dielectric layer 12, a firstconductive layer 13, and a secondconductive layer 14 sequentially stacked in a thickness direction Z. In some embodiments, thesubstrate 11 may include a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. The dielectric layer 12 may include silicon oxide or other suitable dielectric materials. The firstconductive layer 13 may include a non-metal conductive material such as polysilicon and amorphous silicon, or other suitable conductive materials. The secondconductive layer 14 may include a metal material such as aluminum, tungsten, copper, titanium aluminide, or other suitable conductive materials. Thecap layer 20 may include silicon nitride or other suitable insulation materials. - As shown in
FIG. 1 andFIG. 2 , apatterning process 91 is performed to thefirst mask layer 30 and thesecond mask layer 40. Thefirst mask layer 30 is patterned to be afirst mask pattern 30A by thepatterning process 91, and thesecond mask layer 40 is patterned to be asecond mask pattern 40A by thepatterning process 91. In other words, thefirst mask layer 30 and thesecond mask layer 40 are patterned by thepatterning process 91 concurrently, and thesecond mask pattern 40A is formed on thefirst mask pattern 30A accordingly. The projection pattern of thesecond mask pattern 40A in the thickness direction Z of the material layer 10 may be substantially the same as the projection pattern of thefirst mask pattern 30A in the thickness direction Z of the material layer 10, but not limited thereto. Therefore, the critical dimension (CD) of thesecond mask pattern 40A formed by thepatterning process 91 may be substantially equal to the CD of thefirst mask pattern 30A formed by thepatterning process 91, and the width of thesecond mask pattern 40A may be equal to the width of thefirst mask pattern 30A (such as a first width W1 shown inFIG. 2 ). - In some embodiments, the
patterning process 91 may include forming an organicdielectric layer 51, ananti-reflection layer 52, and a patternedphotoresist layer 53 sequentially on thesecond mask layer 40 and performing one or more etching steps for forming thefirst mask pattern 30A and thesecond mask pattern 40A. The organicdielectric layer 51 may include an organic distribution layer (ODL), and theanti-reflection layer 52 may include a silicon-containing hard mask bottom anti-reflecting coating (SHB), but not limited thereto. A plurality of first openings H1 penetrating the organicdielectric layer 51, thesecond mask layer 40, and thefirst mask layer 30 may be formed by thepatterning process 91 for defining thefirst mask pattern 30A, thesecond mask pattern 40A, and a patterned organicdielectric layer 51A overlapping with one another in the thickness direction Z, and the patterned organicdielectric layer 51A may be removed after thepatterning process 91. - In some embodiments, the
first mask pattern 30A may include a plurality of first sub patterns P1 separated from one another, and thesecond mask pattern 40A may include a plurality of second sub patterns P2 separated from one another. The second sub patterns P2 and the first sub patterns P1 may overlap one another in the thickness direction Z, and the width of each of the second sub patterns P2 may be substantially equal to the width of each of the first sub patterns P1 (such as the first width W1 described above). - Subsequently, a first trim process may be performed to the
second mask pattern 40A, and a width of thesecond mask pattern 40A may be smaller than a width of thefirst mask pattern 30A after the first trim process. In some embodiments, the first trim process may include but is not limited to the following steps. As shown inFIG. 3 andFIG. 4 , aplasma treatment 92 may performed to thesecond mask pattern 40A. A part of thesecond mask pattern 40A is converted into a treatedlayer 41 by theplasma treatment 92, and the treatedlayer 41 may encompass thesecond mask pattern 40A. A removingprocess 93 may be performed after theplasma treatment 92 for removing the treatedlayer 41, and the width of thesecond mask pattern 40A (such as a second width W2 shown inFIG. 4 ) is smaller than the width of thefirst mask pattern 30A (such as the first width W1 shown inFIG. 4 ) after the step of removing the treatedlayer 41. In other words, the first trim process may include theplasma treatment 92 and the removingprocess 93 configured to remove the treated layer after theplasma treatment 92, but the present invention is not limited to this. In some embodiments, the first trim process may include other suitable approaches for reducing the width of thesecond mask pattern 40A. - In some embodiments, the
plasma treatment 92 may include an oxidation treatment, a hydrogenation treatment, or other suitable types of plasma treatments, and a part of thesecond mask pattern 40A may be oxidized or hydrogenated by theplasma treatment 92 to be the treatedlayer 41. Therefore, the treatedlayer 41 may include an oxide layer, a hydrogenated layer, or other material layers different from the composition of thesecond mask pattern 40A. Therefore, the removingprocess 93 configured to remove the treatedlayer 41 maybe modified depending on the type of theplasma treatment 92 and the material condition of the treatedlayer 41. For instance, the removingprocess 93 may include an oxide removing process such as a dilute hydrofluoric acid (DHF) clean when the treated layer is an oxide layer, but not limited thereto. - In some embodiments, the treated
layer 41 may be formed by consuming a part of each of the second sub patterns P2 in theplasma treatment 92, and the width of each of the second sub patterns P2 may be smaller than the width of each of the first sub patterns P1 after theplasma treatment 92 accordingly. Therefore, the width of thesecond mask pattern 40A may be substantially equal to the width of thefirst mask pattern 30A before the plasma treatment, and the width of thesecond mask pattern 40A after theplasma treatment 92 may be smaller than the width of thesecond mask pattern 40A before theplasma treatment 92. In other words, the width of thesecond mask pattern 40A may be substantially equal to the width of thefirst mask pattern 30A before the first trim process, and the width of thesecond mask pattern 40A after the first trim process may be smaller than the width of thesecond mask pattern 40A before the first trim process. - It is worth noting that the required thickness of the treated
layer 41 may be obtained and the oxidized or hydrogenated degree of the first mask patterned 30A in theplasma treatment 92 may be lowered by modifying the process condition of theplasma treatment 92 and the material difference between thesecond mask pattern 40A and thefirst mask pattern 30A. For example, when theplasma treatment 92 is an oxidation treatment, the oxidation treatment may be a thermal oxidation treatment or other suitable oxidation approaches, and the process temperature of the oxidation treatment may be higher than or equal to 250° C. for forming the required treatedlayer 41. Additionally, an oxygen pressure used in the oxidation treatment may be higher than or equal to 1 bar for avoiding that the material formed by oxidizing thesecond mask pattern 40 is evaporated directly and the consumption rate of thesecond mask pattern 40 is too high and out of control when the oxygen pressure used in the oxidation treatment is too low, but not limited thereto. Additionally, when the material of thesecond mask pattern 40A is nitrogen doped silicon carbide, the nitride doped in the silicon carbide may be used to generate lattice mismatch and enhance the effect of being oxidized, and other components in the nitrogen doped silicon carbide may be modified for generating the required effect of being oxidized. For instance, the carbon concentration in the nitrogen doped silicon carbide may be higher than or equal to 40%, but not limited thereto. - By the manufacturing method described above, the
plasma treatment 92 is performed to thesecond mask pattern 40A after the step of forming thefirst mask pattern 30A and thesecond mask pattern 40A so that the CD of thesecond mask pattern 40A may be smaller than the CS of thefirst mask pattern 30A. Thesecond mask pattern 40A with smaller CD may be formed on thefirst mask pattern 30A by a self-aligned approach, and thesecond mask pattern 40A with smaller CD may be used for further patterning thefirst mask pattern 30 and forming features with further smaller CD. The purpose of multiple patterning may be achieved accordingly. - For example, as shown in
FIGS. 3-5 , acover layer 60 may be formed covering thefirst mask pattern 30A and thesecond mask pattern 40A after the first trim process described above. In some embodiments, thecover layer 60 may include a planarization layer, and the space in thesecond mask pattern 40A and thefirst mask pattern 30A may be filled with thecover layer 60. In other words, the space between the first sub patterns P1 adjacent to one another and the space between the second sub patterns P2 adjacent to one another maybe filled with thecover layer 60, and the top surface of thecover layer 60 may be higher than the topmost surface of each of the second sub patterns P2 in the thickness direction Z. The material of thecover layer 60 may be different from the material of thefirst mask pattern 30A and the material of thesecond mask pattern 40A. For example, thecover layer 60 may include an organic distribution layer or other suitable materials having higher etching selectivity to thefirst mask pattern 30A and thesecond mask pattern 40A. - As shown in
FIG. 5 andFIG. 6 , an etching backprocess 94 is then performed to thecover layer 60 for removing a part of thecover layer 60 and exposing a top surface of thesecond mask pattern 40A. Subsequently, as shown inFIG. 6 andFIG. 7 , thesecond mask pattern 40A is removed for forming openings (such as second openings H2 shown inFIG. 7 ) in thecover layer 60. Each of the second openings H2 exposes a part of thefirst mask pattern 30A. As shown inFIGS. 6-8 , thefirst mask pattern 30A is patterned using thecover layer 60 as a mask after the step of removing thesecond mask pattern 40A, and thefirst mask pattern 30A is patterned to be athird mask pattern 30B. - Specifically, each of the second openings H2 may be formed self-aligned on the corresponding first sub pattern P1 also because the second openings H2 in the
cover layer 50 are formed by removing the second sub patterns P2 of thesecond mask pattern 40A, and each of the first sub patterns P1 may be partly exposed by the corresponding second opening H2 and partly covered by thecover layer 60. Therefore, anetching process 95 may be performed to thefirst mask pattern 30A with thecover layer 60 having the second openings H2 as an etching mask for removing thefirst mask pattern 30A exposed by the second openings H2 and forming thethird mask pattern 30B including a plurality of third sub patterns P3. Theetching process 95 is performed to thefirst mask pattern 30A after the step of forming thecover layer 60. Theetching process 95 may be performed using thecover layer 60 as a mask after the step of removing thesecond mask pattern 40A, and thefirst mask pattern 30A is etched to be thethird mask pattern 30B by theetching process 95. - Each of the first sub patterns P1 may be etched for forming two third sub patterns P3, and the width of each of the third sub patterns P3 (such as a third width W3 shown in
FIG. 8 ) may be smaller than the width of the first sub pattern P1 accordingly. The third sub patterns P3 formed by the second openings H2 may have the same width substantially because the second openings H2 may be formed self-aligned on the corresponding first sub patterns P1. Additionally, in some embodiments, if the third sub patterns P3 are going to be aligned uniformly by the same spacing and the same pitch, a distance SP between two of the first sub patterns P1 adjacent to each other may be substantially equal to the second width W2 of each of the second sub patterns P2 after the first trim process described above, and the width of each of the second openings H2 may be substantially equal to the distance SP between two of the first sub patterns P1 adjacent to each other, but not limited thereto. In addition, the width of each of the third sub patterns P3 may be modified by the above-mentionedpatterning process 91 inFIG. 2 and the above-mentionedplasma treatment 92 inFIG. 3 respectively, and the CD control of the patterning method may be improved. - As shown in
FIGS. 8-10 , after theetching process 95, thecover layer 60 may be removed, and the pattern of thethird mask pattern 30B may be transferred to thecap layer 20 and the material layer 10. In some embodiments, an etching process may be used to transfer the pattern of thethird mask pattern 30B to thecap layer 20 first, and the patternedcap layer 20 may be used as an etching mask for etching the material layer 10, but not limited thereto. Additionally, in some embodiments, the patterning method described above may be used to form bit line structures in a memory cell region of a semiconductor memory device, gate structures in a peripheral region of the semiconductor memory device, and/or other patterned structures in a semiconductor device, for example. - Additionally, it is worth noting that, as shown in
FIG. 2 ,FIG. 8 , andFIG. 9 , there may be etching recesses on the surface of thecap layer 20 because of the influence of the processes performed before the step of transferring the pattern of thethird mask pattern 30B to thecap layer 20 and the material layer 10. The performance of transferring the pattern of thethird mask pattern 30B to thecap layer 20 and/or the material layer 10 may be affected by the etching recesses on the surface of thecap layer 20 between the third sub patterns P3 especially when the depths of the etching recesses are not uniform. However, the patterning method of the present invention may be used to control the process condition of thepatterning process 91 shown inFIG. 2 and the process condition of theetching process 95 shown inFIG. 8 , and the level of the etching recesses on the surface of thecap layer 20 may be uniform accordingly. Additionally, spacers formed for patterning in the conventional self-aligned double patterning (SADP) approach are not required in the patterning method of the present invention, and related problems cause by using the spacers for patterning (such as the spacer bending issue) may be avoided accordingly. Comparatively, the shape, the size, and the pitch of thethird mask pattern 30 used for patterning in the present invention may be modified by the related processes (such as thepatterning process 91 shown inFIG. 2 , theplasma treatment 92 shown inFIG. 3 , and theetching process 95 shown inFIG. 9 ), the pattern may be transferred more ideally, and the manufacturing yield and the operation performance of the device formed by the patterning method of the present invention may be improved. - The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.
- Please refer to
FIG. 2 ,FIG. 11 , andFIG. 4 .FIG. 11 is a schematic drawing illustrating a patterning method according to a second embodiment of the present invention.FIG. 11 may be regarded as a schematic drawing in a step subsequent to 2, andFIG. 4 may be regarded as a schematic drawing in a step subsequent toFIG. 11 . As shown inFIG. 2 ,FIG. 11 , andFIG. 4 , the difference between the patterning method in this embodiment and the patterning method in the first embodiment is that the treatedlayer 41 in this embodiment may further cover a side surface of each of the first sub patterns P1. In some embodiments, the first sub patterns may be oxidized or hydrogenated by theplasma treatment 92 also, but the oxidation level or the hydrogenation level of the first sub patterns P1 may be lower than the oxidation level or the hydrogenation level of the second sub patterns P2. Therefore, the treatedlayer 41 on the side surfaces of the first sub patterns P1 may be formed by consuming a part of each of the first sub patterns Pl, but not limited thereto. The CD of thefirst mask pattern 30A may be further shrunk by the approach described above, and that is beneficial for forming tinier patterned structures. - Please refer to
FIG. 6 ,FIG. 12 , andFIG. 8 .FIG. 12 is a schematic drawing illustrating a patterning method according to a third embodiment of the present invention.FIG. 12 may be regarded as a schematic drawing in a step subsequent to 6, andFIG. 8 may be regarded as a schematic drawing in a step subsequent toFIG. 12 . As shown inFIG. 6 ,FIG. 12 , andFIG. 8 , the difference between the patterning method in this embodiment and the patterning method in the first embodiment is that the patterning method in this embodiment may further include performing asecond trim process 96 to thecover layer 60 after the step of removing thesecond mask pattern 40A and before theetching process 95 for further modifying the size of the second openings H2 in thecover layer 60. For instance, thesecond trim process 96 may be performed to thecover layer 60 before the step of patterning thefirst mask pattern 30A for enlarging the size of the second openings H2 in thecover layer 60 when the width of each of the second sub patterns P2 in thesecond mask pattern 40A is too small. Therefore, the width of the second opening H2 in thecover layer 60 after the second trim process 96 (such as a fourth width W4 shown inFIG. 12 ) may be larger than the second width W2 of each of the second sub patterns P2, but not limited thereto. - To summarize the above descriptions, in the patterning method of the present invention, the plasma treatment may be performed to the second mask pattern so that the width of the second mask pattern becomes smaller than the width of the first mask pattern. The second mask pattern with the smaller width may be formed self-aligned on the first mask pattern, and the second mask pattern may be used for further patterning the first mask pattern and forming a pattern and a patterned structure with smaller CD. Additionally, the related problems cause by using the spacers for patterning in the conventional self-aligned double patterning may be avoided in the patterning method of the present invention. The etching recess loading control on the surface of the cap layer may be improved, and the size and the alignment pitch of the third mask pattern may be controlled more effectively by the patterning method of the present invention. The pattern may be transferred more ideally by the patterning method of the present invention, and the manufacturing yield and the operation performance of the device formed by the patterning method of the present invention may be improved accordingly.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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US20220044933A1 (en) * | 2019-06-13 | 2022-02-10 | Nanya Technology Corporation | Semiconductor device with reduced critical dimensions |
US12009212B2 (en) * | 2021-10-26 | 2024-06-11 | Nanya Technology Corporation | Semiconductor device with reduced critical dimensions |
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US6867116B1 (en) * | 2003-11-10 | 2005-03-15 | Macronix International Co., Ltd. | Fabrication method of sub-resolution pitch for integrated circuits |
US7183205B2 (en) * | 2004-06-08 | 2007-02-27 | Macronix International Co., Ltd. | Method of pitch dimension shrinkage |
US7611980B2 (en) * | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
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US20130344702A1 (en) * | 2011-03-04 | 2013-12-26 | Tokyo Electron Limited | Method of etching silicon nitride films |
US9613806B2 (en) * | 2013-09-04 | 2017-04-04 | Sandisk Technologies Llc | Triple patterning NAND flash memory |
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US9165765B1 (en) * | 2014-09-09 | 2015-10-20 | Tokyo Electron Limited | Method for patterning differing critical dimensions at sub-resolution scales |
US9576817B1 (en) * | 2015-12-03 | 2017-02-21 | International Business Machines Corporation | Pattern decomposition for directed self assembly patterns templated by sidewall image transfer |
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